Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2700959

1

T2

81

T4

59

T6

44

full_word

1698598

1

T2

9

T3

2

T4

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4399247	1			T2	90		T3	2		T4	69
auto[TlIntgErrCmd]	119	1			T61	6		T62	3		T63	3
auto[TlIntgErrData]	110	1			T61	2		T62	4		T63	6
auto[TlIntgErrBoth]	81	1			T61	2		T62	3		T63	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692278

1

T2

90

T3

2

T4

69

auto[1]

3707279

1

T15

424886

T16

99054

T17

425836

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	291779	1			T2	81		T4	59		T6	44
auto[TlIntgErrNone]	partial	auto[1]	2408891	1			T15	277256		T16	64296		T17	275879
auto[TlIntgErrNone]	full_word	auto[0]	400383	1			T2	9		T3	2		T4	10
auto[TlIntgErrNone]	full_word	auto[1]	1298194	1			T15	147630		T16	34758		T17	149957
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T61	2		T62	1		T63	2
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T61	4		T62	2		T63	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T116	1		T124	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T117	1		T120	1		T125	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T62	1		T63	1		T115	2
auto[TlIntgErrData]	partial	auto[1]	64	1			T61	2		T62	1		T63	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T62	1		T117	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T62	1		T63	1		T124	2
auto[TlIntgErrBoth]	partial	auto[0]	26	1			T62	1		T63	1		T115	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T61	1		T62	2		T115	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T126	1		T127	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T61	1		T116	1		T128	1