Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1947217

1

T2

57

T3

68

T6

60

full_word

1237436

1

T2

6

T3

3

T6

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3184373	1			T2	63		T3	71		T6	65
auto[TlIntgErrCmd]	93	1			T55	2		T56	2		T57	11
auto[TlIntgErrData]	83	1			T55	4		T56	5		T57	5
auto[TlIntgErrBoth]	104	1			T55	4		T56	3		T57	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

514675

1

T2

63

T3

71

T6

65

auto[1]

2669978

1

T12

215066

T13

76182

T14

148071

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	221688	1			T2	57		T3	68		T6	60
auto[TlIntgErrNone]	partial	auto[1]	1725269	1			T12	138645		T13	48899		T14	95224
auto[TlIntgErrNone]	full_word	auto[0]	292879	1			T2	6		T3	3		T6	5
auto[TlIntgErrNone]	full_word	auto[1]	944537	1			T12	76421		T13	27283		T14	52847
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T57	1		T105	2		T106	3
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T55	1		T56	2		T57	9
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T57	1		T107	1		T112	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T55	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	35	1			T55	1		T56	3		T57	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T55	2		T56	2		T57	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T55	1		T57	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T105	1		T113	1		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T55	2		T56	1		T57	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T55	1		T56	1		T57	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T55	1		T115	1		T108	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T56	1		T106	2		T108	1