Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65821	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1552969

1

T1

25

T6

4

T7

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	425679	1			T1	272		T6	46		T7	3
values[0x0]	585978	1			T12	27066		T14	18325		T15	12580
values[0x1]	607133	1			T12	27815		T14	19063		T15	12742

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33847	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1584943

1

T1

159

T6

29

T7

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6794	1			T1	1		T11	2		T12	284
valid_sources[0x01]	6517	1			T16	1		T12	296		T14	243
valid_sources[0x02]	6110	1			T12	300		T14	212		T15	145
valid_sources[0x03]	6159	1			T6	3		T16	1		T12	290
valid_sources[0x04]	6445	1			T1	5		T16	1		T12	281
valid_sources[0x05]	6349	1			T12	272		T14	235		T15	153
valid_sources[0x06]	6090	1			T12	256		T14	196		T15	121
valid_sources[0x07]	6486	1			T6	4		T16	2		T12	266
valid_sources[0x08]	6331	1			T1	2		T16	1		T12	300
valid_sources[0x09]	6372	1			T12	274		T14	193		T15	134
valid_sources[0x0a]	6540	1			T12	310		T19	2		T14	177
valid_sources[0x0b]	6367	1			T12	306		T18	2		T14	187
valid_sources[0x0c]	5922	1			T1	1		T12	277		T14	189
valid_sources[0x0d]	7089	1			T16	1		T12	300		T14	175
valid_sources[0x0e]	6416	1			T1	7		T12	303		T19	2
valid_sources[0x0f]	6056	1			T12	295		T19	2		T14	199
valid_sources[0x10]	6173	1			T1	5		T12	337		T14	170
valid_sources[0x11]	6411	1			T6	2		T12	272		T19	2
valid_sources[0x12]	6171	1			T1	8		T16	1		T12	274
valid_sources[0x13]	6246	1			T1	1		T11	2		T12	285
valid_sources[0x14]	6616	1			T1	9		T11	2		T12	295
valid_sources[0x15]	6824	1			T12	303		T19	1		T18	1
valid_sources[0x16]	5838	1			T12	319		T14	204		T15	130
valid_sources[0x17]	6444	1			T12	288		T18	1		T14	185
valid_sources[0x18]	5996	1			T11	1		T12	306		T14	194
valid_sources[0x19]	5987	1			T1	6		T16	2		T12	279
valid_sources[0x1a]	6210	1			T12	296		T19	1		T18	1
valid_sources[0x1b]	6127	1			T12	286		T18	2		T14	173
valid_sources[0x1c]	6273	1			T11	1		T16	2		T12	274
valid_sources[0x1d]	7109	1			T1	3		T12	296		T18	1
valid_sources[0x1e]	6105	1			T12	287		T18	3		T14	198
valid_sources[0x1f]	6220	1			T11	2		T12	272		T14	181
valid_sources[0x20]	6254	1			T16	2		T12	251		T14	204
valid_sources[0x21]	6067	1			T12	276		T14	210		T15	120
valid_sources[0x22]	6322	1			T1	1		T12	269		T19	1
valid_sources[0x23]	6364	1			T12	297		T14	225		T15	132
valid_sources[0x24]	5879	1			T11	1		T12	275		T19	2
valid_sources[0x25]	6290	1			T16	3		T12	297		T14	194
valid_sources[0x26]	5911	1			T16	2		T12	271		T19	1
valid_sources[0x27]	6365	1			T1	2		T12	297		T19	1
valid_sources[0x28]	6456	1			T1	4		T12	307		T14	202
valid_sources[0x29]	6564	1			T12	282		T19	1		T14	206
valid_sources[0x2a]	6487	1			T11	2		T12	303		T19	2
valid_sources[0x2b]	7352	1			T11	1		T12	276		T19	1
valid_sources[0x2c]	6323	1			T1	9		T12	296		T18	4
valid_sources[0x2d]	5996	1			T12	248		T19	1		T14	200
valid_sources[0x2e]	6042	1			T12	263		T54	16		T14	204
valid_sources[0x2f]	6269	1			T12	297		T19	1		T14	197
valid_sources[0x30]	6138	1			T1	1		T12	298		T18	2
valid_sources[0x31]	6329	1			T1	1		T12	313		T19	3
valid_sources[0x32]	6647	1			T6	1		T12	301		T18	2
valid_sources[0x33]	6523	1			T1	2		T16	3		T12	265
valid_sources[0x34]	6098	1			T12	267		T14	198		T15	143
valid_sources[0x35]	6559	1			T1	2		T12	286		T21	6
valid_sources[0x36]	6189	1			T1	6		T11	1		T16	2
valid_sources[0x37]	6161	1			T16	1		T12	272		T14	179
valid_sources[0x38]	6382	1			T12	267		T14	209		T15	134
valid_sources[0x39]	6429	1			T12	286		T14	205		T15	143
valid_sources[0x3a]	6171	1			T11	1		T12	270		T19	1
valid_sources[0x3b]	6129	1			T11	2		T12	285		T14	188
valid_sources[0x3c]	6118	1			T11	4		T12	288		T19	2
valid_sources[0x3d]	6145	1			T12	267		T18	4		T14	199
valid_sources[0x3e]	6131	1			T12	280		T14	189		T15	170
valid_sources[0x3f]	6184	1			T1	4		T11	2		T12	285
valid_sources[0x40]	6527	1			T1	1		T11	1		T12	274
valid_sources[0x41]	6354	1			T1	2		T11	4		T12	316
valid_sources[0x42]	6409	1			T11	1		T16	1		T12	313
valid_sources[0x43]	6529	1			T11	1		T12	295		T14	201
valid_sources[0x44]	6236	1			T12	282		T14	220		T56	1
valid_sources[0x45]	6745	1			T12	272		T18	1		T14	220
valid_sources[0x46]	6001	1			T16	2		T12	317		T19	2
valid_sources[0x47]	6251	1			T12	290		T14	199		T15	146
valid_sources[0x48]	6671	1			T12	268		T19	1		T14	184
valid_sources[0x49]	6145	1			T1	7		T7	1		T12	314
valid_sources[0x4a]	6901	1			T1	10		T12	302		T14	197
valid_sources[0x4b]	6519	1			T16	3		T12	288		T19	4
valid_sources[0x4c]	6330	1			T12	256		T14	188		T15	148
valid_sources[0x4d]	6211	1			T16	3		T12	305		T18	2
valid_sources[0x4e]	6746	1			T12	309		T19	1		T14	181
valid_sources[0x4f]	5778	1			T12	257		T18	1		T14	198
valid_sources[0x50]	6219	1			T12	307		T19	1		T14	186
valid_sources[0x51]	6197	1			T12	282		T19	1		T18	2
valid_sources[0x52]	6410	1			T11	1		T12	282		T19	1
valid_sources[0x53]	5774	1			T1	1		T12	272		T14	221
valid_sources[0x54]	6626	1			T11	1		T12	289		T19	1
valid_sources[0x55]	6105	1			T11	1		T12	309		T21	1
valid_sources[0x56]	6459	1			T12	276		T19	1		T14	209
valid_sources[0x57]	6367	1			T6	1		T12	289		T14	189
valid_sources[0x58]	6787	1			T16	1		T12	258		T18	2
valid_sources[0x59]	6755	1			T11	3		T12	296		T19	1
valid_sources[0x5a]	6079	1			T6	5		T12	276		T14	168
valid_sources[0x5b]	5818	1			T1	2		T11	2		T12	265
valid_sources[0x5c]	6123	1			T12	267		T19	2		T14	194
valid_sources[0x5d]	6415	1			T1	2		T6	1		T12	281
valid_sources[0x5e]	6363	1			T1	2		T16	1		T12	313
valid_sources[0x5f]	5927	1			T1	3		T12	302		T18	1
valid_sources[0x60]	6418	1			T1	4		T11	1		T12	305
valid_sources[0x61]	6202	1			T1	4		T12	277		T14	181
valid_sources[0x62]	5937	1			T1	1		T12	281		T19	1
valid_sources[0x63]	6288	1			T12	293		T14	182		T15	117
valid_sources[0x64]	6233	1			T1	4		T12	317		T14	209
valid_sources[0x65]	6595	1			T16	1		T12	283		T18	1
valid_sources[0x66]	6652	1			T12	298		T14	187		T15	137
valid_sources[0x67]	6330	1			T12	288		T18	1		T14	190
valid_sources[0x68]	6370	1			T11	2		T12	298		T18	1
valid_sources[0x69]	6147	1			T12	299		T19	1		T14	191
valid_sources[0x6a]	6219	1			T1	4		T12	290		T19	3
valid_sources[0x6b]	6556	1			T11	1		T12	272		T14	204
valid_sources[0x6c]	6551	1			T11	1		T12	276		T14	213
valid_sources[0x6d]	6571	1			T11	3		T12	289		T18	3
valid_sources[0x6e]	6358	1			T12	266		T19	1		T14	207
valid_sources[0x6f]	6509	1			T12	314		T54	10		T14	207
valid_sources[0x70]	6245	1			T1	3		T12	297		T18	1
valid_sources[0x71]	6350	1			T16	1		T12	273		T18	3
valid_sources[0x72]	6486	1			T1	4		T12	291		T14	187
valid_sources[0x73]	6184	1			T6	5		T12	290		T18	4
valid_sources[0x74]	6195	1			T12	281		T21	3		T14	194
valid_sources[0x75]	7061	1			T11	1		T16	2		T12	300
valid_sources[0x76]	6486	1			T1	1		T11	1		T12	282
valid_sources[0x77]	6393	1			T11	1		T16	2		T12	281
valid_sources[0x78]	6282	1			T6	2		T12	290		T18	1
valid_sources[0x79]	6588	1			T6	5		T12	287		T19	4
valid_sources[0x7a]	6054	1			T12	278		T14	199		T15	125
valid_sources[0x7b]	6638	1			T1	2		T16	1		T12	295
valid_sources[0x7c]	6420	1			T11	1		T12	315		T18	1
valid_sources[0x7d]	6581	1			T7	1		T11	2		T12	297
valid_sources[0x7e]	6103	1			T1	6		T16	2		T12	272
valid_sources[0x7f]	7091	1			T1	2		T16	1		T12	306
valid_sources[0x80]	6723	1			T16	1		T12	311		T14	199

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

390805

1

T1

25

T6

4

T7

3

values[0x0]

all_enables

biggest_size

580966

1

T12

26788

T14

18172

T15

12463

values[0x1]

all_enables

biggest_size

581198

1

T12

26568

T14

18270

T15

12186

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	116945	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1196787

1

T2

1

T3

2

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	329372	1			T2	1		T5	1		T6	32
values[0x0]	456151	1			T3	11		T4	7		T8	3
values[0x1]	528209	1			T3	4		T4	3		T8	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1260889

1

T2

1

T3

4

T4

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4918	1			T12	212		T21	1		T54	1
valid_sources[0x01]	4551	1			T12	266		T14	137		T15	91
valid_sources[0x02]	5303	1			T12	177		T14	182		T15	95
valid_sources[0x03]	5169	1			T7	2		T10	9		T16	2
valid_sources[0x04]	5766	1			T12	222		T54	1		T14	126
valid_sources[0x05]	5480	1			T12	284		T14	163		T15	123
valid_sources[0x06]	5643	1			T12	172		T54	1		T14	171
valid_sources[0x07]	5164	1			T12	217		T14	153		T15	110
valid_sources[0x08]	5573	1			T6	1		T7	2		T12	248
valid_sources[0x09]	5400	1			T12	285		T14	162		T15	146
valid_sources[0x0a]	5118	1			T12	271		T14	162		T15	72
valid_sources[0x0b]	6631	1			T12	208		T14	183		T15	107
valid_sources[0x0c]	5572	1			T6	1		T16	1		T12	165
valid_sources[0x0d]	5358	1			T6	1		T12	201		T18	3
valid_sources[0x0e]	5519	1			T12	244		T14	169		T15	138
valid_sources[0x0f]	5303	1			T12	244		T18	1		T14	143
valid_sources[0x10]	5387	1			T12	325		T14	148		T15	110
valid_sources[0x11]	5215	1			T12	268		T14	163		T15	85
valid_sources[0x12]	6066	1			T12	251		T21	1		T14	159
valid_sources[0x13]	4851	1			T12	179		T21	2		T14	160
valid_sources[0x14]	4294	1			T12	180		T14	143		T15	93
valid_sources[0x15]	5653	1			T12	227		T54	1		T14	183
valid_sources[0x16]	5296	1			T16	1		T12	221		T14	161
valid_sources[0x17]	5245	1			T12	238		T14	158		T15	127
valid_sources[0x18]	5136	1			T6	2		T12	215		T18	2
valid_sources[0x19]	5180	1			T12	255		T14	140		T15	167
valid_sources[0x1a]	5883	1			T12	219		T14	165		T15	133
valid_sources[0x1b]	5070	1			T12	208		T14	151		T15	86
valid_sources[0x1c]	5350	1			T12	233		T14	169		T15	123
valid_sources[0x1d]	4836	1			T6	2		T12	245		T54	2
valid_sources[0x1e]	4919	1			T12	200		T18	1		T14	180
valid_sources[0x1f]	6065	1			T6	1		T12	234		T14	154
valid_sources[0x20]	5523	1			T12	214		T21	1		T14	187
valid_sources[0x21]	5278	1			T12	204		T54	1		T14	143
valid_sources[0x22]	4766	1			T12	216		T14	160		T15	165
valid_sources[0x23]	4566	1			T3	15		T12	242		T14	179
valid_sources[0x24]	5113	1			T12	208		T14	168		T15	140
valid_sources[0x25]	5689	1			T12	291		T14	170		T15	163
valid_sources[0x26]	5035	1			T12	229		T14	156		T15	141
valid_sources[0x27]	4923	1			T12	191		T14	144		T15	186
valid_sources[0x28]	5361	1			T16	1		T12	191		T21	1
valid_sources[0x29]	4972	1			T12	234		T18	1		T54	1
valid_sources[0x2a]	4819	1			T12	240		T14	154		T15	148
valid_sources[0x2b]	5273	1			T12	156		T21	1		T14	167
valid_sources[0x2c]	5316	1			T12	261		T54	1		T14	142
valid_sources[0x2d]	5427	1			T12	223		T18	1		T14	161
valid_sources[0x2e]	5020	1			T7	3		T12	231		T14	143
valid_sources[0x2f]	4717	1			T12	223		T14	179		T15	101
valid_sources[0x30]	4431	1			T12	209		T14	154		T15	57
valid_sources[0x31]	4987	1			T12	235		T14	162		T15	91
valid_sources[0x32]	5282	1			T12	233		T14	152		T15	101
valid_sources[0x33]	4806	1			T12	227		T18	1		T14	147
valid_sources[0x34]	5396	1			T6	1		T12	228		T14	176
valid_sources[0x35]	4797	1			T16	1		T12	224		T14	165
valid_sources[0x36]	5440	1			T12	239		T18	1		T14	144
valid_sources[0x37]	4752	1			T12	173		T14	163		T15	81
valid_sources[0x38]	5961	1			T12	322		T14	179		T15	107
valid_sources[0x39]	6134	1			T12	154		T14	170		T15	161
valid_sources[0x3a]	4403	1			T12	207		T14	172		T15	146
valid_sources[0x3b]	5149	1			T12	185		T14	155		T15	140
valid_sources[0x3c]	4619	1			T12	198		T14	162		T15	177
valid_sources[0x3d]	5619	1			T12	238		T18	1		T14	177
valid_sources[0x3e]	5566	1			T7	1		T16	1		T12	218
valid_sources[0x3f]	5133	1			T6	1		T12	228		T14	155
valid_sources[0x40]	5268	1			T12	255		T14	174		T15	96
valid_sources[0x41]	5106	1			T2	1		T12	181		T14	177
valid_sources[0x42]	4618	1			T12	147		T18	4		T14	164
valid_sources[0x43]	4838	1			T12	285		T14	157		T15	107
valid_sources[0x44]	4940	1			T12	265		T14	152		T15	115
valid_sources[0x45]	5330	1			T7	1		T12	205		T14	167
valid_sources[0x46]	4777	1			T12	217		T14	144		T15	139
valid_sources[0x47]	5183	1			T12	200		T14	173		T15	110
valid_sources[0x48]	4857	1			T7	1		T12	268		T18	2
valid_sources[0x49]	5235	1			T6	1		T12	201		T14	177
valid_sources[0x4a]	5208	1			T4	1		T12	212		T14	162
valid_sources[0x4b]	4683	1			T6	2		T16	1		T12	210
valid_sources[0x4c]	5193	1			T12	306		T14	161		T15	158
valid_sources[0x4d]	5692	1			T12	194		T14	155		T15	115
valid_sources[0x4e]	4642	1			T12	226		T14	161		T15	153
valid_sources[0x4f]	4826	1			T12	209		T18	1		T14	173
valid_sources[0x50]	4927	1			T12	247		T18	2		T14	164
valid_sources[0x51]	5149	1			T7	2		T12	256		T21	2
valid_sources[0x52]	4717	1			T12	259		T18	1		T14	179
valid_sources[0x53]	4978	1			T12	193		T18	1		T14	151
valid_sources[0x54]	4901	1			T7	1		T12	225		T14	179
valid_sources[0x55]	5089	1			T4	4		T12	242		T14	174
valid_sources[0x56]	4752	1			T12	222		T14	174		T15	117
valid_sources[0x57]	4645	1			T12	254		T14	157		T15	72
valid_sources[0x58]	5053	1			T6	1		T12	210		T14	157
valid_sources[0x59]	5237	1			T6	1		T12	281		T14	156
valid_sources[0x5a]	5607	1			T6	1		T7	1		T12	240
valid_sources[0x5b]	4916	1			T12	244		T18	1		T14	158
valid_sources[0x5c]	5766	1			T16	2		T12	210		T14	160
valid_sources[0x5d]	5252	1			T12	188		T21	1		T14	170
valid_sources[0x5e]	5221	1			T12	256		T18	3		T14	161
valid_sources[0x5f]	5393	1			T12	218		T21	1		T14	162
valid_sources[0x60]	4573	1			T7	1		T12	297		T36	26
valid_sources[0x61]	5836	1			T12	305		T54	1		T14	174
valid_sources[0x62]	5301	1			T7	2		T12	194		T14	167
valid_sources[0x63]	5007	1			T12	327		T14	151		T15	108
valid_sources[0x64]	5725	1			T12	253		T18	2		T14	143
valid_sources[0x65]	5104	1			T12	244		T14	172		T15	60
valid_sources[0x66]	5622	1			T12	172		T14	161		T15	120
valid_sources[0x67]	5066	1			T12	211		T14	155		T15	111
valid_sources[0x68]	5082	1			T12	204		T14	170		T15	121
valid_sources[0x69]	4805	1			T12	215		T14	178		T15	102
valid_sources[0x6a]	6104	1			T6	1		T12	241		T18	1
valid_sources[0x6b]	5626	1			T12	197		T14	177		T15	115
valid_sources[0x6c]	5122	1			T7	3		T13	3		T12	243
valid_sources[0x6d]	5299	1			T12	224		T14	178		T15	154
valid_sources[0x6e]	5019	1			T12	215		T18	2		T54	1
valid_sources[0x6f]	4869	1			T12	220		T14	147		T15	125
valid_sources[0x70]	5295	1			T16	1		T12	219		T14	154
valid_sources[0x71]	5189	1			T12	227		T14	173		T15	173
valid_sources[0x72]	5551	1			T12	215		T14	144		T15	172
valid_sources[0x73]	4998	1			T12	192		T21	1		T14	164
valid_sources[0x74]	4870	1			T12	228		T14	182		T15	96
valid_sources[0x75]	5158	1			T6	1		T12	191		T14	164
valid_sources[0x76]	5045	1			T12	190		T14	166		T15	139
valid_sources[0x77]	5006	1			T7	2		T12	226		T14	160
valid_sources[0x78]	5478	1			T7	1		T16	1		T12	184
valid_sources[0x79]	5064	1			T12	257		T14	155		T15	98
valid_sources[0x7a]	4710	1			T12	226		T18	1		T14	161
valid_sources[0x7b]	4564	1			T12	202		T18	1		T14	174
valid_sources[0x7c]	4711	1			T12	242		T18	1		T14	152
valid_sources[0x7d]	5553	1			T12	191		T14	166		T15	111
valid_sources[0x7e]	5271	1			T7	1		T12	202		T14	168
valid_sources[0x7f]	5180	1			T9	1		T12	166		T18	1
valid_sources[0x80]	5203	1			T12	233		T14	172		T15	132

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

302805

1

T2

1

T6

18

T7

17

values[0x0]

all_enables

biggest_size

446767

1

T3

2

T4

2

T8

1

values[0x1]

all_enables

biggest_size

447215

1

T10

2

T35

1

T12

19760