Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2809796

1

T1

247

T6

42

T11

90

full_word

1809523

1

T1

25

T6

4

T7

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4619059	1			T1	272		T6	46		T7	2
auto[TlIntgErrCmd]	80	1			T57	5		T58	4		T59	2
auto[TlIntgErrData]	89	1			T57	8		T58	1		T59	2
auto[TlIntgErrBoth]	91	1			T57	7		T58	5		T59	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

741411

1

T1

272

T6

46

T7

2

auto[1]

3877908

1

T12

184104

T14

119331

T15

85534

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	312611	1			T1	247		T6	42		T11	90
auto[TlIntgErrNone]	partial	auto[1]	2496947	1			T12	120292		T14	76196		T15	55879
auto[TlIntgErrNone]	full_word	auto[0]	428685	1			T1	25		T6	4		T7	2
auto[TlIntgErrNone]	full_word	auto[1]	1380816	1			T12	63812		T14	43135		T15	29655
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T57	3		T58	2		T121	2
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T57	2		T58	2		T59	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T121	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T123	2		T126	1		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1			T59	2		T121	3		T125	1
auto[TlIntgErrData]	partial	auto[1]	40	1			T57	7		T58	1		T121	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T57	1		T127	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T125	1		T123	3		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T57	3		T58	1		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T57	3		T58	3		T59	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T57	1		T129	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T58	1		T121	2		T126	1