Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61957	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1337503

1

T1

3

T2

6

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	374543	1			T1	78		T2	6		T3	159
values[0x0]	502987	1			T5	14652		T11	20623		T12	71330
values[0x1]	521930	1			T5	15214		T11	21544		T12	74156

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	31142	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1368318

1

T1

45

T2

6

T3

99

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5235	1			T3	1		T5	2		T11	255
valid_sources[0x01]	4296	1			T5	136		T11	208		T14	3
valid_sources[0x02]	4857	1			T5	172		T11	197		T14	4
valid_sources[0x03]	5444	1			T5	1		T9	2		T11	216
valid_sources[0x04]	5922	1			T5	5		T11	237		T73	2
valid_sources[0x05]	4967	1			T3	2		T11	216		T70	4
valid_sources[0x06]	4867	1			T11	221		T14	8		T73	4
valid_sources[0x07]	5179	1			T11	237		T71	1		T73	3
valid_sources[0x08]	5515	1			T3	3		T5	3		T11	218
valid_sources[0x09]	5250	1			T5	507		T11	206		T115	1
valid_sources[0x0a]	4574	1			T3	1		T11	217		T101	3
valid_sources[0x0b]	5608	1			T5	491		T11	213		T101	1
valid_sources[0x0c]	5279	1			T11	234		T88	1		T73	1
valid_sources[0x0d]	6495	1			T3	2		T11	226		T70	1
valid_sources[0x0e]	5850	1			T3	1		T5	207		T8	1
valid_sources[0x0f]	7432	1			T5	174		T11	224		T14	5
valid_sources[0x10]	5105	1			T11	218		T71	2		T115	1
valid_sources[0x11]	6699	1			T1	2		T5	195		T8	1
valid_sources[0x12]	5807	1			T5	541		T11	219		T73	2
valid_sources[0x13]	7118	1			T5	289		T11	223		T14	15
valid_sources[0x14]	5062	1			T1	1		T5	5		T11	238
valid_sources[0x15]	5798	1			T3	3		T11	232		T70	1
valid_sources[0x16]	5675	1			T1	2		T11	236		T14	4
valid_sources[0x17]	5345	1			T5	245		T11	204		T116	7
valid_sources[0x18]	4626	1			T11	222		T101	2		T88	1
valid_sources[0x19]	4798	1			T11	222		T88	2		T73	3
valid_sources[0x1a]	4704	1			T5	211		T11	232		T116	4
valid_sources[0x1b]	5470	1			T5	225		T11	204		T101	2
valid_sources[0x1c]	5259	1			T5	92		T11	223		T34	1
valid_sources[0x1d]	4500	1			T8	1		T11	227		T14	4
valid_sources[0x1e]	4867	1			T3	2		T11	227		T88	2
valid_sources[0x1f]	6014	1			T11	223		T88	2		T71	1
valid_sources[0x20]	5310	1			T5	335		T11	230		T101	1
valid_sources[0x21]	5793	1			T1	1		T3	1		T4	1
valid_sources[0x22]	6257	1			T3	1		T5	560		T8	1
valid_sources[0x23]	4530	1			T11	229		T101	1		T70	1
valid_sources[0x24]	4858	1			T3	2		T5	21		T8	1
valid_sources[0x25]	6036	1			T1	1		T4	1		T5	529
valid_sources[0x26]	5947	1			T5	847		T11	221		T115	2
valid_sources[0x27]	5718	1			T5	579		T11	236		T71	2
valid_sources[0x28]	5729	1			T3	2		T11	246		T101	5
valid_sources[0x29]	5321	1			T5	168		T11	226		T14	2
valid_sources[0x2a]	5808	1			T5	202		T8	1		T11	235
valid_sources[0x2b]	6043	1			T1	2		T3	2		T5	387
valid_sources[0x2c]	5986	1			T11	198		T14	2		T101	2
valid_sources[0x2d]	5169	1			T3	1		T11	231		T71	1
valid_sources[0x2e]	4688	1			T1	2		T11	226		T71	2
valid_sources[0x2f]	4308	1			T3	1		T5	1		T11	234
valid_sources[0x30]	6054	1			T3	1		T5	112		T11	204
valid_sources[0x31]	5764	1			T1	1		T3	1		T5	44
valid_sources[0x32]	5708	1			T8	1		T11	230		T14	1
valid_sources[0x33]	6364	1			T8	1		T11	231		T115	3
valid_sources[0x34]	5417	1			T5	600		T11	231		T14	2
valid_sources[0x35]	6291	1			T5	644		T11	214		T101	1
valid_sources[0x36]	5452	1			T3	2		T11	219		T101	2
valid_sources[0x37]	5717	1			T5	185		T11	211		T101	1
valid_sources[0x38]	4956	1			T5	158		T11	237		T14	1
valid_sources[0x39]	4886	1			T1	3		T11	245		T101	1
valid_sources[0x3a]	5379	1			T5	342		T8	1		T11	214
valid_sources[0x3b]	5193	1			T5	798		T8	1		T11	215
valid_sources[0x3c]	5491	1			T5	307		T11	218		T13	13
valid_sources[0x3d]	5941	1			T3	1		T11	224		T14	2
valid_sources[0x3e]	6641	1			T3	1		T11	230		T70	1
valid_sources[0x3f]	6369	1			T5	95		T11	201		T14	1
valid_sources[0x40]	5394	1			T1	1		T5	28		T11	236
valid_sources[0x41]	5042	1			T2	6		T3	1		T11	206
valid_sources[0x42]	5751	1			T5	125		T11	217		T13	12
valid_sources[0x43]	6050	1			T1	3		T3	3		T5	803
valid_sources[0x44]	5007	1			T5	162		T8	1		T11	245
valid_sources[0x45]	5172	1			T11	224		T14	5		T71	1
valid_sources[0x46]	4758	1			T11	213		T71	1		T73	1
valid_sources[0x47]	5654	1			T5	561		T11	237		T101	1
valid_sources[0x48]	6775	1			T1	4		T3	1		T5	2
valid_sources[0x49]	6774	1			T1	1		T5	330		T8	1
valid_sources[0x4a]	5251	1			T3	2		T11	238		T73	2
valid_sources[0x4b]	5604	1			T3	1		T11	208		T14	4
valid_sources[0x4c]	4511	1			T11	214		T73	1		T117	4
valid_sources[0x4d]	6341	1			T1	2		T11	232		T116	5
valid_sources[0x4e]	5015	1			T3	1		T8	1		T11	225
valid_sources[0x4f]	6414	1			T3	2		T5	769		T8	2
valid_sources[0x50]	4662	1			T11	241		T14	2		T71	1
valid_sources[0x51]	5317	1			T5	812		T11	226		T101	1
valid_sources[0x52]	4763	1			T3	1		T11	209		T74	1
valid_sources[0x53]	6543	1			T5	3		T11	234		T101	3
valid_sources[0x54]	4612	1			T5	1		T11	214		T101	2
valid_sources[0x55]	5619	1			T11	215		T73	2		T117	3
valid_sources[0x56]	4315	1			T11	250		T101	2		T70	1
valid_sources[0x57]	4536	1			T11	235		T115	1		T75	1
valid_sources[0x58]	4951	1			T3	3		T5	432		T11	223
valid_sources[0x59]	5165	1			T5	135		T11	207		T14	1
valid_sources[0x5a]	5650	1			T11	218		T86	23		T88	2
valid_sources[0x5b]	5251	1			T1	4		T3	1		T5	244
valid_sources[0x5c]	5823	1			T1	1		T3	1		T5	91
valid_sources[0x5d]	4737	1			T5	241		T11	235		T13	51
valid_sources[0x5e]	5736	1			T5	37		T11	213		T101	1
valid_sources[0x5f]	4996	1			T3	2		T5	276		T11	234
valid_sources[0x60]	5288	1			T11	239		T73	5		T115	1
valid_sources[0x61]	5637	1			T3	1		T11	233		T60	41
valid_sources[0x62]	4954	1			T5	69		T11	201		T101	3
valid_sources[0x63]	5454	1			T3	1		T5	4		T11	214
valid_sources[0x64]	5807	1			T1	1		T3	1		T8	3
valid_sources[0x65]	4963	1			T5	164		T11	183		T14	7
valid_sources[0x66]	5072	1			T3	2		T5	562		T11	195
valid_sources[0x67]	5838	1			T11	247		T59	43		T88	3
valid_sources[0x68]	7649	1			T3	1		T11	234		T14	7
valid_sources[0x69]	4905	1			T3	1		T11	224		T115	1
valid_sources[0x6a]	4624	1			T11	212		T101	3		T70	1
valid_sources[0x6b]	5319	1			T3	1		T5	22		T8	1
valid_sources[0x6c]	6750	1			T3	2		T5	8		T11	228
valid_sources[0x6d]	4610	1			T5	360		T11	230		T101	2
valid_sources[0x6e]	6115	1			T1	1		T3	1		T5	92
valid_sources[0x6f]	5387	1			T11	205		T117	1		T75	2
valid_sources[0x70]	6693	1			T5	158		T11	217		T73	1
valid_sources[0x71]	6816	1			T5	9		T11	211		T101	4
valid_sources[0x72]	5191	1			T5	231		T8	1		T11	222
valid_sources[0x73]	5182	1			T3	3		T5	303		T11	219
valid_sources[0x74]	5377	1			T1	1		T5	1044		T8	1
valid_sources[0x75]	5313	1			T11	211		T14	1		T70	1
valid_sources[0x76]	5071	1			T5	122		T11	222		T86	14
valid_sources[0x77]	5593	1			T5	15		T11	246		T14	2
valid_sources[0x78]	5524	1			T1	1		T5	265		T11	197
valid_sources[0x79]	5144	1			T11	203		T101	4		T73	3
valid_sources[0x7a]	4863	1			T11	222		T14	1		T70	1
valid_sources[0x7b]	5110	1			T1	1		T11	233		T88	2
valid_sources[0x7c]	5263	1			T3	3		T5	359		T11	224
valid_sources[0x7d]	5748	1			T3	2		T5	660		T11	205
valid_sources[0x7e]	4555	1			T3	1		T5	105		T11	227
valid_sources[0x7f]	5031	1			T11	261		T14	1		T70	1
valid_sources[0x80]	5334	1			T11	220		T101	3		T70	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

338874

1

T1

3

T2

6

T3

21

values[0x0]

all_enables

biggest_size

498766

1

T5

14523

T11

20463

T12

70731

values[0x1]

all_enables

biggest_size

499863

1

T5

14518

T11

20652

T12

71156

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	100893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1001158

1

T1

12

T2

21

T3

37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	277835	1			T1	32		T2	40		T3	64
values[0x0]	382587	1			T5	11391		T6	2		T10	8
values[0x1]	441629	1			T5	13411		T6	5		T10	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46233	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1055818

1

T1

16

T2

25

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4426	1			T5	133		T11	138		T89	1
valid_sources[0x01]	3915	1			T5	113		T11	147		T14	4
valid_sources[0x02]	4544	1			T5	128		T9	1		T11	156
valid_sources[0x03]	4104	1			T5	127		T11	146		T60	1
valid_sources[0x04]	4003	1			T5	129		T6	1		T11	146
valid_sources[0x05]	4040	1			T3	1		T5	138		T11	145
valid_sources[0x06]	4085	1			T5	109		T10	1		T11	141
valid_sources[0x07]	4142	1			T5	120		T11	148		T13	5
valid_sources[0x08]	4447	1			T5	113		T11	143		T89	1
valid_sources[0x09]	4484	1			T5	144		T11	168		T89	1
valid_sources[0x0a]	3640	1			T5	142		T9	2		T10	2
valid_sources[0x0b]	3978	1			T1	1		T5	135		T11	164
valid_sources[0x0c]	4341	1			T5	165		T11	212		T13	2
valid_sources[0x0d]	4815	1			T3	1		T5	141		T9	1
valid_sources[0x0e]	4102	1			T3	1		T5	132		T11	153
valid_sources[0x0f]	4358	1			T3	2		T5	134		T11	160
valid_sources[0x10]	4557	1			T5	122		T11	120		T54	8
valid_sources[0x11]	4357	1			T5	127		T11	155		T118	4
valid_sources[0x12]	4261	1			T5	141		T11	171		T13	2
valid_sources[0x13]	4619	1			T5	113		T11	153		T73	3
valid_sources[0x14]	4371	1			T3	1		T5	126		T11	148
valid_sources[0x15]	4651	1			T5	129		T11	172		T89	1
valid_sources[0x16]	4247	1			T5	117		T11	173		T36	2
valid_sources[0x17]	4193	1			T5	121		T11	174		T37	2
valid_sources[0x18]	4345	1			T5	117		T11	156		T14	1
valid_sources[0x19]	4360	1			T5	125		T11	139		T70	1
valid_sources[0x1a]	4504	1			T5	121		T11	156		T34	3
valid_sources[0x1b]	4523	1			T3	1		T5	152		T11	142
valid_sources[0x1c]	4040	1			T5	108		T11	151		T14	4
valid_sources[0x1d]	4366	1			T3	1		T5	118		T11	157
valid_sources[0x1e]	4005	1			T5	123		T11	150		T116	1
valid_sources[0x1f]	3926	1			T5	115		T11	154		T35	13
valid_sources[0x20]	3884	1			T5	114		T11	140		T14	3
valid_sources[0x21]	4528	1			T5	127		T11	149		T37	1
valid_sources[0x22]	4067	1			T5	129		T11	158		T73	1
valid_sources[0x23]	4132	1			T5	136		T10	1		T11	165
valid_sources[0x24]	4116	1			T5	129		T11	130		T119	1
valid_sources[0x25]	4812	1			T5	116		T11	150		T36	1
valid_sources[0x26]	4951	1			T5	140		T11	129		T36	1
valid_sources[0x27]	4525	1			T3	1		T5	154		T11	160
valid_sources[0x28]	4684	1			T1	10		T5	128		T11	170
valid_sources[0x29]	4743	1			T3	1		T5	125		T9	1
valid_sources[0x2a]	4102	1			T5	129		T11	177		T60	1
valid_sources[0x2b]	3961	1			T3	1		T5	106		T11	127
valid_sources[0x2c]	4260	1			T1	2		T5	141		T11	209
valid_sources[0x2d]	4403	1			T5	135		T11	152		T14	3
valid_sources[0x2e]	3949	1			T3	1		T5	115		T11	147
valid_sources[0x2f]	4380	1			T3	1		T5	137		T9	2
valid_sources[0x30]	3838	1			T3	3		T5	127		T8	5
valid_sources[0x31]	4402	1			T5	119		T10	1		T11	145
valid_sources[0x32]	4095	1			T3	1		T5	145		T11	179
valid_sources[0x33]	4332	1			T5	114		T10	1		T11	164
valid_sources[0x34]	4419	1			T5	149		T11	152		T60	1
valid_sources[0x35]	4084	1			T5	127		T11	193		T13	1
valid_sources[0x36]	4137	1			T5	132		T6	1		T11	171
valid_sources[0x37]	3862	1			T5	111		T9	1		T11	173
valid_sources[0x38]	4229	1			T5	137		T11	157		T37	1
valid_sources[0x39]	4215	1			T5	127		T10	1		T11	149
valid_sources[0x3a]	4516	1			T4	21		T5	127		T11	180
valid_sources[0x3b]	4000	1			T5	142		T11	132		T89	1
valid_sources[0x3c]	3905	1			T5	121		T9	2		T11	191
valid_sources[0x3d]	4302	1			T3	1		T5	122		T11	162
valid_sources[0x3e]	4433	1			T5	110		T11	183		T120	1
valid_sources[0x3f]	4442	1			T5	152		T11	149		T70	1
valid_sources[0x40]	4628	1			T1	1		T5	136		T11	179
valid_sources[0x41]	4368	1			T5	101		T11	168		T73	3
valid_sources[0x42]	5068	1			T3	1		T5	113		T11	134
valid_sources[0x43]	3711	1			T5	132		T11	151		T89	1
valid_sources[0x44]	4000	1			T5	107		T8	9		T11	175
valid_sources[0x45]	4422	1			T1	8		T5	115		T11	150
valid_sources[0x46]	4319	1			T3	1		T5	130		T10	1
valid_sources[0x47]	4096	1			T5	123		T11	173		T70	1
valid_sources[0x48]	4181	1			T5	118		T11	153		T18	1
valid_sources[0x49]	4446	1			T5	136		T9	1		T11	154
valid_sources[0x4a]	4202	1			T5	136		T11	162		T13	1
valid_sources[0x4b]	4420	1			T5	117		T11	152		T56	1
valid_sources[0x4c]	4065	1			T5	106		T11	156		T14	4
valid_sources[0x4d]	4028	1			T5	128		T11	127		T70	1
valid_sources[0x4e]	4798	1			T5	113		T11	159		T34	1
valid_sources[0x4f]	4439	1			T5	131		T10	1		T11	158
valid_sources[0x50]	3932	1			T5	120		T11	167		T89	1
valid_sources[0x51]	4800	1			T3	1		T5	145		T11	154
valid_sources[0x52]	4432	1			T5	123		T11	181		T38	4
valid_sources[0x53]	4107	1			T5	123		T11	153		T89	1
valid_sources[0x54]	4549	1			T5	147		T11	150		T13	2
valid_sources[0x55]	3908	1			T5	126		T11	156		T89	1
valid_sources[0x56]	4147	1			T5	133		T11	175		T74	1
valid_sources[0x57]	4319	1			T5	109		T11	174		T34	1
valid_sources[0x58]	4454	1			T5	107		T9	2		T11	186
valid_sources[0x59]	4257	1			T5	107		T11	146		T14	2
valid_sources[0x5a]	4211	1			T5	143		T9	1		T11	144
valid_sources[0x5b]	4191	1			T5	126		T11	156		T14	1
valid_sources[0x5c]	4388	1			T5	156		T11	137		T70	1
valid_sources[0x5d]	4818	1			T5	101		T11	142		T73	1
valid_sources[0x5e]	4602	1			T5	110		T10	1		T11	165
valid_sources[0x5f]	4623	1			T2	40		T5	134		T11	153
valid_sources[0x60]	4625	1			T5	139		T9	1		T11	156
valid_sources[0x61]	3936	1			T5	132		T11	150		T55	1
valid_sources[0x62]	4505	1			T3	2		T5	158		T9	1
valid_sources[0x63]	4263	1			T5	131		T11	153		T36	1
valid_sources[0x64]	4579	1			T5	157		T11	170		T121	1
valid_sources[0x65]	4229	1			T5	125		T9	1		T11	156
valid_sources[0x66]	4251	1			T3	1		T5	109		T11	171
valid_sources[0x67]	4253	1			T5	110		T11	134		T18	1
valid_sources[0x68]	3969	1			T3	1		T5	164		T9	2
valid_sources[0x69]	4476	1			T5	143		T11	177		T13	1
valid_sources[0x6a]	4482	1			T5	103		T6	1		T11	174
valid_sources[0x6b]	4307	1			T5	129		T11	143		T73	2
valid_sources[0x6c]	3818	1			T5	138		T11	149		T18	1
valid_sources[0x6d]	4200	1			T5	129		T11	152		T73	1
valid_sources[0x6e]	4139	1			T5	106		T11	181		T73	7
valid_sources[0x6f]	4969	1			T5	136		T11	163		T58	2
valid_sources[0x70]	3969	1			T5	143		T11	156		T116	1
valid_sources[0x71]	4493	1			T5	121		T11	137		T70	1
valid_sources[0x72]	4969	1			T5	158		T11	147		T70	1
valid_sources[0x73]	4569	1			T5	115		T11	147		T60	1
valid_sources[0x74]	4306	1			T3	2		T5	97		T11	151
valid_sources[0x75]	4365	1			T5	148		T11	127		T73	7
valid_sources[0x76]	3983	1			T5	125		T11	116		T56	1
valid_sources[0x77]	4642	1			T5	118		T11	139		T73	1
valid_sources[0x78]	4377	1			T5	154		T11	157		T70	1
valid_sources[0x79]	4236	1			T5	100		T11	157		T14	1
valid_sources[0x7a]	4004	1			T5	126		T11	112		T89	1
valid_sources[0x7b]	4137	1			T5	133		T11	197		T13	3
valid_sources[0x7c]	4567	1			T3	1		T5	135		T11	161
valid_sources[0x7d]	4914	1			T5	118		T11	190		T12	1125
valid_sources[0x7e]	4264	1			T5	131		T11	146		T60	1
valid_sources[0x7f]	4457	1			T5	112		T11	188		T35	9
valid_sources[0x80]	4335	1			T5	119		T11	185		T60	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

253431

1

T1

12

T2

21

T3

37

values[0x0]

all_enables

biggest_size

374695

1

T5

11185

T10

1

T11

13499

values[0x1]

all_enables

biggest_size

373032

1

T5

11396

T6

2

T10

1