Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2386300

1

T1

75

T3

138

T5

70758

full_word

1555730

1

T1

3

T2

4

T3

21

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3941700	1			T1	78		T2	4		T3	159
auto[TlIntgErrCmd]	123	1			T49	6		T50	7		T51	4
auto[TlIntgErrData]	105	1			T49	7		T50	6		T51	3
auto[TlIntgErrBoth]	102	1			T49	7		T50	7		T51	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

639727

1

T1

78

T2

4

T3

159

auto[1]

3302303

1

T5

98326

T11

136925

T12

454656

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	268666	1			T1	75		T3	138		T5	7003
auto[TlIntgErrNone]	partial	auto[1]	2117323	1			T5	63755		T11	87854		T12	287326
auto[TlIntgErrNone]	full_word	auto[0]	370899	1			T1	3		T2	4		T3	21
auto[TlIntgErrNone]	full_word	auto[1]	1184812	1			T5	34571		T11	49071		T12	167330
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T49	4		T50	2		T51	1
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T49	2		T50	5		T51	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T103	1		T108	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T105	1		T108	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T49	2		T50	5		T51	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T49	5		T50	1		T104	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T104	1		T105	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T108	1		T112	1		T110	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T49	3		T50	4		T51	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T49	4		T50	3		T113	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T51	2		T108	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T111	1		-	-		-	-