Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2720759

1

T5

216

T7

146311

T11

98

full_word

1747750

1

T1

6

T2

2

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4468189	1			T1	6		T2	2		T3	4
auto[TlIntgErrCmd]	98	1			T57	3		T58	3		T59	9
auto[TlIntgErrData]	114	1			T57	3		T58	6		T59	7
auto[TlIntgErrBoth]	108	1			T57	4		T58	1		T59	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

714791

1

T1

6

T2

2

T3

4

auto[1]

3753718

1

T7

200475

T15

299424

T16

750517

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	300824	1			T5	216		T7	14978		T11	98
auto[TlIntgErrNone]	partial	auto[1]	2419644	1			T7	131333		T15	192422		T16	483480
auto[TlIntgErrNone]	full_word	auto[0]	413817	1			T1	6		T2	2		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	1333904	1			T7	69142		T15	107002		T16	267037
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T57	2		T58	1		T59	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T57	1		T58	2		T59	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T113	1		T108	1		T114	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T110	1		T115	1		T116	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T57	1		T58	4		T59	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T57	2		T58	1		T59	4
auto[TlIntgErrData]	full_word	auto[0]	9	1			T58	1		T106	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T111	1		T109	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T58	1		T59	2		T105	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T57	4		T59	2		T105	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T105	1		T111	2		T110	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T110	1		T115	1		T117	1