Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4252848

1

T3

74

T4

225

T8

148

full_word

2697597

1

T3

3

T4

32

T6

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6950165	1			T3	77		T4	257		T6	4
auto[TlIntgErrCmd]	85	1			T63	4		T64	3		T65	2
auto[TlIntgErrData]	99	1			T63	2		T64	5		T65	3
auto[TlIntgErrBoth]	96	1			T63	4		T64	2		T65	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097424

1

T3

77

T4

257

T6

4

auto[1]

5853021

1

T22

109775

T23

447710

T24

221055

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	459494	1			T3	74		T4	225		T8	148
auto[TlIntgErrNone]	partial	auto[1]	3793100	1			T22	71058		T23	287559		T24	141317
auto[TlIntgErrNone]	full_word	auto[0]	637793	1			T3	3		T4	32		T6	4
auto[TlIntgErrNone]	full_word	auto[1]	2059778	1			T22	38717		T23	160151		T24	79738
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T63	4		T64	1		T65	1
auto[TlIntgErrCmd]	partial	auto[1]	36	1			T64	1		T65	1		T107	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T64	1		T108	1		T109	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T63	1		T64	1		T65	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T63	1		T64	3		T65	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T110	1		T111	1		T112	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T64	1		T65	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T65	3		T107	1		T110	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T63	2		T64	2		T65	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T114	1		T109	1		T115	2
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T63	2		T107	1		T116	2