Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	67255	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1474213

1

T2

16

T3

40984

T5

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	407765	1			T2	194		T3	11241		T5	83
values[0x0]	556263	1			T3	15534		T12	26565		T15	62907
values[0x1]	577440	1			T3	16029		T12	27775		T15	65574

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34383	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1507085

1

T2

110

T3

41883

T5

52

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8500	1			T3	155		T12	259		T15	2439
valid_sources[0x01]	5441	1			T3	156		T12	289		T15	237
valid_sources[0x02]	7421	1			T3	162		T6	4		T12	289
valid_sources[0x03]	6368	1			T3	173		T6	6		T12	324
valid_sources[0x04]	5313	1			T3	159		T12	287		T15	543
valid_sources[0x05]	5575	1			T3	170		T12	269		T15	805
valid_sources[0x06]	6615	1			T3	166		T5	1		T12	241
valid_sources[0x07]	5389	1			T3	164		T12	281		T15	251
valid_sources[0x08]	6448	1			T3	178		T6	1		T12	248
valid_sources[0x09]	5652	1			T3	176		T5	1		T6	1
valid_sources[0x0a]	6887	1			T3	205		T12	303		T15	1112
valid_sources[0x0b]	5329	1			T3	177		T12	294		T15	444
valid_sources[0x0c]	4493	1			T3	164		T14	3		T12	316
valid_sources[0x0d]	6462	1			T3	142		T5	1		T6	5
valid_sources[0x0e]	5797	1			T3	135		T11	3		T12	307
valid_sources[0x0f]	6483	1			T3	162		T19	21		T12	295
valid_sources[0x10]	6155	1			T3	166		T6	1		T14	1
valid_sources[0x11]	4647	1			T3	165		T12	221		T15	52
valid_sources[0x12]	6129	1			T3	169		T12	273		T15	604
valid_sources[0x13]	4888	1			T3	171		T14	10		T12	281
valid_sources[0x14]	5933	1			T3	151		T5	3		T12	296
valid_sources[0x15]	6682	1			T3	167		T5	2		T6	2
valid_sources[0x16]	5149	1			T3	141		T6	4		T12	292
valid_sources[0x17]	5157	1			T2	53		T3	181		T5	1
valid_sources[0x18]	4877	1			T3	158		T12	279		T15	360
valid_sources[0x19]	5329	1			T3	152		T12	277		T15	797
valid_sources[0x1a]	5728	1			T3	156		T6	1		T12	283
valid_sources[0x1b]	5170	1			T3	143		T6	2		T12	315
valid_sources[0x1c]	6587	1			T3	157		T5	2		T12	294
valid_sources[0x1d]	5898	1			T3	189		T6	1		T12	270
valid_sources[0x1e]	4859	1			T3	154		T6	3		T12	233
valid_sources[0x1f]	5024	1			T3	174		T5	1		T12	281
valid_sources[0x20]	5137	1			T3	220		T12	263		T15	335
valid_sources[0x21]	5636	1			T3	181		T10	23		T12	276
valid_sources[0x22]	5758	1			T3	165		T6	1		T12	284
valid_sources[0x23]	10006	1			T3	187		T12	265		T15	2170
valid_sources[0x24]	5507	1			T3	147		T6	1		T10	10
valid_sources[0x25]	6043	1			T3	190		T19	26		T12	269
valid_sources[0x26]	7696	1			T3	172		T6	1		T12	300
valid_sources[0x27]	6165	1			T3	167		T6	1		T19	18
valid_sources[0x28]	5867	1			T3	168		T6	4		T19	28
valid_sources[0x29]	7147	1			T3	161		T6	1		T12	277
valid_sources[0x2a]	5916	1			T3	154		T6	4		T12	300
valid_sources[0x2b]	6232	1			T3	160		T6	1		T12	285
valid_sources[0x2c]	5131	1			T3	150		T5	3		T14	12
valid_sources[0x2d]	4844	1			T3	156		T12	305		T115	1
valid_sources[0x2e]	5989	1			T3	153		T6	6		T19	2
valid_sources[0x2f]	7761	1			T3	180		T6	5		T12	271
valid_sources[0x30]	5501	1			T3	161		T12	271		T13	24
valid_sources[0x31]	4961	1			T3	150		T6	2		T12	294
valid_sources[0x32]	5507	1			T3	166		T12	284		T15	285
valid_sources[0x33]	5777	1			T3	172		T5	1		T12	296
valid_sources[0x34]	5293	1			T3	149		T6	4		T12	309
valid_sources[0x35]	5220	1			T3	169		T12	277		T15	143
valid_sources[0x36]	6305	1			T3	164		T5	1		T6	9
valid_sources[0x37]	5771	1			T3	158		T5	1		T19	7
valid_sources[0x38]	5794	1			T3	188		T12	294		T15	1002
valid_sources[0x39]	4884	1			T3	164		T19	10		T12	296
valid_sources[0x3a]	6657	1			T3	157		T6	1		T12	306
valid_sources[0x3b]	5464	1			T3	164		T12	294		T15	82
valid_sources[0x3c]	6175	1			T3	161		T19	7		T12	282
valid_sources[0x3d]	7029	1			T3	160		T5	2		T6	1
valid_sources[0x3e]	7103	1			T3	180		T6	1		T12	289
valid_sources[0x3f]	6705	1			T3	161		T14	2		T12	302
valid_sources[0x40]	5291	1			T3	160		T6	2		T12	314
valid_sources[0x41]	6734	1			T3	163		T12	249		T15	809
valid_sources[0x42]	5920	1			T3	168		T12	276		T15	489
valid_sources[0x43]	6758	1			T3	160		T12	298		T15	1668
valid_sources[0x44]	5387	1			T3	153		T6	3		T12	302
valid_sources[0x45]	6552	1			T3	168		T12	259		T15	1181
valid_sources[0x46]	4751	1			T3	177		T19	20		T12	314
valid_sources[0x47]	6390	1			T3	171		T12	271		T15	1354
valid_sources[0x48]	8176	1			T2	23		T3	164		T12	261
valid_sources[0x49]	5234	1			T3	176		T19	3		T12	289
valid_sources[0x4a]	6143	1			T3	164		T5	1		T6	1
valid_sources[0x4b]	6211	1			T3	151		T6	2		T12	296
valid_sources[0x4c]	6799	1			T3	154		T12	291		T54	22
valid_sources[0x4d]	7125	1			T3	147		T6	1		T14	15
valid_sources[0x4e]	4787	1			T3	178		T12	264		T15	80
valid_sources[0x4f]	5171	1			T3	153		T5	1		T12	293
valid_sources[0x50]	5977	1			T3	171		T5	1		T14	1
valid_sources[0x51]	6399	1			T3	158		T12	271		T15	1230
valid_sources[0x52]	4713	1			T3	180		T6	1		T12	263
valid_sources[0x53]	6911	1			T3	167		T6	4		T12	285
valid_sources[0x54]	6424	1			T3	158		T5	1		T19	7
valid_sources[0x55]	6137	1			T3	173		T12	297		T15	274
valid_sources[0x56]	6861	1			T3	187		T12	288		T15	966
valid_sources[0x57]	5613	1			T3	165		T12	297		T15	626
valid_sources[0x58]	4899	1			T3	167		T12	302		T15	140
valid_sources[0x59]	6658	1			T3	158		T12	300		T15	80
valid_sources[0x5a]	6438	1			T3	163		T5	1		T6	3
valid_sources[0x5b]	4708	1			T2	22		T3	143		T12	307
valid_sources[0x5c]	5944	1			T3	189		T12	278		T15	26
valid_sources[0x5d]	5888	1			T3	172		T6	4		T12	282
valid_sources[0x5e]	5222	1			T3	159		T12	275		T15	104
valid_sources[0x5f]	5396	1			T3	187		T19	6		T12	288
valid_sources[0x60]	5345	1			T3	168		T6	1		T12	263
valid_sources[0x61]	5540	1			T3	173		T11	2		T12	292
valid_sources[0x62]	5532	1			T3	157		T19	38		T12	247
valid_sources[0x63]	6554	1			T3	175		T5	2		T6	3
valid_sources[0x64]	7163	1			T3	171		T12	316		T15	1108
valid_sources[0x65]	6067	1			T3	173		T12	235		T15	1616
valid_sources[0x66]	6176	1			T3	179		T5	1		T6	1
valid_sources[0x67]	6123	1			T3	176		T12	283		T54	15
valid_sources[0x68]	5449	1			T3	161		T12	246		T15	451
valid_sources[0x69]	5928	1			T3	180		T5	1		T11	7
valid_sources[0x6a]	7873	1			T3	166		T11	5		T12	257
valid_sources[0x6b]	7252	1			T3	169		T12	288		T15	2484
valid_sources[0x6c]	5626	1			T2	15		T3	171		T5	1
valid_sources[0x6d]	5102	1			T2	15		T3	158		T11	6
valid_sources[0x6e]	6379	1			T3	167		T6	3		T10	24
valid_sources[0x6f]	6590	1			T3	175		T6	2		T11	22
valid_sources[0x70]	7234	1			T3	167		T19	2		T12	289
valid_sources[0x71]	5674	1			T3	182		T12	302		T15	764
valid_sources[0x72]	6009	1			T3	158		T12	257		T15	450
valid_sources[0x73]	6441	1			T3	161		T6	2		T12	301
valid_sources[0x74]	5281	1			T3	174		T12	286		T15	434
valid_sources[0x75]	6342	1			T3	158		T12	282		T20	1
valid_sources[0x76]	5787	1			T3	167		T19	6		T12	256
valid_sources[0x77]	5907	1			T3	171		T12	310		T15	1338
valid_sources[0x78]	7564	1			T3	187		T6	1		T12	299
valid_sources[0x79]	5611	1			T3	159		T5	1		T6	4
valid_sources[0x7a]	5525	1			T3	159		T5	1		T6	1
valid_sources[0x7b]	5430	1			T2	10		T3	171		T12	236
valid_sources[0x7c]	6194	1			T3	184		T6	1		T12	272
valid_sources[0x7d]	5567	1			T3	188		T12	262		T15	49
valid_sources[0x7e]	6040	1			T3	173		T5	2		T6	2
valid_sources[0x7f]	6423	1			T3	170		T12	334		T15	1274
valid_sources[0x80]	5594	1			T3	162		T5	2		T12	300

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

371099

1

T2

16

T3

10273

T5

10

values[0x0]

all_enables

biggest_size

551226

1

T3

15408

T12

26319

T15

62282

values[0x1]

all_enables

biggest_size

551888

1

T3

15303

T12

26495

T15

62546

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	112596	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1116943

1

T2

61

T3

29774

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	310308	1			T1	20		T2	96		T3	8426
values[0x0]	425544	1			T3	11127		T9	6		T23	3
values[0x1]	493687	1			T3	13200		T9	2		T23	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1178246

1

T1

3

T2

72

T3

31408

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3826	1			T3	156		T8	1		T12	182
valid_sources[0x01]	4329	1			T3	123		T8	1		T11	2
valid_sources[0x02]	5625	1			T3	157		T12	210		T20	2
valid_sources[0x03]	4858	1			T3	93		T5	1		T8	1
valid_sources[0x04]	5267	1			T3	156		T10	1		T12	175
valid_sources[0x05]	4037	1			T3	123		T12	200		T15	404
valid_sources[0x06]	4706	1			T1	4		T3	141		T10	2
valid_sources[0x07]	5244	1			T3	134		T11	1		T12	205
valid_sources[0x08]	4130	1			T3	132		T10	1		T11	1
valid_sources[0x09]	4130	1			T1	2		T3	164		T8	1
valid_sources[0x0a]	5556	1			T3	113		T11	1		T12	173
valid_sources[0x0b]	4242	1			T3	104		T12	237		T15	60
valid_sources[0x0c]	3973	1			T3	126		T10	1		T12	241
valid_sources[0x0d]	4257	1			T3	146		T12	222		T15	230
valid_sources[0x0e]	4228	1			T3	115		T10	3		T12	169
valid_sources[0x0f]	4503	1			T3	113		T12	214		T15	373
valid_sources[0x10]	4421	1			T3	134		T10	4		T12	226
valid_sources[0x11]	4847	1			T3	117		T12	204		T20	1
valid_sources[0x12]	4104	1			T3	121		T11	1		T12	254
valid_sources[0x13]	5621	1			T3	105		T10	2		T12	244
valid_sources[0x14]	5100	1			T3	102		T8	2		T10	1
valid_sources[0x15]	5127	1			T3	120		T11	2		T12	297
valid_sources[0x16]	3454	1			T3	133		T10	1		T11	2
valid_sources[0x17]	4211	1			T3	117		T8	1		T12	253
valid_sources[0x18]	4716	1			T3	125		T5	2		T11	3
valid_sources[0x19]	5775	1			T3	108		T12	163		T54	10
valid_sources[0x1a]	4936	1			T3	125		T12	223		T54	4
valid_sources[0x1b]	4817	1			T3	152		T12	230		T15	604
valid_sources[0x1c]	5237	1			T3	112		T12	210		T15	1033
valid_sources[0x1d]	5193	1			T1	1		T3	132		T5	2
valid_sources[0x1e]	5308	1			T3	126		T10	1		T12	216
valid_sources[0x1f]	4889	1			T3	128		T11	1		T12	160
valid_sources[0x20]	4127	1			T3	127		T10	1		T12	204
valid_sources[0x21]	4080	1			T3	126		T12	208		T15	172
valid_sources[0x22]	4186	1			T3	123		T8	1		T10	1
valid_sources[0x23]	6134	1			T3	132		T10	1		T12	254
valid_sources[0x24]	4685	1			T3	132		T12	270		T15	643
valid_sources[0x25]	4520	1			T3	155		T10	1		T12	205
valid_sources[0x26]	5250	1			T3	121		T8	1		T12	240
valid_sources[0x27]	5718	1			T3	124		T12	218		T13	1
valid_sources[0x28]	5788	1			T3	129		T5	1		T10	1
valid_sources[0x29]	4897	1			T3	115		T12	232		T13	3
valid_sources[0x2a]	5872	1			T3	133		T12	167		T15	628
valid_sources[0x2b]	3896	1			T3	115		T12	233		T15	858
valid_sources[0x2c]	4316	1			T3	133		T12	216		T15	949
valid_sources[0x2d]	5295	1			T3	127		T9	8		T12	160
valid_sources[0x2e]	5315	1			T3	122		T12	218		T15	408
valid_sources[0x2f]	4878	1			T3	141		T10	1		T12	214
valid_sources[0x30]	5132	1			T3	121		T10	1		T11	1
valid_sources[0x31]	4482	1			T3	142		T5	2		T12	275
valid_sources[0x32]	4945	1			T3	121		T8	1		T10	1
valid_sources[0x33]	5775	1			T3	160		T12	281		T15	456
valid_sources[0x34]	6443	1			T3	130		T12	171		T13	2
valid_sources[0x35]	3984	1			T3	114		T10	1		T12	246
valid_sources[0x36]	4544	1			T3	111		T12	200		T15	517
valid_sources[0x37]	4355	1			T3	122		T12	266		T15	287
valid_sources[0x38]	4930	1			T3	122		T8	1		T12	200
valid_sources[0x39]	4417	1			T3	131		T12	171		T15	429
valid_sources[0x3a]	5010	1			T3	113		T5	2		T23	9
valid_sources[0x3b]	4424	1			T3	115		T12	218		T13	1
valid_sources[0x3c]	4813	1			T3	116		T10	2		T12	115
valid_sources[0x3d]	4109	1			T3	133		T12	213		T54	2
valid_sources[0x3e]	4828	1			T3	99		T12	185		T15	658
valid_sources[0x3f]	4752	1			T3	107		T12	185		T15	958
valid_sources[0x40]	5797	1			T3	152		T12	161		T13	2
valid_sources[0x41]	4914	1			T3	121		T10	1		T12	172
valid_sources[0x42]	4557	1			T3	129		T12	168		T13	1
valid_sources[0x43]	4788	1			T3	122		T10	3		T12	284
valid_sources[0x44]	4932	1			T3	124		T12	285		T54	19
valid_sources[0x45]	5626	1			T3	154		T10	2		T12	190
valid_sources[0x46]	5630	1			T3	119		T10	1		T12	224
valid_sources[0x47]	4579	1			T1	1		T3	127		T12	184
valid_sources[0x48]	3904	1			T3	114		T12	239		T15	731
valid_sources[0x49]	6334	1			T1	1		T3	126		T12	226
valid_sources[0x4a]	5211	1			T3	150		T11	1		T12	357
valid_sources[0x4b]	5413	1			T3	119		T10	2		T12	157
valid_sources[0x4c]	3755	1			T3	106		T10	2		T12	219
valid_sources[0x4d]	5466	1			T3	137		T12	212		T15	736
valid_sources[0x4e]	4933	1			T3	148		T12	203		T15	567
valid_sources[0x4f]	4029	1			T3	142		T10	1		T12	232
valid_sources[0x50]	3860	1			T3	127		T10	1		T12	240
valid_sources[0x51]	4776	1			T3	138		T12	196		T15	276
valid_sources[0x52]	5006	1			T3	120		T12	256		T15	333
valid_sources[0x53]	5164	1			T3	158		T8	2		T10	1
valid_sources[0x54]	4560	1			T3	108		T10	1		T12	215
valid_sources[0x55]	4929	1			T3	151		T12	207		T15	603
valid_sources[0x56]	5242	1			T3	128		T12	187		T15	260
valid_sources[0x57]	4107	1			T3	127		T12	193		T15	674
valid_sources[0x58]	4430	1			T3	126		T12	214		T15	778
valid_sources[0x59]	4495	1			T3	115		T5	1		T12	174
valid_sources[0x5a]	4738	1			T1	1		T3	130		T12	204
valid_sources[0x5b]	4560	1			T1	1		T3	138		T10	1
valid_sources[0x5c]	4803	1			T3	110		T12	190		T13	1
valid_sources[0x5d]	4160	1			T3	118		T12	203		T20	2
valid_sources[0x5e]	5038	1			T3	125		T12	231		T15	218
valid_sources[0x5f]	5309	1			T3	112		T12	156		T15	744
valid_sources[0x60]	4491	1			T1	1		T3	112		T10	1
valid_sources[0x61]	5247	1			T3	130		T10	1		T12	196
valid_sources[0x62]	3981	1			T3	107		T12	146		T13	2
valid_sources[0x63]	5354	1			T3	125		T10	1		T12	199
valid_sources[0x64]	3787	1			T1	1		T3	128		T12	183
valid_sources[0x65]	4843	1			T3	122		T12	238		T20	3
valid_sources[0x66]	4038	1			T3	124		T12	195		T15	229
valid_sources[0x67]	3217	1			T3	88		T10	1		T12	188
valid_sources[0x68]	3624	1			T3	134		T12	281		T13	2
valid_sources[0x69]	4394	1			T3	153		T5	2		T12	223
valid_sources[0x6a]	5217	1			T3	121		T12	202		T13	1
valid_sources[0x6b]	5372	1			T3	140		T12	217		T15	132
valid_sources[0x6c]	5570	1			T3	151		T12	245		T15	584
valid_sources[0x6d]	4524	1			T3	124		T12	221		T15	561
valid_sources[0x6e]	5317	1			T3	132		T10	1		T12	270
valid_sources[0x6f]	4640	1			T3	126		T12	261		T15	399
valid_sources[0x70]	4527	1			T3	120		T12	166		T13	1
valid_sources[0x71]	4849	1			T3	120		T12	205		T15	764
valid_sources[0x72]	5391	1			T3	144		T10	1		T12	197
valid_sources[0x73]	4690	1			T3	121		T10	1		T12	227
valid_sources[0x74]	5032	1			T3	149		T10	1		T11	3
valid_sources[0x75]	5176	1			T3	116		T12	187		T15	292
valid_sources[0x76]	4944	1			T3	147		T8	1		T10	1
valid_sources[0x77]	5339	1			T2	96		T3	145		T12	225
valid_sources[0x78]	4284	1			T3	133		T12	169		T15	287
valid_sources[0x79]	4720	1			T3	114		T10	2		T11	1
valid_sources[0x7a]	4715	1			T3	129		T12	211		T15	621
valid_sources[0x7b]	5229	1			T3	130		T12	215		T20	6
valid_sources[0x7c]	4130	1			T3	168		T12	172		T15	510
valid_sources[0x7d]	3659	1			T3	136		T10	1		T12	165
valid_sources[0x7e]	4703	1			T3	143		T12	225		T15	616
valid_sources[0x7f]	5103	1			T3	128		T8	1		T11	1
valid_sources[0x80]	4542	1			T3	152		T10	1		T12	183

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

283754

1

T2

61

T3

7741

T4

1

values[0x0]

all_enables

biggest_size

416521

1

T3

10896

T12

18427

T15

48126

values[0x1]

all_enables

biggest_size

416668

1

T3

11137

T23

1

T12

18450