Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2690395

1

T2

178

T3

73636

T5

73

full_word

1718018

1

T2

16

T3

47577

T5

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4408093	1			T2	194		T3	121213		T5	83
auto[TlIntgErrCmd]	116	1			T44	8		T45	7		T46	6
auto[TlIntgErrData]	93	1			T44	7		T45	5		T46	3
auto[TlIntgErrBoth]	111	1			T44	5		T45	8		T46	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

702835

1

T2

194

T3

18888

T5

83

auto[1]

3705578

1

T3

102325

T12

177919

T15

424284

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	296375	1			T2	178		T3	7714		T5	73
auto[TlIntgErrNone]	partial	auto[1]	2393730	1			T3	65922		T12	115102		T15	275348
auto[TlIntgErrNone]	full_word	auto[0]	406319	1			T2	16		T3	11174		T5	10
auto[TlIntgErrNone]	full_word	auto[1]	1311669	1			T3	36403		T12	62817		T15	148936
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T45	2		T46	3		T102	1
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T44	7		T45	3		T46	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T45	1		T109	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T44	1		T45	1		T102	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T44	4		T45	4		T46	1
auto[TlIntgErrData]	partial	auto[1]	31	1			T44	2		T46	1		T102	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T45	1		T46	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T44	1		T102	1		T105	2
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T44	1		T45	1		T46	6
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T44	4		T45	6		T46	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T45	1		T111	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T46	1		T102	1		T112	1