Unified Coverage Report :: Module :: rom_ctrl_regs_csr_assert_fpv

Module : rom_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rom_ctrl_csr_assert_0/rom_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rom_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rom_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.05	100.00	98.28	97.26		100.00	69.70	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rom_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	215029614	1992243	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215029614	1992243	0	0
T3	193396	54168	0	0
T4	98771	0	0	0
T5	214510	0	0	0
T6	210207	0	0	0
T7	795344	0	0	0
T8	136587	0	0	0
T9	128183	0	0	0
T10	845820	0	0	0
T11	280558	0	0	0
T12	0	92682	0	0
T15	0	223337	0	0
T16	0	105462	0	0
T18	0	133746	0	0
T23	8510	0	0	0
T39	0	64146	0	0
T40	0	243422	0	0
T41	0	121831	0	0
T42	0	37798	0	0
T43	0	177859	0	0