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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.32 96.89 92.42 97.67 100.00 98.62 97.30 98.37


Total test records in report: 462
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T295 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2589871133 Jul 20 04:57:32 PM PDT 24 Jul 20 04:57:42 PM PDT 24 2073454315 ps
T296 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1609507716 Jul 20 04:57:49 PM PDT 24 Jul 20 04:58:18 PM PDT 24 3426464867 ps
T297 /workspace/coverage/default/34.rom_ctrl_smoke.1216660979 Jul 20 04:57:26 PM PDT 24 Jul 20 04:57:56 PM PDT 24 18138437744 ps
T298 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2567414067 Jul 20 04:56:12 PM PDT 24 Jul 20 04:59:13 PM PDT 24 32982661467 ps
T299 /workspace/coverage/default/10.rom_ctrl_smoke.121243493 Jul 20 04:55:58 PM PDT 24 Jul 20 04:56:10 PM PDT 24 184494895 ps
T300 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.830415940 Jul 20 04:55:41 PM PDT 24 Jul 20 04:55:47 PM PDT 24 96332561 ps
T301 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1128680021 Jul 20 04:57:14 PM PDT 24 Jul 20 04:57:22 PM PDT 24 360108056 ps
T302 /workspace/coverage/default/27.rom_ctrl_smoke.275829453 Jul 20 04:56:59 PM PDT 24 Jul 20 04:57:31 PM PDT 24 61091198290 ps
T303 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3439818750 Jul 20 04:56:51 PM PDT 24 Jul 20 05:00:51 PM PDT 24 138463104203 ps
T304 /workspace/coverage/default/42.rom_ctrl_smoke.2367233036 Jul 20 04:57:50 PM PDT 24 Jul 20 04:58:01 PM PDT 24 187641388 ps
T305 /workspace/coverage/default/18.rom_ctrl_smoke.615147967 Jul 20 04:56:28 PM PDT 24 Jul 20 04:57:03 PM PDT 24 15153542598 ps
T306 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3701952730 Jul 20 04:55:50 PM PDT 24 Jul 20 04:58:59 PM PDT 24 12621414710 ps
T307 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2717344490 Jul 20 04:58:00 PM PDT 24 Jul 20 04:58:13 PM PDT 24 1657433703 ps
T308 /workspace/coverage/default/33.rom_ctrl_alert_test.858381694 Jul 20 04:57:23 PM PDT 24 Jul 20 04:57:28 PM PDT 24 518924155 ps
T309 /workspace/coverage/default/27.rom_ctrl_alert_test.4163824357 Jul 20 04:57:00 PM PDT 24 Jul 20 04:57:05 PM PDT 24 171122595 ps
T310 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4231186259 Jul 20 04:55:43 PM PDT 24 Jul 20 04:56:12 PM PDT 24 7368331943 ps
T311 /workspace/coverage/default/15.rom_ctrl_stress_all.4053140884 Jul 20 04:56:22 PM PDT 24 Jul 20 04:56:44 PM PDT 24 5982131334 ps
T312 /workspace/coverage/default/10.rom_ctrl_stress_all.1192613546 Jul 20 04:55:59 PM PDT 24 Jul 20 04:56:38 PM PDT 24 4387469358 ps
T313 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3109743425 Jul 20 04:57:58 PM PDT 24 Jul 20 04:58:04 PM PDT 24 556745326 ps
T314 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2871211882 Jul 20 04:55:42 PM PDT 24 Jul 20 04:55:48 PM PDT 24 193557120 ps
T315 /workspace/coverage/default/3.rom_ctrl_stress_all.1933760806 Jul 20 04:55:40 PM PDT 24 Jul 20 04:55:48 PM PDT 24 514910527 ps
T316 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3898711497 Jul 20 04:55:48 PM PDT 24 Jul 20 04:56:03 PM PDT 24 1803632768 ps
T317 /workspace/coverage/default/38.rom_ctrl_stress_all.2987813226 Jul 20 04:57:33 PM PDT 24 Jul 20 04:57:59 PM PDT 24 485051235 ps
T26 /workspace/coverage/default/3.rom_ctrl_sec_cm.3546773521 Jul 20 04:55:42 PM PDT 24 Jul 20 04:56:45 PM PDT 24 6389708971 ps
T318 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4002578012 Jul 20 04:57:51 PM PDT 24 Jul 20 05:02:06 PM PDT 24 19844267070 ps
T319 /workspace/coverage/default/25.rom_ctrl_smoke.3291610141 Jul 20 04:56:50 PM PDT 24 Jul 20 04:57:01 PM PDT 24 245540923 ps
T320 /workspace/coverage/default/39.rom_ctrl_alert_test.604453096 Jul 20 04:57:41 PM PDT 24 Jul 20 04:57:47 PM PDT 24 168737694 ps
T321 /workspace/coverage/default/42.rom_ctrl_alert_test.232036088 Jul 20 04:57:51 PM PDT 24 Jul 20 04:57:59 PM PDT 24 1818675187 ps
T322 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.893216541 Jul 20 04:57:04 PM PDT 24 Jul 20 05:17:26 PM PDT 24 115865233766 ps
T323 /workspace/coverage/default/31.rom_ctrl_smoke.3490268600 Jul 20 04:57:16 PM PDT 24 Jul 20 04:57:32 PM PDT 24 9560982254 ps
T324 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3409184797 Jul 20 04:57:50 PM PDT 24 Jul 20 04:58:03 PM PDT 24 1330330211 ps
T325 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.699995897 Jul 20 04:55:49 PM PDT 24 Jul 20 04:56:05 PM PDT 24 3314078783 ps
T326 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3620095106 Jul 20 04:56:09 PM PDT 24 Jul 20 04:56:27 PM PDT 24 26225306304 ps
T327 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3012658987 Jul 20 04:57:24 PM PDT 24 Jul 20 04:57:59 PM PDT 24 8364246410 ps
T328 /workspace/coverage/default/18.rom_ctrl_stress_all.473496995 Jul 20 04:56:30 PM PDT 24 Jul 20 04:56:53 PM PDT 24 1368470052 ps
T329 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1309555823 Jul 20 04:56:39 PM PDT 24 Jul 20 04:56:51 PM PDT 24 1030376268 ps
T330 /workspace/coverage/default/18.rom_ctrl_alert_test.1596750598 Jul 20 04:56:38 PM PDT 24 Jul 20 04:56:50 PM PDT 24 1538294452 ps
T331 /workspace/coverage/default/43.rom_ctrl_stress_all.215214433 Jul 20 04:57:50 PM PDT 24 Jul 20 04:58:39 PM PDT 24 18644739652 ps
T332 /workspace/coverage/default/6.rom_ctrl_alert_test.2660785006 Jul 20 04:55:52 PM PDT 24 Jul 20 04:56:08 PM PDT 24 7505489974 ps
T333 /workspace/coverage/default/23.rom_ctrl_smoke.1305752811 Jul 20 04:56:44 PM PDT 24 Jul 20 04:57:15 PM PDT 24 3848365611 ps
T334 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1331521533 Jul 20 04:57:10 PM PDT 24 Jul 20 04:57:16 PM PDT 24 94931809 ps
T335 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3784201400 Jul 20 04:55:42 PM PDT 24 Jul 20 04:55:59 PM PDT 24 7883995992 ps
T336 /workspace/coverage/default/31.rom_ctrl_stress_all.983335445 Jul 20 04:57:16 PM PDT 24 Jul 20 04:58:20 PM PDT 24 30011548150 ps
T337 /workspace/coverage/default/14.rom_ctrl_stress_all.3017290359 Jul 20 04:56:15 PM PDT 24 Jul 20 04:56:25 PM PDT 24 137521109 ps
T338 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2343299182 Jul 20 04:55:58 PM PDT 24 Jul 20 04:56:06 PM PDT 24 1410244079 ps
T339 /workspace/coverage/default/2.rom_ctrl_stress_all.3028718264 Jul 20 04:55:42 PM PDT 24 Jul 20 04:56:53 PM PDT 24 6650852138 ps
T340 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3957621258 Jul 20 04:57:41 PM PDT 24 Jul 20 05:06:09 PM PDT 24 203577442968 ps
T341 /workspace/coverage/default/6.rom_ctrl_stress_all.197193690 Jul 20 04:55:53 PM PDT 24 Jul 20 04:57:23 PM PDT 24 9475081847 ps
T342 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.311220213 Jul 20 04:56:46 PM PDT 24 Jul 20 04:56:53 PM PDT 24 1180656105 ps
T343 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1546075595 Jul 20 04:58:08 PM PDT 24 Jul 20 04:58:14 PM PDT 24 395379151 ps
T344 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2342234062 Jul 20 04:56:48 PM PDT 24 Jul 20 04:57:08 PM PDT 24 1319267210 ps
T345 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3772471283 Jul 20 04:57:16 PM PDT 24 Jul 20 04:57:34 PM PDT 24 9506360170 ps
T346 /workspace/coverage/default/12.rom_ctrl_alert_test.3107617038 Jul 20 04:56:05 PM PDT 24 Jul 20 04:56:21 PM PDT 24 3576706941 ps
T347 /workspace/coverage/default/44.rom_ctrl_smoke.1243270370 Jul 20 04:57:51 PM PDT 24 Jul 20 04:58:14 PM PDT 24 3999137611 ps
T348 /workspace/coverage/default/35.rom_ctrl_stress_all.3281469984 Jul 20 04:57:24 PM PDT 24 Jul 20 04:57:36 PM PDT 24 3486864961 ps
T349 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.207937571 Jul 20 04:56:48 PM PDT 24 Jul 20 04:56:57 PM PDT 24 172376556 ps
T350 /workspace/coverage/default/40.rom_ctrl_alert_test.1406220797 Jul 20 04:57:41 PM PDT 24 Jul 20 04:57:45 PM PDT 24 347880367 ps
T351 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4106581253 Jul 20 04:57:32 PM PDT 24 Jul 20 04:57:47 PM PDT 24 1720517925 ps
T352 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2164371337 Jul 20 04:56:58 PM PDT 24 Jul 20 04:57:30 PM PDT 24 4131387510 ps
T353 /workspace/coverage/default/32.rom_ctrl_alert_test.1819912472 Jul 20 04:57:17 PM PDT 24 Jul 20 04:57:25 PM PDT 24 1184085528 ps
T354 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3334360837 Jul 20 04:56:17 PM PDT 24 Jul 20 04:56:43 PM PDT 24 10670703027 ps
T355 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3824874437 Jul 20 04:57:52 PM PDT 24 Jul 20 05:00:52 PM PDT 24 49988720602 ps
T356 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.606390587 Jul 20 04:57:44 PM PDT 24 Jul 20 04:58:12 PM PDT 24 26565998723 ps
T357 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2729628611 Jul 20 04:57:31 PM PDT 24 Jul 20 05:01:04 PM PDT 24 38736794770 ps
T358 /workspace/coverage/default/15.rom_ctrl_smoke.4280991771 Jul 20 04:56:19 PM PDT 24 Jul 20 04:56:38 PM PDT 24 1077688083 ps
T359 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3014077566 Jul 20 04:57:14 PM PDT 24 Jul 20 04:57:24 PM PDT 24 593790708 ps
T360 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2291254458 Jul 20 04:56:30 PM PDT 24 Jul 20 04:56:42 PM PDT 24 1049022792 ps
T361 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.826073221 Jul 20 04:36:32 PM PDT 24 Jul 20 04:36:47 PM PDT 24 2138093341 ps
T58 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2947546302 Jul 20 04:36:18 PM PDT 24 Jul 20 04:36:30 PM PDT 24 2409926260 ps
T59 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1781687373 Jul 20 04:36:28 PM PDT 24 Jul 20 04:37:19 PM PDT 24 19826904869 ps
T60 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3241808226 Jul 20 04:36:33 PM PDT 24 Jul 20 04:37:30 PM PDT 24 16073035139 ps
T362 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.584173843 Jul 20 04:36:25 PM PDT 24 Jul 20 04:36:36 PM PDT 24 2030736827 ps
T363 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.948224637 Jul 20 04:36:25 PM PDT 24 Jul 20 04:36:32 PM PDT 24 177249371 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.705973657 Jul 20 04:36:22 PM PDT 24 Jul 20 04:36:38 PM PDT 24 2476871645 ps
T91 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1048495308 Jul 20 04:36:21 PM PDT 24 Jul 20 04:36:35 PM PDT 24 3000203491 ps
T94 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3028613409 Jul 20 04:36:17 PM PDT 24 Jul 20 04:36:37 PM PDT 24 8788847922 ps
T67 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3868564084 Jul 20 04:36:22 PM PDT 24 Jul 20 04:37:19 PM PDT 24 5075430488 ps
T68 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1294305268 Jul 20 04:36:34 PM PDT 24 Jul 20 04:36:52 PM PDT 24 7517228417 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1123066815 Jul 20 04:36:19 PM PDT 24 Jul 20 04:36:25 PM PDT 24 177434944 ps
T95 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4123939294 Jul 20 04:36:23 PM PDT 24 Jul 20 04:37:25 PM PDT 24 21848946772 ps
T69 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1231271666 Jul 20 04:36:17 PM PDT 24 Jul 20 04:37:25 PM PDT 24 38979705522 ps
T70 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1366967108 Jul 20 04:36:17 PM PDT 24 Jul 20 04:36:23 PM PDT 24 171904246 ps
T55 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.663034691 Jul 20 04:36:25 PM PDT 24 Jul 20 04:37:05 PM PDT 24 1095587286 ps
T365 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3233699243 Jul 20 04:36:24 PM PDT 24 Jul 20 04:36:37 PM PDT 24 1311124208 ps
T71 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3911934363 Jul 20 04:36:18 PM PDT 24 Jul 20 04:36:29 PM PDT 24 933984399 ps
T366 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2912068378 Jul 20 04:36:28 PM PDT 24 Jul 20 04:36:36 PM PDT 24 1384978182 ps
T72 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4249676698 Jul 20 04:36:15 PM PDT 24 Jul 20 04:37:03 PM PDT 24 12431865272 ps
T367 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1123147859 Jul 20 04:36:24 PM PDT 24 Jul 20 04:36:33 PM PDT 24 1771284821 ps
T368 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.562931533 Jul 20 04:36:25 PM PDT 24 Jul 20 04:36:31 PM PDT 24 348204266 ps
T56 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4109726907 Jul 20 04:36:25 PM PDT 24 Jul 20 04:37:09 PM PDT 24 2917444893 ps
T369 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3433106598 Jul 20 04:36:26 PM PDT 24 Jul 20 04:36:43 PM PDT 24 4305675400 ps
T73 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1735492306 Jul 20 04:36:37 PM PDT 24 Jul 20 04:36:54 PM PDT 24 3692662461 ps
T370 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.806167980 Jul 20 04:36:18 PM PDT 24 Jul 20 04:36:35 PM PDT 24 2031439348 ps
T74 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3944540051 Jul 20 04:36:31 PM PDT 24 Jul 20 04:36:37 PM PDT 24 346819708 ps
T75 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3858467576 Jul 20 04:36:13 PM PDT 24 Jul 20 04:36:25 PM PDT 24 1975862841 ps
T92 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3709716810 Jul 20 04:36:38 PM PDT 24 Jul 20 04:36:52 PM PDT 24 2939964968 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.99175157 Jul 20 04:36:19 PM PDT 24 Jul 20 04:36:37 PM PDT 24 9034265275 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1670029694 Jul 20 04:36:12 PM PDT 24 Jul 20 04:36:29 PM PDT 24 2092287043 ps
T81 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3452262681 Jul 20 04:36:30 PM PDT 24 Jul 20 04:37:54 PM PDT 24 36996879910 ps
T57 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3500102007 Jul 20 04:36:29 PM PDT 24 Jul 20 04:37:39 PM PDT 24 755491756 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2962203039 Jul 20 04:36:25 PM PDT 24 Jul 20 04:36:32 PM PDT 24 343887733 ps
T82 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3582232449 Jul 20 04:36:30 PM PDT 24 Jul 20 04:36:50 PM PDT 24 1987346044 ps
T102 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3884880277 Jul 20 04:36:36 PM PDT 24 Jul 20 04:37:16 PM PDT 24 569664786 ps
T374 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1971038609 Jul 20 04:36:24 PM PDT 24 Jul 20 04:36:31 PM PDT 24 186924422 ps
T375 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.622880165 Jul 20 04:36:18 PM PDT 24 Jul 20 04:36:34 PM PDT 24 5056598504 ps
T376 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1274100462 Jul 20 04:36:21 PM PDT 24 Jul 20 04:36:30 PM PDT 24 2580613991 ps
T377 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2712156480 Jul 20 04:36:29 PM PDT 24 Jul 20 04:36:38 PM PDT 24 920851393 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.722573304 Jul 20 04:36:17 PM PDT 24 Jul 20 04:36:31 PM PDT 24 1556683269 ps
T379 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2428402252 Jul 20 04:36:24 PM PDT 24 Jul 20 04:36:34 PM PDT 24 255142045 ps
T103 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1515418859 Jul 20 04:36:19 PM PDT 24 Jul 20 04:37:35 PM PDT 24 1411825267 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3514707667 Jul 20 04:36:19 PM PDT 24 Jul 20 04:36:25 PM PDT 24 90212198 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1020216761 Jul 20 04:36:25 PM PDT 24 Jul 20 04:36:44 PM PDT 24 2162406045 ps
T382 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3154611700 Jul 20 04:36:19 PM PDT 24 Jul 20 04:36:38 PM PDT 24 3871654648 ps
T383 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.59521316 Jul 20 04:36:25 PM PDT 24 Jul 20 04:36:32 PM PDT 24 288133864 ps
T384 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1524957367 Jul 20 04:36:25 PM PDT 24 Jul 20 04:36:40 PM PDT 24 6006887616 ps
T385 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1726431346 Jul 20 04:36:15 PM PDT 24 Jul 20 04:36:26 PM PDT 24 1901455858 ps
T386 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3909084406 Jul 20 04:36:14 PM PDT 24 Jul 20 04:36:20 PM PDT 24 85479167 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.853252164 Jul 20 04:36:20 PM PDT 24 Jul 20 04:36:36 PM PDT 24 1664200683 ps
T97 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1049144994 Jul 20 04:36:30 PM PDT 24 Jul 20 04:37:46 PM PDT 24 1394770834 ps
T107 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4055998578 Jul 20 04:36:30 PM PDT 24 Jul 20 04:37:17 PM PDT 24 3346470761 ps
T388 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3738723243 Jul 20 04:36:39 PM PDT 24 Jul 20 04:36:45 PM PDT 24 361404172 ps
T98 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2503362110 Jul 20 04:36:17 PM PDT 24 Jul 20 04:37:27 PM PDT 24 221376350 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3742530079 Jul 20 04:36:19 PM PDT 24 Jul 20 04:36:26 PM PDT 24 430871334 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2705210962 Jul 20 04:36:16 PM PDT 24 Jul 20 04:36:26 PM PDT 24 1658023918 ps
T104 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.732218492 Jul 20 04:36:15 PM PDT 24 Jul 20 04:37:30 PM PDT 24 2843535953 ps
T391 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3435743997 Jul 20 04:36:29 PM PDT 24 Jul 20 04:36:45 PM PDT 24 7651788157 ps
T392 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2436063909 Jul 20 04:36:13 PM PDT 24 Jul 20 04:36:43 PM PDT 24 1555733668 ps
T393 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2939764875 Jul 20 04:36:28 PM PDT 24 Jul 20 04:36:34 PM PDT 24 105091842 ps
T99 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1630880893 Jul 20 04:36:30 PM PDT 24 Jul 20 04:37:42 PM PDT 24 974323632 ps
T394 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2692391798 Jul 20 04:36:24 PM PDT 24 Jul 20 04:36:35 PM PDT 24 976835051 ps
T395 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.461189523 Jul 20 04:36:24 PM PDT 24 Jul 20 04:36:39 PM PDT 24 4258997978 ps
T83 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3352146031 Jul 20 04:36:37 PM PDT 24 Jul 20 04:36:48 PM PDT 24 4066066313 ps
T396 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4111815410 Jul 20 04:36:32 PM PDT 24 Jul 20 04:36:41 PM PDT 24 703857690 ps
T109 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4088260462 Jul 20 04:36:20 PM PDT 24 Jul 20 04:37:09 PM PDT 24 8355861805 ps
T397 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3112419274 Jul 20 04:36:15 PM PDT 24 Jul 20 04:36:32 PM PDT 24 21479047343 ps
T398 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3658719567 Jul 20 04:36:31 PM PDT 24 Jul 20 04:36:41 PM PDT 24 991927981 ps
T399 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.932341192 Jul 20 04:36:15 PM PDT 24 Jul 20 04:36:30 PM PDT 24 3207991538 ps
T100 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4275385238 Jul 20 04:36:17 PM PDT 24 Jul 20 04:37:35 PM PDT 24 1832781593 ps
T400 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2264177804 Jul 20 04:36:39 PM PDT 24 Jul 20 04:36:50 PM PDT 24 973761574 ps
T401 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2718380440 Jul 20 04:36:30 PM PDT 24 Jul 20 04:36:48 PM PDT 24 8823847072 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4187121552 Jul 20 04:36:28 PM PDT 24 Jul 20 04:36:43 PM PDT 24 1815733011 ps
T403 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.628562755 Jul 20 04:36:29 PM PDT 24 Jul 20 04:37:17 PM PDT 24 9759124424 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3481066021 Jul 20 04:36:29 PM PDT 24 Jul 20 04:36:46 PM PDT 24 8738496816 ps
T405 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.574979753 Jul 20 04:36:17 PM PDT 24 Jul 20 04:36:30 PM PDT 24 4919484142 ps
T406 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.846868875 Jul 20 04:36:30 PM PDT 24 Jul 20 04:36:37 PM PDT 24 96528816 ps
T407 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3162022306 Jul 20 04:36:37 PM PDT 24 Jul 20 04:36:43 PM PDT 24 102653331 ps
T408 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.348602981 Jul 20 04:36:28 PM PDT 24 Jul 20 04:36:36 PM PDT 24 387010130 ps
T409 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3742289826 Jul 20 04:36:23 PM PDT 24 Jul 20 04:37:49 PM PDT 24 37396917027 ps
T108 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4112894732 Jul 20 04:36:19 PM PDT 24 Jul 20 04:37:32 PM PDT 24 1835695118 ps
T410 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2269926559 Jul 20 04:36:37 PM PDT 24 Jul 20 04:36:57 PM PDT 24 1647117605 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1274828992 Jul 20 04:36:28 PM PDT 24 Jul 20 04:36:44 PM PDT 24 1760686329 ps
T412 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.897860111 Jul 20 04:36:20 PM PDT 24 Jul 20 04:36:37 PM PDT 24 6395638999 ps
T413 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.123760946 Jul 20 04:36:16 PM PDT 24 Jul 20 04:36:26 PM PDT 24 350749025 ps
T414 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4038688432 Jul 20 04:36:31 PM PDT 24 Jul 20 04:36:38 PM PDT 24 636812971 ps
T415 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2988624828 Jul 20 04:36:27 PM PDT 24 Jul 20 04:36:32 PM PDT 24 105126128 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3450960490 Jul 20 04:36:15 PM PDT 24 Jul 20 04:36:32 PM PDT 24 4240735797 ps
T417 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2150090583 Jul 20 04:36:19 PM PDT 24 Jul 20 04:36:28 PM PDT 24 2332663107 ps
T418 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2093265182 Jul 20 04:36:29 PM PDT 24 Jul 20 04:37:18 PM PDT 24 24269569734 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3264014845 Jul 20 04:36:12 PM PDT 24 Jul 20 04:36:21 PM PDT 24 374249995 ps
T420 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3065192601 Jul 20 04:36:30 PM PDT 24 Jul 20 04:36:39 PM PDT 24 1733543180 ps
T421 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1203568826 Jul 20 04:36:30 PM PDT 24 Jul 20 04:36:44 PM PDT 24 1672982103 ps
T84 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3307345001 Jul 20 04:36:32 PM PDT 24 Jul 20 04:37:16 PM PDT 24 4157512570 ps
T85 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1224868892 Jul 20 04:36:25 PM PDT 24 Jul 20 04:37:04 PM PDT 24 12463225565 ps
T422 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3767199986 Jul 20 04:36:30 PM PDT 24 Jul 20 04:36:38 PM PDT 24 89242977 ps
T423 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2915909503 Jul 20 04:36:21 PM PDT 24 Jul 20 04:36:34 PM PDT 24 5118726868 ps
T424 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1568516923 Jul 20 04:36:24 PM PDT 24 Jul 20 04:36:44 PM PDT 24 7581566527 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2141242639 Jul 20 04:36:15 PM PDT 24 Jul 20 04:36:29 PM PDT 24 1530322599 ps
T426 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.230402964 Jul 20 04:36:24 PM PDT 24 Jul 20 04:37:15 PM PDT 24 4111775404 ps
T427 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.859730387 Jul 20 04:36:29 PM PDT 24 Jul 20 04:36:43 PM PDT 24 10299716587 ps
T428 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.511166721 Jul 20 04:36:16 PM PDT 24 Jul 20 04:36:30 PM PDT 24 1979939786 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1502037834 Jul 20 04:36:15 PM PDT 24 Jul 20 04:36:30 PM PDT 24 5269422763 ps
T430 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.498554142 Jul 20 04:36:19 PM PDT 24 Jul 20 04:36:34 PM PDT 24 1009638858 ps
T431 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1486813536 Jul 20 04:36:20 PM PDT 24 Jul 20 04:36:32 PM PDT 24 667060183 ps
T432 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3903425277 Jul 20 04:36:28 PM PDT 24 Jul 20 04:36:40 PM PDT 24 5177908319 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1010198941 Jul 20 04:36:25 PM PDT 24 Jul 20 04:37:44 PM PDT 24 2011006867 ps
T434 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1032823245 Jul 20 04:36:29 PM PDT 24 Jul 20 04:36:36 PM PDT 24 100908666 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2778028808 Jul 20 04:36:15 PM PDT 24 Jul 20 04:36:22 PM PDT 24 183990280 ps
T105 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.619534078 Jul 20 04:36:14 PM PDT 24 Jul 20 04:37:03 PM PDT 24 10717411173 ps
T88 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3041338812 Jul 20 04:36:21 PM PDT 24 Jul 20 04:37:25 PM PDT 24 23823045763 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1262856436 Jul 20 04:36:20 PM PDT 24 Jul 20 04:36:44 PM PDT 24 6864839499 ps
T101 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1341634346 Jul 20 04:36:19 PM PDT 24 Jul 20 04:37:36 PM PDT 24 1950050719 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2726276572 Jul 20 04:36:12 PM PDT 24 Jul 20 04:36:27 PM PDT 24 6177794045 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2666103806 Jul 20 04:36:11 PM PDT 24 Jul 20 04:36:24 PM PDT 24 1493652111 ps
T438 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1802899349 Jul 20 04:36:25 PM PDT 24 Jul 20 04:36:42 PM PDT 24 1983347009 ps
T106 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.354165573 Jul 20 04:36:27 PM PDT 24 Jul 20 04:37:14 PM PDT 24 6258321944 ps
T439 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.707056248 Jul 20 04:36:21 PM PDT 24 Jul 20 04:36:38 PM PDT 24 1781932039 ps
T440 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1253421332 Jul 20 04:36:26 PM PDT 24 Jul 20 04:36:41 PM PDT 24 1279805616 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.766528228 Jul 20 04:36:19 PM PDT 24 Jul 20 04:36:35 PM PDT 24 7193067168 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2893451241 Jul 20 04:36:13 PM PDT 24 Jul 20 04:36:28 PM PDT 24 1643655829 ps
T443 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3261628022 Jul 20 04:36:23 PM PDT 24 Jul 20 04:36:28 PM PDT 24 346583404 ps
T444 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1480698054 Jul 20 04:36:25 PM PDT 24 Jul 20 04:36:41 PM PDT 24 2106668372 ps
T445 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1260717213 Jul 20 04:36:24 PM PDT 24 Jul 20 04:36:37 PM PDT 24 2651311646 ps
T89 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3025737112 Jul 20 04:36:28 PM PDT 24 Jul 20 04:36:34 PM PDT 24 88975927 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2742529587 Jul 20 04:36:13 PM PDT 24 Jul 20 04:36:22 PM PDT 24 1921435873 ps
T87 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1428610955 Jul 20 04:36:21 PM PDT 24 Jul 20 04:37:18 PM PDT 24 62833515978 ps
T447 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1081534938 Jul 20 04:36:32 PM PDT 24 Jul 20 04:37:09 PM PDT 24 5396492971 ps
T448 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.537807185 Jul 20 04:36:37 PM PDT 24 Jul 20 04:36:48 PM PDT 24 537894587 ps
T449 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2459392008 Jul 20 04:36:28 PM PDT 24 Jul 20 04:36:40 PM PDT 24 1116096971 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2534640181 Jul 20 04:36:22 PM PDT 24 Jul 20 04:36:37 PM PDT 24 1861439953 ps
T451 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.985680073 Jul 20 04:36:28 PM PDT 24 Jul 20 04:36:39 PM PDT 24 4104283170 ps
T90 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3714901496 Jul 20 04:36:19 PM PDT 24 Jul 20 04:36:25 PM PDT 24 220288610 ps
T452 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3281819799 Jul 20 04:36:19 PM PDT 24 Jul 20 04:37:19 PM PDT 24 48110002838 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.730272018 Jul 20 04:36:11 PM PDT 24 Jul 20 04:36:26 PM PDT 24 1713369167 ps
T454 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4011369711 Jul 20 04:36:31 PM PDT 24 Jul 20 04:36:41 PM PDT 24 222410545 ps
T455 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2174349029 Jul 20 04:36:30 PM PDT 24 Jul 20 04:36:50 PM PDT 24 8667217980 ps
T456 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.960889271 Jul 20 04:36:14 PM PDT 24 Jul 20 04:36:23 PM PDT 24 837595545 ps
T457 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.234647066 Jul 20 04:36:14 PM PDT 24 Jul 20 04:36:26 PM PDT 24 6619576901 ps
T458 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3241456993 Jul 20 04:36:28 PM PDT 24 Jul 20 04:37:05 PM PDT 24 165264044 ps
T459 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1258373989 Jul 20 04:36:21 PM PDT 24 Jul 20 04:37:35 PM PDT 24 5358053085 ps
T460 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3977453473 Jul 20 04:36:24 PM PDT 24 Jul 20 04:36:33 PM PDT 24 6527971780 ps
T461 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1121464176 Jul 20 04:36:30 PM PDT 24 Jul 20 04:36:41 PM PDT 24 274915945 ps
T462 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3774262249 Jul 20 04:36:30 PM PDT 24 Jul 20 04:36:50 PM PDT 24 1997587932 ps

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2396468094
Short name T10
Test name
Test status
Simulation time 26493889527 ps
CPU time 124.72 seconds
Started Jul 20 04:55:57 PM PDT 24
Finished Jul 20 04:58:03 PM PDT 24
Peak memory 219332 kb
Host smart-acf039c7-ba5f-4dce-97de-46183f3c0f29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396468094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2396468094
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.4019731566
Short name T11
Test name
Test status
Simulation time 600756396372 ps
CPU time 3658.05 seconds
Started Jul 20 04:56:01 PM PDT 24
Finished Jul 20 05:57:01 PM PDT 24
Peak memory 252116 kb
Host smart-6ae431e3-ed65-444b-94c6-ea8baf82cc54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019731566 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.4019731566
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3975494158
Short name T14
Test name
Test status
Simulation time 145640554310 ps
CPU time 312.23 seconds
Started Jul 20 04:56:58 PM PDT 24
Finished Jul 20 05:02:12 PM PDT 24
Peak memory 236932 kb
Host smart-3b1604a5-b9c5-4ea8-8f22-822bd34badcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975494158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3975494158
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3500102007
Short name T57
Test name
Test status
Simulation time 755491756 ps
CPU time 67.93 seconds
Started Jul 20 04:36:29 PM PDT 24
Finished Jul 20 04:37:39 PM PDT 24
Peak memory 210960 kb
Host smart-31e92242-398c-4395-a598-80fdbef42293
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500102007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3500102007
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.655142917
Short name T39
Test name
Test status
Simulation time 37701709965 ps
CPU time 346.91 seconds
Started Jul 20 04:57:33 PM PDT 24
Finished Jul 20 05:03:20 PM PDT 24
Peak memory 237868 kb
Host smart-b05467d9-bc68-4239-9ed1-ce4adddd9eaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655142917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.655142917
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1217975439
Short name T49
Test name
Test status
Simulation time 19760276054 ps
CPU time 103.23 seconds
Started Jul 20 04:56:38 PM PDT 24
Finished Jul 20 04:58:22 PM PDT 24
Peak memory 218488 kb
Host smart-2eba27b4-01bb-4271-961a-d73af9100dfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217975439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1217975439
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3759305413
Short name T21
Test name
Test status
Simulation time 1296287021 ps
CPU time 104.51 seconds
Started Jul 20 04:55:41 PM PDT 24
Finished Jul 20 04:57:26 PM PDT 24
Peak memory 236780 kb
Host smart-6baf41f5-c7aa-4f31-bcb9-4f8dabcc1da7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759305413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3759305413
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1231271666
Short name T69
Test name
Test status
Simulation time 38979705522 ps
CPU time 66.8 seconds
Started Jul 20 04:36:17 PM PDT 24
Finished Jul 20 04:37:25 PM PDT 24
Peak memory 210636 kb
Host smart-e9e7efc8-f46f-4862-b809-3f90716e3480
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231271666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1231271666
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1964696459
Short name T2
Test name
Test status
Simulation time 7629087779 ps
CPU time 14.67 seconds
Started Jul 20 04:57:26 PM PDT 24
Finished Jul 20 04:57:42 PM PDT 24
Peak memory 211364 kb
Host smart-e1dc7339-7f90-4611-a902-790a633ccf44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964696459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1964696459
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.4275385238
Short name T100
Test name
Test status
Simulation time 1832781593 ps
CPU time 77.19 seconds
Started Jul 20 04:36:17 PM PDT 24
Finished Jul 20 04:37:35 PM PDT 24
Peak memory 212128 kb
Host smart-e95127c5-caaf-4f7f-ae17-b23abf453ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275385238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.4275385238
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2213892113
Short name T4
Test name
Test status
Simulation time 7832228536 ps
CPU time 21.12 seconds
Started Jul 20 04:56:46 PM PDT 24
Finished Jul 20 04:57:08 PM PDT 24
Peak memory 212344 kb
Host smart-7fd6951a-2baa-4233-a9c6-8b387579fc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213892113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2213892113
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.433461180
Short name T123
Test name
Test status
Simulation time 335071632 ps
CPU time 9.33 seconds
Started Jul 20 04:56:37 PM PDT 24
Finished Jul 20 04:56:46 PM PDT 24
Peak memory 211904 kb
Host smart-e55f156a-6f5c-4d35-99f9-545d44d8c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433461180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.433461180
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1279117111
Short name T152
Test name
Test status
Simulation time 1707900359 ps
CPU time 12.8 seconds
Started Jul 20 04:56:18 PM PDT 24
Finished Jul 20 04:56:32 PM PDT 24
Peak memory 213400 kb
Host smart-297001e2-faad-40bc-9df5-e7c106d3faf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279117111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1279117111
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.732218492
Short name T104
Test name
Test status
Simulation time 2843535953 ps
CPU time 73.74 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:37:30 PM PDT 24
Peak memory 218676 kb
Host smart-53b03d28-73e9-40c0-8c48-baee9a3c982c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732218492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.732218492
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4112894732
Short name T108
Test name
Test status
Simulation time 1835695118 ps
CPU time 71.47 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:37:32 PM PDT 24
Peak memory 210920 kb
Host smart-0428a438-64bd-46ad-8cfd-5da641bb8d96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112894732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4112894732
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1781687373
Short name T59
Test name
Test status
Simulation time 19826904869 ps
CPU time 49.96 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:37:19 PM PDT 24
Peak memory 210628 kb
Host smart-ec15a15d-ccbb-46bd-8a1d-75a6d468d963
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781687373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1781687373
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1781707691
Short name T122
Test name
Test status
Simulation time 1170593576 ps
CPU time 12.17 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:55:46 PM PDT 24
Peak memory 211348 kb
Host smart-dbac2fbb-e54e-4a77-8806-f99feaf95719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781707691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1781707691
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2976089227
Short name T110
Test name
Test status
Simulation time 7346318732 ps
CPU time 106.44 seconds
Started Jul 20 04:55:37 PM PDT 24
Finished Jul 20 04:57:24 PM PDT 24
Peak memory 212748 kb
Host smart-ba09d709-d325-48e9-819e-7085d62713dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976089227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2976089227
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3458005703
Short name T43
Test name
Test status
Simulation time 32201158972 ps
CPU time 4770.69 seconds
Started Jul 20 04:55:35 PM PDT 24
Finished Jul 20 06:15:07 PM PDT 24
Peak memory 224456 kb
Host smart-96b3e477-845e-42eb-8439-5c1225a2cfc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458005703 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3458005703
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2141242639
Short name T425
Test name
Test status
Simulation time 1530322599 ps
CPU time 12.88 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:36:29 PM PDT 24
Peak memory 210364 kb
Host smart-7a2c502c-dd82-46a2-abeb-170db8dd7799
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141242639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2141242639
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2742529587
Short name T446
Test name
Test status
Simulation time 1921435873 ps
CPU time 7.81 seconds
Started Jul 20 04:36:13 PM PDT 24
Finished Jul 20 04:36:22 PM PDT 24
Peak memory 210456 kb
Host smart-820655e7-5115-401f-a791-5f976f6eca7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742529587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2742529587
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3858467576
Short name T75
Test name
Test status
Simulation time 1975862841 ps
CPU time 9.82 seconds
Started Jul 20 04:36:13 PM PDT 24
Finished Jul 20 04:36:25 PM PDT 24
Peak memory 210392 kb
Host smart-a6152f90-de43-4dcf-ac9d-00e2449b8749
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858467576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3858467576
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1502037834
Short name T429
Test name
Test status
Simulation time 5269422763 ps
CPU time 13.35 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:36:30 PM PDT 24
Peak memory 213756 kb
Host smart-89ac98d2-f528-406d-aeb0-b4b6cb8ebb36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502037834 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1502037834
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3909084406
Short name T386
Test name
Test status
Simulation time 85479167 ps
CPU time 4.19 seconds
Started Jul 20 04:36:14 PM PDT 24
Finished Jul 20 04:36:20 PM PDT 24
Peak memory 210360 kb
Host smart-a361a4f7-0090-4e86-bd23-5362de8ae60b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909084406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3909084406
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.730272018
Short name T453
Test name
Test status
Simulation time 1713369167 ps
CPU time 13.56 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:26 PM PDT 24
Peak memory 210264 kb
Host smart-1c6a0d02-401f-46fd-ad14-fe3fd7fc8db0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730272018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.730272018
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.574979753
Short name T405
Test name
Test status
Simulation time 4919484142 ps
CPU time 11.73 seconds
Started Jul 20 04:36:17 PM PDT 24
Finished Jul 20 04:36:30 PM PDT 24
Peak memory 210400 kb
Host smart-5f85d530-2ecd-42c4-9eab-47060ec8fb0a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574979753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
574979753
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3264014845
Short name T419
Test name
Test status
Simulation time 374249995 ps
CPU time 6.83 seconds
Started Jul 20 04:36:12 PM PDT 24
Finished Jul 20 04:36:21 PM PDT 24
Peak memory 210516 kb
Host smart-5fe68988-c554-4512-82f2-3a012f69cd90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264014845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3264014845
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2726276572
Short name T436
Test name
Test status
Simulation time 6177794045 ps
CPU time 12.7 seconds
Started Jul 20 04:36:12 PM PDT 24
Finished Jul 20 04:36:27 PM PDT 24
Peak memory 218828 kb
Host smart-84040374-fb0f-456c-8a21-d8d65eca2575
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726276572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2726276572
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2893451241
Short name T442
Test name
Test status
Simulation time 1643655829 ps
CPU time 13.31 seconds
Started Jul 20 04:36:13 PM PDT 24
Finished Jul 20 04:36:28 PM PDT 24
Peak memory 218124 kb
Host smart-c9533448-4a97-471a-a4ec-6579bfce20f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893451241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2893451241
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.932341192
Short name T399
Test name
Test status
Simulation time 3207991538 ps
CPU time 13.56 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:36:30 PM PDT 24
Peak memory 218632 kb
Host smart-7c818778-7c11-4d66-a1ba-89772ff17460
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932341192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.932341192
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2778028808
Short name T86
Test name
Test status
Simulation time 183990280 ps
CPU time 5.69 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:36:22 PM PDT 24
Peak memory 217828 kb
Host smart-6fddc37f-10b7-4d7a-9f26-15a416980747
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778028808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2778028808
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.960889271
Short name T456
Test name
Test status
Simulation time 837595545 ps
CPU time 6.89 seconds
Started Jul 20 04:36:14 PM PDT 24
Finished Jul 20 04:36:23 PM PDT 24
Peak memory 218776 kb
Host smart-ecb09862-1377-41aa-b8ac-690eb756d0a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960889271 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.960889271
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.234647066
Short name T457
Test name
Test status
Simulation time 6619576901 ps
CPU time 11.05 seconds
Started Jul 20 04:36:14 PM PDT 24
Finished Jul 20 04:36:26 PM PDT 24
Peak memory 218604 kb
Host smart-ca86ef92-8270-44c7-8c3c-578d8a0f1a08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234647066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.234647066
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1670029694
Short name T372
Test name
Test status
Simulation time 2092287043 ps
CPU time 15.37 seconds
Started Jul 20 04:36:12 PM PDT 24
Finished Jul 20 04:36:29 PM PDT 24
Peak memory 210272 kb
Host smart-d275d828-3abc-4907-93d6-94fb0a087c9d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670029694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1670029694
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1726431346
Short name T385
Test name
Test status
Simulation time 1901455858 ps
CPU time 9.13 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:36:26 PM PDT 24
Peak memory 210216 kb
Host smart-e2961dff-1724-48a5-a6f5-2abe5e73d15f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726431346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1726431346
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2436063909
Short name T392
Test name
Test status
Simulation time 1555733668 ps
CPU time 27.65 seconds
Started Jul 20 04:36:13 PM PDT 24
Finished Jul 20 04:36:43 PM PDT 24
Peak memory 210456 kb
Host smart-f12a6dbd-7e7d-4603-95da-edda0d00a301
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436063909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2436063909
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3112419274
Short name T397
Test name
Test status
Simulation time 21479047343 ps
CPU time 15.58 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:36:32 PM PDT 24
Peak memory 210672 kb
Host smart-6d04a71b-b232-4165-a0d2-cf0278007ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112419274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3112419274
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2705210962
Short name T390
Test name
Test status
Simulation time 1658023918 ps
CPU time 8.74 seconds
Started Jul 20 04:36:16 PM PDT 24
Finished Jul 20 04:36:26 PM PDT 24
Peak memory 218720 kb
Host smart-7701a4b0-c10a-4317-8479-943716855f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705210962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2705210962
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3433106598
Short name T369
Test name
Test status
Simulation time 4305675400 ps
CPU time 15.79 seconds
Started Jul 20 04:36:26 PM PDT 24
Finished Jul 20 04:36:43 PM PDT 24
Peak memory 218864 kb
Host smart-5d242530-b74b-4081-8712-1d6804415b3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433106598 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3433106598
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.562931533
Short name T368
Test name
Test status
Simulation time 348204266 ps
CPU time 4.19 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:36:31 PM PDT 24
Peak memory 210464 kb
Host smart-76fee322-ff21-439a-a9b1-8e9442b07a00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562931533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.562931533
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3742289826
Short name T409
Test name
Test status
Simulation time 37396917027 ps
CPU time 85.45 seconds
Started Jul 20 04:36:23 PM PDT 24
Finished Jul 20 04:37:49 PM PDT 24
Peak memory 210628 kb
Host smart-702551e2-4f47-4e08-b064-b8430ef50d6d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742289826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3742289826
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1480698054
Short name T444
Test name
Test status
Simulation time 2106668372 ps
CPU time 14.71 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:36:41 PM PDT 24
Peak memory 210548 kb
Host smart-d636822f-933e-4105-b31d-e3aecdfa04af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480698054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1480698054
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1524957367
Short name T384
Test name
Test status
Simulation time 6006887616 ps
CPU time 13.89 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:36:40 PM PDT 24
Peak memory 215740 kb
Host smart-f9d54c09-4076-46bf-8177-f8fed981081e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524957367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1524957367
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1010198941
Short name T433
Test name
Test status
Simulation time 2011006867 ps
CPU time 77.17 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:37:44 PM PDT 24
Peak memory 211892 kb
Host smart-100c400c-4543-40a5-99d9-521e323bb135
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010198941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1010198941
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.985680073
Short name T451
Test name
Test status
Simulation time 4104283170 ps
CPU time 10.13 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:36:39 PM PDT 24
Peak memory 211828 kb
Host smart-9a4a2e08-42c9-4326-b5f5-0379ca7b62d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985680073 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.985680073
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1274100462
Short name T376
Test name
Test status
Simulation time 2580613991 ps
CPU time 8.22 seconds
Started Jul 20 04:36:21 PM PDT 24
Finished Jul 20 04:36:30 PM PDT 24
Peak memory 210760 kb
Host smart-127ca984-8ab6-49cb-871e-9e043faa87d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274100462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1274100462
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1224868892
Short name T85
Test name
Test status
Simulation time 12463225565 ps
CPU time 38.19 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:37:04 PM PDT 24
Peak memory 210672 kb
Host smart-64db1f6c-0576-44b9-bf3c-2ed65c855e53
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224868892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1224868892
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.707056248
Short name T439
Test name
Test status
Simulation time 1781932039 ps
CPU time 16.46 seconds
Started Jul 20 04:36:21 PM PDT 24
Finished Jul 20 04:36:38 PM PDT 24
Peak memory 210564 kb
Host smart-1b0569aa-4bc9-43e9-bc18-55fa4f06e0e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707056248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.707056248
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1253421332
Short name T440
Test name
Test status
Simulation time 1279805616 ps
CPU time 13.62 seconds
Started Jul 20 04:36:26 PM PDT 24
Finished Jul 20 04:36:41 PM PDT 24
Peak memory 218688 kb
Host smart-ba5fdab6-e450-4a0f-8051-329e40b86cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253421332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1253421332
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.4088260462
Short name T109
Test name
Test status
Simulation time 8355861805 ps
CPU time 47.4 seconds
Started Jul 20 04:36:20 PM PDT 24
Finished Jul 20 04:37:09 PM PDT 24
Peak memory 218796 kb
Host smart-172ef833-1ab1-42ae-a060-acfdaf1c9e88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088260462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.4088260462
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2939764875
Short name T393
Test name
Test status
Simulation time 105091842 ps
CPU time 5.14 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:36:34 PM PDT 24
Peak memory 218668 kb
Host smart-81ebc10f-8035-440b-a54e-d7d8ffefadc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939764875 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2939764875
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3065192601
Short name T420
Test name
Test status
Simulation time 1733543180 ps
CPU time 7.12 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:36:39 PM PDT 24
Peak memory 210340 kb
Host smart-dd783ebd-1f6e-4441-908b-354da17c4809
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065192601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3065192601
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2712156480
Short name T377
Test name
Test status
Simulation time 920851393 ps
CPU time 7.27 seconds
Started Jul 20 04:36:29 PM PDT 24
Finished Jul 20 04:36:38 PM PDT 24
Peak memory 210496 kb
Host smart-2abd2c5f-ae38-406d-a97a-2fb215fa400f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712156480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2712156480
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.826073221
Short name T361
Test name
Test status
Simulation time 2138093341 ps
CPU time 13.69 seconds
Started Jul 20 04:36:32 PM PDT 24
Finished Jul 20 04:36:47 PM PDT 24
Peak memory 215520 kb
Host smart-e3b9d302-7bac-4caf-9909-95ded4533604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826073221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.826073221
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1049144994
Short name T97
Test name
Test status
Simulation time 1394770834 ps
CPU time 74.65 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:37:46 PM PDT 24
Peak memory 212040 kb
Host smart-385fa954-733f-4cfc-93a8-1a002b281bed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049144994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1049144994
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.846868875
Short name T406
Test name
Test status
Simulation time 96528816 ps
CPU time 4.7 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:36:37 PM PDT 24
Peak memory 213172 kb
Host smart-2eaa7227-8a5a-42d6-bd59-56ca7bc4e35d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846868875 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.846868875
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1802899349
Short name T438
Test name
Test status
Simulation time 1983347009 ps
CPU time 15.57 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:36:42 PM PDT 24
Peak memory 210684 kb
Host smart-c51cbf4f-50a6-46c6-a363-6d996e358d44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802899349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1802899349
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3452262681
Short name T81
Test name
Test status
Simulation time 36996879910 ps
CPU time 81.86 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:37:54 PM PDT 24
Peak memory 210664 kb
Host smart-299944ec-4d99-442c-98e4-80965b3dcc45
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452262681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3452262681
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1294305268
Short name T68
Test name
Test status
Simulation time 7517228417 ps
CPU time 17.49 seconds
Started Jul 20 04:36:34 PM PDT 24
Finished Jul 20 04:36:52 PM PDT 24
Peak memory 210940 kb
Host smart-08df4027-dd38-4703-8198-47a753a3ccb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294305268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1294305268
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3774262249
Short name T462
Test name
Test status
Simulation time 1997587932 ps
CPU time 18.56 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:36:50 PM PDT 24
Peak memory 218724 kb
Host smart-fbdffc51-499d-4e39-a247-95342916790d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774262249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3774262249
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3241456993
Short name T458
Test name
Test status
Simulation time 165264044 ps
CPU time 36.26 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:37:05 PM PDT 24
Peak memory 211876 kb
Host smart-9dfaa0f0-bd66-4624-ac21-c1b6592edc41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241456993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3241456993
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1032823245
Short name T434
Test name
Test status
Simulation time 100908666 ps
CPU time 5.75 seconds
Started Jul 20 04:36:29 PM PDT 24
Finished Jul 20 04:36:36 PM PDT 24
Peak memory 218676 kb
Host smart-eb0411fd-5ad1-4692-9e18-e6e413f411dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032823245 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1032823245
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2988624828
Short name T415
Test name
Test status
Simulation time 105126128 ps
CPU time 4.38 seconds
Started Jul 20 04:36:27 PM PDT 24
Finished Jul 20 04:36:32 PM PDT 24
Peak memory 210396 kb
Host smart-4b9ac65d-8792-486d-ad8a-dca42432e7a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988624828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2988624828
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3582232449
Short name T82
Test name
Test status
Simulation time 1987346044 ps
CPU time 18.72 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:36:50 PM PDT 24
Peak memory 210512 kb
Host smart-e48e4a50-fdbb-403f-a3a6-0590d2abb42c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582232449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3582232449
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3435743997
Short name T391
Test name
Test status
Simulation time 7651788157 ps
CPU time 14.57 seconds
Started Jul 20 04:36:29 PM PDT 24
Finished Jul 20 04:36:45 PM PDT 24
Peak memory 210852 kb
Host smart-862b7bc3-c677-4801-90a5-fedf686d993b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435743997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3435743997
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3767199986
Short name T422
Test name
Test status
Simulation time 89242977 ps
CPU time 6.2 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:36:38 PM PDT 24
Peak memory 215100 kb
Host smart-7db48fbf-76aa-41ff-8401-86aafd155d86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767199986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3767199986
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.354165573
Short name T106
Test name
Test status
Simulation time 6258321944 ps
CPU time 45.75 seconds
Started Jul 20 04:36:27 PM PDT 24
Finished Jul 20 04:37:14 PM PDT 24
Peak memory 210568 kb
Host smart-90197792-3e99-48f4-b39b-336966d4af30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354165573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.354165573
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1203568826
Short name T421
Test name
Test status
Simulation time 1672982103 ps
CPU time 12.98 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:36:44 PM PDT 24
Peak memory 218748 kb
Host smart-4e586861-3edd-4b1d-8ac5-e9e34221e77f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203568826 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1203568826
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3025737112
Short name T89
Test name
Test status
Simulation time 88975927 ps
CPU time 4.1 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:36:34 PM PDT 24
Peak memory 210380 kb
Host smart-adcf5608-10fd-4aeb-9efc-a3281fd2a6a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025737112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3025737112
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.628562755
Short name T403
Test name
Test status
Simulation time 9759124424 ps
CPU time 46.86 seconds
Started Jul 20 04:36:29 PM PDT 24
Finished Jul 20 04:37:17 PM PDT 24
Peak memory 210664 kb
Host smart-cfb624e5-941a-4062-a413-ee2587e612e7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628562755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.628562755
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3903425277
Short name T432
Test name
Test status
Simulation time 5177908319 ps
CPU time 10.38 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:36:40 PM PDT 24
Peak memory 211148 kb
Host smart-de92efa0-ab26-4e50-9249-b8a9eb7a5f6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903425277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3903425277
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.859730387
Short name T427
Test name
Test status
Simulation time 10299716587 ps
CPU time 12.28 seconds
Started Jul 20 04:36:29 PM PDT 24
Finished Jul 20 04:36:43 PM PDT 24
Peak memory 218744 kb
Host smart-5bdd7134-924c-4915-8b93-915f1723ad89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859730387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.859730387
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1630880893
Short name T99
Test name
Test status
Simulation time 974323632 ps
CPU time 69.4 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:37:42 PM PDT 24
Peak memory 212248 kb
Host smart-60fd82ce-1f6d-4273-b5eb-68890392a2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630880893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1630880893
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.4038688432
Short name T414
Test name
Test status
Simulation time 636812971 ps
CPU time 4.7 seconds
Started Jul 20 04:36:31 PM PDT 24
Finished Jul 20 04:36:38 PM PDT 24
Peak memory 218704 kb
Host smart-341df965-82a5-4ba2-a0de-dbd0ac524777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038688432 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.4038688432
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3944540051
Short name T74
Test name
Test status
Simulation time 346819708 ps
CPU time 4.17 seconds
Started Jul 20 04:36:31 PM PDT 24
Finished Jul 20 04:36:37 PM PDT 24
Peak memory 217532 kb
Host smart-9f09277e-52cc-4e8f-8dc3-fe67f6aaa9d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944540051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3944540051
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1081534938
Short name T447
Test name
Test status
Simulation time 5396492971 ps
CPU time 35.8 seconds
Started Jul 20 04:36:32 PM PDT 24
Finished Jul 20 04:37:09 PM PDT 24
Peak memory 210548 kb
Host smart-abb27ea1-11f5-4f18-b67f-3b75e1eb330e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081534938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1081534938
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3658719567
Short name T398
Test name
Test status
Simulation time 991927981 ps
CPU time 7.74 seconds
Started Jul 20 04:36:31 PM PDT 24
Finished Jul 20 04:36:41 PM PDT 24
Peak memory 210520 kb
Host smart-6516bf7f-1918-44a1-ad2f-1da30940da91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658719567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3658719567
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2174349029
Short name T455
Test name
Test status
Simulation time 8667217980 ps
CPU time 18.18 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:36:50 PM PDT 24
Peak memory 215484 kb
Host smart-2d0c063a-3222-4cf6-bdcb-d8577f28ee8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174349029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2174349029
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2093265182
Short name T418
Test name
Test status
Simulation time 24269569734 ps
CPU time 46.14 seconds
Started Jul 20 04:36:29 PM PDT 24
Finished Jul 20 04:37:18 PM PDT 24
Peak memory 212308 kb
Host smart-a4719c8d-711e-4bef-bbe7-6e76c70e8502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093265182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2093265182
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3481066021
Short name T404
Test name
Test status
Simulation time 8738496816 ps
CPU time 15.74 seconds
Started Jul 20 04:36:29 PM PDT 24
Finished Jul 20 04:36:46 PM PDT 24
Peak memory 218736 kb
Host smart-2e9302b8-e598-4e81-b6d8-345af0e9e2cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481066021 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3481066021
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2718380440
Short name T401
Test name
Test status
Simulation time 8823847072 ps
CPU time 16.19 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:36:48 PM PDT 24
Peak memory 218652 kb
Host smart-3576afee-4457-41e0-b342-c310cfe1bc91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718380440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2718380440
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3307345001
Short name T84
Test name
Test status
Simulation time 4157512570 ps
CPU time 41.8 seconds
Started Jul 20 04:36:32 PM PDT 24
Finished Jul 20 04:37:16 PM PDT 24
Peak memory 210636 kb
Host smart-8b82cf4e-c3df-4f22-81b6-f0d8b2375185
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307345001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3307345001
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.4111815410
Short name T396
Test name
Test status
Simulation time 703857690 ps
CPU time 7.28 seconds
Started Jul 20 04:36:32 PM PDT 24
Finished Jul 20 04:36:41 PM PDT 24
Peak memory 218272 kb
Host smart-ffb2c222-9bc3-490f-9b46-810d7d9c6222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111815410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.4111815410
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4011369711
Short name T454
Test name
Test status
Simulation time 222410545 ps
CPU time 8.6 seconds
Started Jul 20 04:36:31 PM PDT 24
Finished Jul 20 04:36:41 PM PDT 24
Peak memory 218696 kb
Host smart-6b936273-59b0-40cf-bd02-88de11353da1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011369711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4011369711
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3162022306
Short name T407
Test name
Test status
Simulation time 102653331 ps
CPU time 5.03 seconds
Started Jul 20 04:36:37 PM PDT 24
Finished Jul 20 04:36:43 PM PDT 24
Peak memory 218632 kb
Host smart-2aea5371-edeb-4309-a423-d64de3a765f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162022306 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3162022306
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2264177804
Short name T400
Test name
Test status
Simulation time 973761574 ps
CPU time 10 seconds
Started Jul 20 04:36:39 PM PDT 24
Finished Jul 20 04:36:50 PM PDT 24
Peak memory 210336 kb
Host smart-fd426eee-9b74-45e7-ae22-be3288f0cb76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264177804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2264177804
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3241808226
Short name T60
Test name
Test status
Simulation time 16073035139 ps
CPU time 55.53 seconds
Started Jul 20 04:36:33 PM PDT 24
Finished Jul 20 04:37:30 PM PDT 24
Peak memory 210636 kb
Host smart-b46bd610-0de7-4e87-a4b7-25b0c6547382
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241808226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3241808226
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1735492306
Short name T73
Test name
Test status
Simulation time 3692662461 ps
CPU time 14.88 seconds
Started Jul 20 04:36:37 PM PDT 24
Finished Jul 20 04:36:54 PM PDT 24
Peak memory 210564 kb
Host smart-670226bb-812d-4788-b6b1-01f7f7131d31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735492306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1735492306
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1121464176
Short name T461
Test name
Test status
Simulation time 274915945 ps
CPU time 9.94 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:36:41 PM PDT 24
Peak memory 218776 kb
Host smart-ccedf59f-a62b-4298-b5b3-bdd976cf5a8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121464176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1121464176
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.4055998578
Short name T107
Test name
Test status
Simulation time 3346470761 ps
CPU time 44.92 seconds
Started Jul 20 04:36:30 PM PDT 24
Finished Jul 20 04:37:17 PM PDT 24
Peak memory 218684 kb
Host smart-9a5b72e7-8f4f-456e-957f-e8862c62b3af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055998578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.4055998578
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3738723243
Short name T388
Test name
Test status
Simulation time 361404172 ps
CPU time 4.42 seconds
Started Jul 20 04:36:39 PM PDT 24
Finished Jul 20 04:36:45 PM PDT 24
Peak memory 211932 kb
Host smart-53e91cf8-ce1e-4ac0-aac9-82aa2e5189e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738723243 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3738723243
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3352146031
Short name T83
Test name
Test status
Simulation time 4066066313 ps
CPU time 9.62 seconds
Started Jul 20 04:36:37 PM PDT 24
Finished Jul 20 04:36:48 PM PDT 24
Peak memory 218428 kb
Host smart-de4c218b-bef3-4963-a2d5-d3488e01180f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352146031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3352146031
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2269926559
Short name T410
Test name
Test status
Simulation time 1647117605 ps
CPU time 18.53 seconds
Started Jul 20 04:36:37 PM PDT 24
Finished Jul 20 04:36:57 PM PDT 24
Peak memory 210496 kb
Host smart-112deb1f-9c2b-4d98-8a98-b3a1b39e1c3f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269926559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2269926559
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3709716810
Short name T92
Test name
Test status
Simulation time 2939964968 ps
CPU time 12.64 seconds
Started Jul 20 04:36:38 PM PDT 24
Finished Jul 20 04:36:52 PM PDT 24
Peak memory 218672 kb
Host smart-d4e68fde-badb-4a84-b1c0-80ea3af106f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709716810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3709716810
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.537807185
Short name T448
Test name
Test status
Simulation time 537894587 ps
CPU time 9.61 seconds
Started Jul 20 04:36:37 PM PDT 24
Finished Jul 20 04:36:48 PM PDT 24
Peak memory 218764 kb
Host smart-afa5ad1b-ead0-4d29-837f-ae05400f2baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537807185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.537807185
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3884880277
Short name T102
Test name
Test status
Simulation time 569664786 ps
CPU time 39.06 seconds
Started Jul 20 04:36:36 PM PDT 24
Finished Jul 20 04:37:16 PM PDT 24
Peak memory 218700 kb
Host smart-be6c72f2-116d-45aa-aa2b-5b21d6b772f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884880277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3884880277
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2915909503
Short name T423
Test name
Test status
Simulation time 5118726868 ps
CPU time 11.97 seconds
Started Jul 20 04:36:21 PM PDT 24
Finished Jul 20 04:36:34 PM PDT 24
Peak memory 210516 kb
Host smart-e83fab7b-f9a6-4527-a64f-c926bcc59578
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915909503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2915909503
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.806167980
Short name T370
Test name
Test status
Simulation time 2031439348 ps
CPU time 16.44 seconds
Started Jul 20 04:36:18 PM PDT 24
Finished Jul 20 04:36:35 PM PDT 24
Peak memory 210424 kb
Host smart-ba451d51-64ea-4a4d-ae69-fc96676d94ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806167980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.806167980
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.722573304
Short name T378
Test name
Test status
Simulation time 1556683269 ps
CPU time 12.15 seconds
Started Jul 20 04:36:17 PM PDT 24
Finished Jul 20 04:36:31 PM PDT 24
Peak memory 210428 kb
Host smart-fd9c8ebf-4e31-4839-8bc1-28b4247d5539
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722573304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_re
set.722573304
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1123066815
Short name T364
Test name
Test status
Simulation time 177434944 ps
CPU time 5.72 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:36:25 PM PDT 24
Peak memory 212880 kb
Host smart-e3f3ff67-8a60-4372-a5e5-687c49a516de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123066815 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1123066815
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.348602981
Short name T408
Test name
Test status
Simulation time 387010130 ps
CPU time 6.5 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:36:36 PM PDT 24
Peak memory 210456 kb
Host smart-bf128239-41e8-4c90-8001-08ed1e69128b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348602981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.348602981
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2666103806
Short name T437
Test name
Test status
Simulation time 1493652111 ps
CPU time 11.93 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:24 PM PDT 24
Peak memory 210272 kb
Host smart-fd18a1aa-2c4c-4c48-a7f4-4f84824d33a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666103806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2666103806
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3450960490
Short name T416
Test name
Test status
Simulation time 4240735797 ps
CPU time 16.1 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:36:32 PM PDT 24
Peak memory 210296 kb
Host smart-9596ec67-333c-4c0f-a3a5-785c884448a7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450960490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3450960490
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4249676698
Short name T72
Test name
Test status
Simulation time 12431865272 ps
CPU time 46.89 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:37:03 PM PDT 24
Peak memory 210556 kb
Host smart-258d8e2d-09a9-4942-81e5-8717695cc2d3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249676698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4249676698
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1020216761
Short name T381
Test name
Test status
Simulation time 2162406045 ps
CPU time 17.65 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:36:44 PM PDT 24
Peak memory 218620 kb
Host smart-dc918f9d-aed2-4964-977b-9a5351fd78d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020216761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1020216761
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.511166721
Short name T428
Test name
Test status
Simulation time 1979939786 ps
CPU time 13.15 seconds
Started Jul 20 04:36:16 PM PDT 24
Finished Jul 20 04:36:30 PM PDT 24
Peak memory 218684 kb
Host smart-487c6079-c5b2-4dc1-a9f7-b9b13d9f0951
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511166721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.511166721
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.619534078
Short name T105
Test name
Test status
Simulation time 10717411173 ps
CPU time 47.58 seconds
Started Jul 20 04:36:14 PM PDT 24
Finished Jul 20 04:37:03 PM PDT 24
Peak memory 218792 kb
Host smart-43979b61-1ae0-4f37-bcb4-6f355764ad18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619534078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.619534078
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2947546302
Short name T58
Test name
Test status
Simulation time 2409926260 ps
CPU time 11.1 seconds
Started Jul 20 04:36:18 PM PDT 24
Finished Jul 20 04:36:30 PM PDT 24
Peak memory 218352 kb
Host smart-5f0381d5-6054-4141-b546-3386f557bb31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947546302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2947546302
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2459392008
Short name T449
Test name
Test status
Simulation time 1116096971 ps
CPU time 11.14 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:36:40 PM PDT 24
Peak memory 210456 kb
Host smart-73a78a57-3b9d-4106-b8b9-d492731ae4fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459392008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2459392008
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3028613409
Short name T94
Test name
Test status
Simulation time 8788847922 ps
CPU time 19.46 seconds
Started Jul 20 04:36:17 PM PDT 24
Finished Jul 20 04:36:37 PM PDT 24
Peak memory 210548 kb
Host smart-ac2b8508-02cf-4537-a10e-7f7fcfa403df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028613409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3028613409
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3742530079
Short name T389
Test name
Test status
Simulation time 430871334 ps
CPU time 6.19 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:36:26 PM PDT 24
Peak memory 218696 kb
Host smart-3a053f13-4da9-463b-a2f2-582969f246dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742530079 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3742530079
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3714901496
Short name T90
Test name
Test status
Simulation time 220288610 ps
CPU time 4.12 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:36:25 PM PDT 24
Peak memory 217308 kb
Host smart-3a9154f3-dea2-49ad-ad1e-e787e1a09e80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714901496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3714901496
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2150090583
Short name T417
Test name
Test status
Simulation time 2332663107 ps
CPU time 7.52 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:36:28 PM PDT 24
Peak memory 210328 kb
Host smart-8c6b63b9-1e31-45da-85dc-10d7f0971375
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150090583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2150090583
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.622880165
Short name T375
Test name
Test status
Simulation time 5056598504 ps
CPU time 15.08 seconds
Started Jul 20 04:36:18 PM PDT 24
Finished Jul 20 04:36:34 PM PDT 24
Peak memory 210476 kb
Host smart-c5361d38-a316-4f18-8df7-973d881c1826
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622880165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
622880165
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3041338812
Short name T88
Test name
Test status
Simulation time 23823045763 ps
CPU time 63.58 seconds
Started Jul 20 04:36:21 PM PDT 24
Finished Jul 20 04:37:25 PM PDT 24
Peak memory 218824 kb
Host smart-1f3c6745-e6ec-4fe9-a991-ce0b28f3ac44
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041338812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3041338812
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2534640181
Short name T450
Test name
Test status
Simulation time 1861439953 ps
CPU time 14.4 seconds
Started Jul 20 04:36:22 PM PDT 24
Finished Jul 20 04:36:37 PM PDT 24
Peak memory 210508 kb
Host smart-2974723f-4c14-4f89-ac7a-87999779c761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534640181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2534640181
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1274828992
Short name T411
Test name
Test status
Simulation time 1760686329 ps
CPU time 15.15 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:36:44 PM PDT 24
Peak memory 218708 kb
Host smart-624eb524-97b8-4950-be5f-138e28f45dff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274828992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1274828992
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1515418859
Short name T103
Test name
Test status
Simulation time 1411825267 ps
CPU time 74.6 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:37:35 PM PDT 24
Peak memory 218676 kb
Host smart-0c352cf4-54fc-470e-b65d-f37466241b1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515418859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1515418859
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.766528228
Short name T441
Test name
Test status
Simulation time 7193067168 ps
CPU time 14.79 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:36:35 PM PDT 24
Peak memory 218592 kb
Host smart-371642d4-be7d-4b78-a93f-0fb43cffbb5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766528228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.766528228
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3233699243
Short name T365
Test name
Test status
Simulation time 1311124208 ps
CPU time 12.01 seconds
Started Jul 20 04:36:24 PM PDT 24
Finished Jul 20 04:36:37 PM PDT 24
Peak memory 218356 kb
Host smart-a8cc3913-0f35-43a9-a9d8-f3805bbd16e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233699243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3233699243
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2962203039
Short name T373
Test name
Test status
Simulation time 343887733 ps
CPU time 5.83 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:36:32 PM PDT 24
Peak memory 218568 kb
Host smart-37ffaa23-aca2-461e-b6c0-301e0bee9c2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962203039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2962203039
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.584173843
Short name T362
Test name
Test status
Simulation time 2030736827 ps
CPU time 10.05 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:36:36 PM PDT 24
Peak memory 218736 kb
Host smart-ce749a78-7023-401d-8a87-06729d43ce1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584173843 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.584173843
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.705973657
Short name T93
Test name
Test status
Simulation time 2476871645 ps
CPU time 16.16 seconds
Started Jul 20 04:36:22 PM PDT 24
Finished Jul 20 04:36:38 PM PDT 24
Peak memory 218036 kb
Host smart-bdc356f0-3be6-46da-ac8d-281811338b9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705973657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.705973657
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3514707667
Short name T380
Test name
Test status
Simulation time 90212198 ps
CPU time 4.15 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:36:25 PM PDT 24
Peak memory 210292 kb
Host smart-73a42605-fc16-4db5-9ae4-bec13ebdcdc6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514707667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3514707667
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.99175157
Short name T371
Test name
Test status
Simulation time 9034265275 ps
CPU time 16.32 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:36:37 PM PDT 24
Peak memory 210404 kb
Host smart-19cd31de-7a96-409a-8c67-28e575de278c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99175157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.99175157
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3868564084
Short name T67
Test name
Test status
Simulation time 5075430488 ps
CPU time 56.58 seconds
Started Jul 20 04:36:22 PM PDT 24
Finished Jul 20 04:37:19 PM PDT 24
Peak memory 210628 kb
Host smart-2085be4f-a1ac-48f2-9dcd-b2d6a052434f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868564084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3868564084
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3911934363
Short name T71
Test name
Test status
Simulation time 933984399 ps
CPU time 9.81 seconds
Started Jul 20 04:36:18 PM PDT 24
Finished Jul 20 04:36:29 PM PDT 24
Peak memory 210400 kb
Host smart-42e21d06-97d4-403b-998d-c562d4d38cad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911934363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3911934363
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.498554142
Short name T430
Test name
Test status
Simulation time 1009638858 ps
CPU time 13.61 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:36:34 PM PDT 24
Peak memory 218636 kb
Host smart-d8ac3d9e-db80-4754-a727-2abde4258f75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498554142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.498554142
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1258373989
Short name T459
Test name
Test status
Simulation time 5358053085 ps
CPU time 73.32 seconds
Started Jul 20 04:36:21 PM PDT 24
Finished Jul 20 04:37:35 PM PDT 24
Peak memory 218604 kb
Host smart-0aa73410-cbc1-4417-8f8e-d2969984125f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258373989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1258373989
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.853252164
Short name T387
Test name
Test status
Simulation time 1664200683 ps
CPU time 14.53 seconds
Started Jul 20 04:36:20 PM PDT 24
Finished Jul 20 04:36:36 PM PDT 24
Peak memory 218976 kb
Host smart-84a0b3bc-735e-4ac4-9a6b-e3be582d2b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853252164 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.853252164
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1366967108
Short name T70
Test name
Test status
Simulation time 171904246 ps
CPU time 4.12 seconds
Started Jul 20 04:36:17 PM PDT 24
Finished Jul 20 04:36:23 PM PDT 24
Peak memory 210420 kb
Host smart-eac17c80-a972-4bf9-9c18-637d4e58c487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366967108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1366967108
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1262856436
Short name T435
Test name
Test status
Simulation time 6864839499 ps
CPU time 23.07 seconds
Started Jul 20 04:36:20 PM PDT 24
Finished Jul 20 04:36:44 PM PDT 24
Peak memory 210528 kb
Host smart-dbf39dce-fd15-42cd-89a7-6fa84b980f51
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262856436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1262856436
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.123760946
Short name T413
Test name
Test status
Simulation time 350749025 ps
CPU time 8.07 seconds
Started Jul 20 04:36:16 PM PDT 24
Finished Jul 20 04:36:26 PM PDT 24
Peak memory 210544 kb
Host smart-e8557b64-5198-4735-9b4a-1bb3a34cf7af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123760946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.123760946
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3154611700
Short name T382
Test name
Test status
Simulation time 3871654648 ps
CPU time 18.06 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:36:38 PM PDT 24
Peak memory 218684 kb
Host smart-ec46cfbd-37c7-4b5f-84d8-5c9d6c4bb3dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154611700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3154611700
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.4187121552
Short name T402
Test name
Test status
Simulation time 1815733011 ps
CPU time 13.2 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:36:43 PM PDT 24
Peak memory 218736 kb
Host smart-08fd69c8-9a17-4658-904b-59cebb926626
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187121552 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4187121552
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1260717213
Short name T445
Test name
Test status
Simulation time 2651311646 ps
CPU time 12.08 seconds
Started Jul 20 04:36:24 PM PDT 24
Finished Jul 20 04:36:37 PM PDT 24
Peak memory 218588 kb
Host smart-e22d7543-b5cd-43b2-9853-ec28911811fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260717213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1260717213
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3281819799
Short name T452
Test name
Test status
Simulation time 48110002838 ps
CPU time 58.68 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:37:19 PM PDT 24
Peak memory 210664 kb
Host smart-904256bb-5991-48b1-b942-a6168ea690e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281819799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3281819799
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1048495308
Short name T91
Test name
Test status
Simulation time 3000203491 ps
CPU time 12.68 seconds
Started Jul 20 04:36:21 PM PDT 24
Finished Jul 20 04:36:35 PM PDT 24
Peak memory 210588 kb
Host smart-19ba2079-5809-4027-b2af-dd4d4873ea76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048495308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1048495308
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1486813536
Short name T431
Test name
Test status
Simulation time 667060183 ps
CPU time 10.82 seconds
Started Jul 20 04:36:20 PM PDT 24
Finished Jul 20 04:36:32 PM PDT 24
Peak memory 218760 kb
Host smart-70329a14-a37a-42a4-a3b9-e26c4ceaeedc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486813536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1486813536
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1341634346
Short name T101
Test name
Test status
Simulation time 1950050719 ps
CPU time 76.67 seconds
Started Jul 20 04:36:19 PM PDT 24
Finished Jul 20 04:37:36 PM PDT 24
Peak memory 210980 kb
Host smart-ad591888-a997-4e2e-ae91-8ba4c7bad833
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341634346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1341634346
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.948224637
Short name T363
Test name
Test status
Simulation time 177249371 ps
CPU time 5.91 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:36:32 PM PDT 24
Peak memory 215372 kb
Host smart-5353771c-197c-4803-9fdf-60991a814726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948224637 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.948224637
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2912068378
Short name T366
Test name
Test status
Simulation time 1384978182 ps
CPU time 6.42 seconds
Started Jul 20 04:36:28 PM PDT 24
Finished Jul 20 04:36:36 PM PDT 24
Peak memory 210456 kb
Host smart-c4642981-dc3d-45ac-ad58-8107514b6d96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912068378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2912068378
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1428610955
Short name T87
Test name
Test status
Simulation time 62833515978 ps
CPU time 55.76 seconds
Started Jul 20 04:36:21 PM PDT 24
Finished Jul 20 04:37:18 PM PDT 24
Peak memory 210668 kb
Host smart-6219d0d6-14fb-4a31-9089-6c53c9c643bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428610955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1428610955
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2692391798
Short name T394
Test name
Test status
Simulation time 976835051 ps
CPU time 9.46 seconds
Started Jul 20 04:36:24 PM PDT 24
Finished Jul 20 04:36:35 PM PDT 24
Peak memory 218624 kb
Host smart-6576fb78-84a1-47f8-b51d-2db41237606e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692391798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2692391798
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.461189523
Short name T395
Test name
Test status
Simulation time 4258997978 ps
CPU time 13.11 seconds
Started Jul 20 04:36:24 PM PDT 24
Finished Jul 20 04:36:39 PM PDT 24
Peak memory 218724 kb
Host smart-33d675fc-7da2-4236-8a5c-016265c76510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461189523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.461189523
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2503362110
Short name T98
Test name
Test status
Simulation time 221376350 ps
CPU time 68.92 seconds
Started Jul 20 04:36:17 PM PDT 24
Finished Jul 20 04:37:27 PM PDT 24
Peak memory 211192 kb
Host smart-15b2b876-22fb-487f-aefa-390af80829ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503362110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2503362110
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1123147859
Short name T367
Test name
Test status
Simulation time 1771284821 ps
CPU time 7.74 seconds
Started Jul 20 04:36:24 PM PDT 24
Finished Jul 20 04:36:33 PM PDT 24
Peak memory 218756 kb
Host smart-f61155f0-8612-42e9-aaa3-3afd2f1c11f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123147859 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1123147859
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3261628022
Short name T443
Test name
Test status
Simulation time 346583404 ps
CPU time 4.13 seconds
Started Jul 20 04:36:23 PM PDT 24
Finished Jul 20 04:36:28 PM PDT 24
Peak memory 210468 kb
Host smart-0df71e2d-978d-41a9-9f33-b4f9b863a3ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261628022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3261628022
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.230402964
Short name T426
Test name
Test status
Simulation time 4111775404 ps
CPU time 50.45 seconds
Started Jul 20 04:36:24 PM PDT 24
Finished Jul 20 04:37:15 PM PDT 24
Peak memory 210548 kb
Host smart-bd0668cb-1680-494f-bbec-0b64c04c3d43
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230402964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.230402964
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.897860111
Short name T412
Test name
Test status
Simulation time 6395638999 ps
CPU time 15.36 seconds
Started Jul 20 04:36:20 PM PDT 24
Finished Jul 20 04:36:37 PM PDT 24
Peak memory 218804 kb
Host smart-d70f90a5-c43a-46ac-8fff-34c7ec2b00b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897860111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.897860111
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2428402252
Short name T379
Test name
Test status
Simulation time 255142045 ps
CPU time 8.29 seconds
Started Jul 20 04:36:24 PM PDT 24
Finished Jul 20 04:36:34 PM PDT 24
Peak memory 218692 kb
Host smart-788f4e01-0dbf-4443-bf91-3a105eeb52d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428402252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2428402252
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4109726907
Short name T56
Test name
Test status
Simulation time 2917444893 ps
CPU time 42.22 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:37:09 PM PDT 24
Peak memory 211716 kb
Host smart-c932607f-4965-43cc-a9a5-ce62c015c367
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109726907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4109726907
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1971038609
Short name T374
Test name
Test status
Simulation time 186924422 ps
CPU time 6 seconds
Started Jul 20 04:36:24 PM PDT 24
Finished Jul 20 04:36:31 PM PDT 24
Peak memory 218732 kb
Host smart-4d6e079e-3219-440b-87a5-32f7d15f580d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971038609 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1971038609
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.59521316
Short name T383
Test name
Test status
Simulation time 288133864 ps
CPU time 6.24 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:36:32 PM PDT 24
Peak memory 210448 kb
Host smart-63aca903-aebb-45ad-8e12-2e6353f9c98a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59521316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.59521316
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4123939294
Short name T95
Test name
Test status
Simulation time 21848946772 ps
CPU time 61.25 seconds
Started Jul 20 04:36:23 PM PDT 24
Finished Jul 20 04:37:25 PM PDT 24
Peak memory 210628 kb
Host smart-b892775b-2981-482c-af7d-fea3b6f40692
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123939294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.4123939294
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3977453473
Short name T460
Test name
Test status
Simulation time 6527971780 ps
CPU time 8.35 seconds
Started Jul 20 04:36:24 PM PDT 24
Finished Jul 20 04:36:33 PM PDT 24
Peak memory 218284 kb
Host smart-736276f4-5768-44c4-b6b2-0bb4e87370d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977453473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3977453473
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1568516923
Short name T424
Test name
Test status
Simulation time 7581566527 ps
CPU time 19.16 seconds
Started Jul 20 04:36:24 PM PDT 24
Finished Jul 20 04:36:44 PM PDT 24
Peak memory 218772 kb
Host smart-dddfd21d-b069-4328-b495-61b60c46ccbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568516923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1568516923
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.663034691
Short name T55
Test name
Test status
Simulation time 1095587286 ps
CPU time 38.93 seconds
Started Jul 20 04:36:25 PM PDT 24
Finished Jul 20 04:37:05 PM PDT 24
Peak memory 210552 kb
Host smart-d0974b37-cf5e-4ac3-8279-c86acc665da0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663034691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_int
g_err.663034691
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1427634378
Short name T1
Test name
Test status
Simulation time 1594831665 ps
CPU time 6.44 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:55:42 PM PDT 24
Peak memory 211292 kb
Host smart-a77ee630-6974-4959-b967-4bb43652ab04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427634378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1427634378
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.227218909
Short name T151
Test name
Test status
Simulation time 13401910399 ps
CPU time 30.08 seconds
Started Jul 20 04:55:36 PM PDT 24
Finished Jul 20 04:56:07 PM PDT 24
Peak memory 212496 kb
Host smart-4fd8f076-84e3-41ef-9b95-c442e29bc4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227218909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.227218909
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3222207461
Short name T20
Test name
Test status
Simulation time 953048682 ps
CPU time 57.69 seconds
Started Jul 20 04:55:33 PM PDT 24
Finished Jul 20 04:56:32 PM PDT 24
Peak memory 236096 kb
Host smart-a36a9315-8fee-4049-b190-e09bb0272862
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222207461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3222207461
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4144976720
Short name T115
Test name
Test status
Simulation time 9189366105 ps
CPU time 26.63 seconds
Started Jul 20 04:55:35 PM PDT 24
Finished Jul 20 04:56:03 PM PDT 24
Peak memory 214364 kb
Host smart-90a768cc-6223-44ca-aded-8f1e5b4e25bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144976720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4144976720
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2730015353
Short name T113
Test name
Test status
Simulation time 3068398750 ps
CPU time 26.6 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:56:02 PM PDT 24
Peak memory 215248 kb
Host smart-e695111a-0b58-4e2d-ba5e-2d740ac1e8ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730015353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2730015353
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3281433612
Short name T61
Test name
Test status
Simulation time 8499195555 ps
CPU time 16.69 seconds
Started Jul 20 04:55:36 PM PDT 24
Finished Jul 20 04:55:53 PM PDT 24
Peak memory 211416 kb
Host smart-a2a292ff-f155-49c8-9c66-e9c180737066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281433612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3281433612
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4200999997
Short name T284
Test name
Test status
Simulation time 83318570573 ps
CPU time 227.25 seconds
Started Jul 20 04:55:35 PM PDT 24
Finished Jul 20 04:59:23 PM PDT 24
Peak memory 228248 kb
Host smart-e5dd738e-bfce-4f75-8972-b09a96ee805c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200999997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4200999997
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2928641818
Short name T172
Test name
Test status
Simulation time 9213595838 ps
CPU time 27.07 seconds
Started Jul 20 04:55:35 PM PDT 24
Finished Jul 20 04:56:03 PM PDT 24
Peak memory 212244 kb
Host smart-7a9b1920-435c-47c4-b19b-5c3c148ef4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928641818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2928641818
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2070532779
Short name T239
Test name
Test status
Simulation time 4330646183 ps
CPU time 17.22 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:55:52 PM PDT 24
Peak memory 211440 kb
Host smart-7c96161c-d88c-4549-a1d7-a7a81a3c6ba0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070532779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2070532779
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3069642512
Short name T25
Test name
Test status
Simulation time 8559363563 ps
CPU time 60.49 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:56:35 PM PDT 24
Peak memory 236900 kb
Host smart-b3162318-81be-454b-9296-6d1a3e5ebc68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069642512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3069642512
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.181384994
Short name T125
Test name
Test status
Simulation time 11479199302 ps
CPU time 28.49 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 04:56:04 PM PDT 24
Peak memory 214396 kb
Host smart-ac35229c-b1e9-47c0-a6b0-7332b66eca48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181384994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.181384994
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.284795055
Short name T80
Test name
Test status
Simulation time 11512844286 ps
CPU time 38.01 seconds
Started Jul 20 04:55:36 PM PDT 24
Finished Jul 20 04:56:15 PM PDT 24
Peak memory 214048 kb
Host smart-0636c408-8eb7-44f1-a360-39a9f41f9020
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284795055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.284795055
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1833602334
Short name T54
Test name
Test status
Simulation time 44912887583 ps
CPU time 1651.54 seconds
Started Jul 20 04:55:34 PM PDT 24
Finished Jul 20 05:23:07 PM PDT 24
Peak memory 230900 kb
Host smart-11c977e2-b2ee-4510-8903-a1babb63d0b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833602334 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1833602334
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2660886743
Short name T263
Test name
Test status
Simulation time 15438512044 ps
CPU time 15.21 seconds
Started Jul 20 04:56:07 PM PDT 24
Finished Jul 20 04:56:23 PM PDT 24
Peak memory 211332 kb
Host smart-5dfd4660-046c-41ea-8463-207b9e82130f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660886743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2660886743
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2825056261
Short name T150
Test name
Test status
Simulation time 3471045170 ps
CPU time 98.31 seconds
Started Jul 20 04:56:08 PM PDT 24
Finished Jul 20 04:57:47 PM PDT 24
Peak memory 232760 kb
Host smart-e401bb2c-36d9-45cb-9234-8be5daaa638b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825056261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2825056261
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3620095106
Short name T326
Test name
Test status
Simulation time 26225306304 ps
CPU time 17.77 seconds
Started Jul 20 04:56:09 PM PDT 24
Finished Jul 20 04:56:27 PM PDT 24
Peak memory 212416 kb
Host smart-9addd845-6211-48cd-8d9c-140c4fadde38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620095106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3620095106
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2343299182
Short name T338
Test name
Test status
Simulation time 1410244079 ps
CPU time 7.64 seconds
Started Jul 20 04:55:58 PM PDT 24
Finished Jul 20 04:56:06 PM PDT 24
Peak memory 211404 kb
Host smart-4c85a473-484f-43ba-b4c9-dbe3429826e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2343299182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2343299182
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.121243493
Short name T299
Test name
Test status
Simulation time 184494895 ps
CPU time 10.19 seconds
Started Jul 20 04:55:58 PM PDT 24
Finished Jul 20 04:56:10 PM PDT 24
Peak memory 213056 kb
Host smart-568613b5-7e00-4d18-b097-2619cc242dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121243493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.121243493
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1192613546
Short name T312
Test name
Test status
Simulation time 4387469358 ps
CPU time 37.85 seconds
Started Jul 20 04:55:59 PM PDT 24
Finished Jul 20 04:56:38 PM PDT 24
Peak memory 214292 kb
Host smart-00f56e80-62ca-4ec7-be0f-dbc711a20c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192613546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1192613546
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.692986047
Short name T267
Test name
Test status
Simulation time 1659143083 ps
CPU time 14.04 seconds
Started Jul 20 04:56:06 PM PDT 24
Finished Jul 20 04:56:21 PM PDT 24
Peak memory 211356 kb
Host smart-0e8c8187-f84f-4401-87cf-204c02836475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692986047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.692986047
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4042430995
Short name T271
Test name
Test status
Simulation time 66664395618 ps
CPU time 238.18 seconds
Started Jul 20 04:56:05 PM PDT 24
Finished Jul 20 05:00:04 PM PDT 24
Peak memory 237820 kb
Host smart-bef4ceee-b9a6-4799-ab37-c00365a9e63d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042430995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4042430995
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1021912824
Short name T128
Test name
Test status
Simulation time 2980929708 ps
CPU time 15.28 seconds
Started Jul 20 04:56:06 PM PDT 24
Finished Jul 20 04:56:22 PM PDT 24
Peak memory 212100 kb
Host smart-1d554a75-47fb-4175-ab62-b5415756c8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021912824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1021912824
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1395871221
Short name T146
Test name
Test status
Simulation time 1496777609 ps
CPU time 13.58 seconds
Started Jul 20 04:56:05 PM PDT 24
Finished Jul 20 04:56:20 PM PDT 24
Peak memory 211260 kb
Host smart-b043d61d-76c5-46bb-af64-645c493dce0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395871221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1395871221
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.28157481
Short name T244
Test name
Test status
Simulation time 15154565462 ps
CPU time 31.38 seconds
Started Jul 20 04:56:07 PM PDT 24
Finished Jul 20 04:56:39 PM PDT 24
Peak memory 213676 kb
Host smart-862d930c-f065-4ec8-a68f-1d81eb01ec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28157481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.28157481
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.941066964
Short name T264
Test name
Test status
Simulation time 32052913899 ps
CPU time 76.31 seconds
Started Jul 20 04:56:09 PM PDT 24
Finished Jul 20 04:57:26 PM PDT 24
Peak memory 218404 kb
Host smart-0e51451f-e915-4228-af29-4f512e724c1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941066964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.941066964
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3107617038
Short name T346
Test name
Test status
Simulation time 3576706941 ps
CPU time 15.01 seconds
Started Jul 20 04:56:05 PM PDT 24
Finished Jul 20 04:56:21 PM PDT 24
Peak memory 211464 kb
Host smart-240ccb58-7faf-49a3-9da8-607e9df90d52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107617038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3107617038
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3904544322
Short name T41
Test name
Test status
Simulation time 39759939149 ps
CPU time 195.35 seconds
Started Jul 20 04:56:07 PM PDT 24
Finished Jul 20 04:59:23 PM PDT 24
Peak memory 233680 kb
Host smart-7c09bc6b-0a8b-41b8-a367-f31d41e77b63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904544322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3904544322
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.634328753
Short name T31
Test name
Test status
Simulation time 7934369818 ps
CPU time 22.91 seconds
Started Jul 20 04:56:04 PM PDT 24
Finished Jul 20 04:56:28 PM PDT 24
Peak memory 212248 kb
Host smart-33807b5d-0c09-40cd-a117-230ee646d4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634328753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.634328753
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.701261583
Short name T29
Test name
Test status
Simulation time 3538414535 ps
CPU time 10.97 seconds
Started Jul 20 04:56:06 PM PDT 24
Finished Jul 20 04:56:17 PM PDT 24
Peak memory 211404 kb
Host smart-1cbf5b19-db2c-4af4-8748-d5ba8633c528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=701261583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.701261583
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1081671680
Short name T190
Test name
Test status
Simulation time 563639914 ps
CPU time 12.82 seconds
Started Jul 20 04:56:06 PM PDT 24
Finished Jul 20 04:56:20 PM PDT 24
Peak memory 212264 kb
Host smart-603ddbec-763e-48e7-aab2-7000e855d405
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081671680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1081671680
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.4140343465
Short name T64
Test name
Test status
Simulation time 12244585854 ps
CPU time 11.89 seconds
Started Jul 20 04:56:12 PM PDT 24
Finished Jul 20 04:56:24 PM PDT 24
Peak memory 211412 kb
Host smart-aafc25a8-ee57-4b3f-ab91-a501a7e53744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140343465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.4140343465
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2567414067
Short name T298
Test name
Test status
Simulation time 32982661467 ps
CPU time 181.07 seconds
Started Jul 20 04:56:12 PM PDT 24
Finished Jul 20 04:59:13 PM PDT 24
Peak memory 236948 kb
Host smart-dde24d5b-7e2f-4512-a0d7-a13137f26d0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567414067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2567414067
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.799269478
Short name T27
Test name
Test status
Simulation time 3405777842 ps
CPU time 28.12 seconds
Started Jul 20 04:56:13 PM PDT 24
Finished Jul 20 04:56:41 PM PDT 24
Peak memory 215824 kb
Host smart-df1e9e08-e849-44dd-bd1b-954fb2b32329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799269478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.799269478
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1355786431
Short name T96
Test name
Test status
Simulation time 3184177907 ps
CPU time 14.12 seconds
Started Jul 20 04:56:13 PM PDT 24
Finished Jul 20 04:56:27 PM PDT 24
Peak memory 211460 kb
Host smart-f8672011-3dab-4fde-a11f-84ceb8ab61ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1355786431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1355786431
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1365447295
Short name T203
Test name
Test status
Simulation time 14522467046 ps
CPU time 29.88 seconds
Started Jul 20 04:56:07 PM PDT 24
Finished Jul 20 04:56:37 PM PDT 24
Peak memory 213960 kb
Host smart-8ddc252e-0c1e-4e2c-b2e3-afc58659abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365447295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1365447295
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2847624845
Short name T212
Test name
Test status
Simulation time 7338118112 ps
CPU time 20.5 seconds
Started Jul 20 04:56:12 PM PDT 24
Finished Jul 20 04:56:33 PM PDT 24
Peak memory 211304 kb
Host smart-ee82cf25-e226-4c42-8fad-c12e9f669f3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847624845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2847624845
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1284325440
Short name T63
Test name
Test status
Simulation time 4105266704 ps
CPU time 10.47 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 04:56:40 PM PDT 24
Peak memory 211388 kb
Host smart-695db179-242d-46c6-9d05-86a0b3ec3c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284325440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1284325440
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.881948542
Short name T144
Test name
Test status
Simulation time 7213711583 ps
CPU time 97.57 seconds
Started Jul 20 04:56:22 PM PDT 24
Finished Jul 20 04:58:00 PM PDT 24
Peak memory 237952 kb
Host smart-5c52e964-1f94-4457-99a9-1fc58b465fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881948542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.881948542
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3081374791
Short name T262
Test name
Test status
Simulation time 2372157819 ps
CPU time 23.96 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 04:56:54 PM PDT 24
Peak memory 211856 kb
Host smart-77f7f18f-44b4-4a31-bad3-17e5d09325c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081374791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3081374791
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3056584251
Short name T226
Test name
Test status
Simulation time 94116551 ps
CPU time 5.43 seconds
Started Jul 20 04:56:14 PM PDT 24
Finished Jul 20 04:56:19 PM PDT 24
Peak memory 211384 kb
Host smart-d5da4d4e-f75e-42b6-8cb1-98d3d6ca2e81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3056584251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3056584251
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2693298609
Short name T192
Test name
Test status
Simulation time 7824425420 ps
CPU time 19.57 seconds
Started Jul 20 04:56:15 PM PDT 24
Finished Jul 20 04:56:35 PM PDT 24
Peak memory 213804 kb
Host smart-173ae32a-93ac-4d71-98a7-a90c352f5a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693298609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2693298609
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3017290359
Short name T337
Test name
Test status
Simulation time 137521109 ps
CPU time 9.23 seconds
Started Jul 20 04:56:15 PM PDT 24
Finished Jul 20 04:56:25 PM PDT 24
Peak memory 211216 kb
Host smart-9540203c-02f9-4e1f-88e7-4f8f51428498
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017290359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3017290359
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3949770035
Short name T286
Test name
Test status
Simulation time 640654224 ps
CPU time 8.12 seconds
Started Jul 20 04:56:23 PM PDT 24
Finished Jul 20 04:56:31 PM PDT 24
Peak memory 211292 kb
Host smart-c7e2080f-916e-4974-9355-a4b32cce4347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949770035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3949770035
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.942450175
Short name T215
Test name
Test status
Simulation time 30195227561 ps
CPU time 151.79 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 04:59:02 PM PDT 24
Peak memory 233756 kb
Host smart-e3237bf2-2afa-4496-97f8-03bac9392b97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942450175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_c
orrupt_sig_fatal_chk.942450175
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4192822371
Short name T247
Test name
Test status
Simulation time 10218214148 ps
CPU time 31.48 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 04:57:01 PM PDT 24
Peak memory 212228 kb
Host smart-a2859fc3-c544-4890-b9de-4a454e7dd0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192822371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4192822371
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1823776656
Short name T169
Test name
Test status
Simulation time 467018765 ps
CPU time 6.87 seconds
Started Jul 20 04:56:19 PM PDT 24
Finished Jul 20 04:56:27 PM PDT 24
Peak memory 211336 kb
Host smart-6aaf5c79-ba9f-4244-a55a-a0cc7caf9479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823776656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1823776656
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.4280991771
Short name T358
Test name
Test status
Simulation time 1077688083 ps
CPU time 18.25 seconds
Started Jul 20 04:56:19 PM PDT 24
Finished Jul 20 04:56:38 PM PDT 24
Peak memory 213688 kb
Host smart-ba218006-60cf-4bf9-96a8-e9dd12bb8360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280991771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.4280991771
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.4053140884
Short name T311
Test name
Test status
Simulation time 5982131334 ps
CPU time 20.92 seconds
Started Jul 20 04:56:22 PM PDT 24
Finished Jul 20 04:56:44 PM PDT 24
Peak memory 212916 kb
Host smart-aa53a759-9a2d-4d97-9bf2-ac80fccbb1f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053140884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.4053140884
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1702973675
Short name T181
Test name
Test status
Simulation time 6793648749 ps
CPU time 13.03 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 04:56:43 PM PDT 24
Peak memory 211416 kb
Host smart-963a473b-27fb-46dc-9955-13423bc31cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702973675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1702973675
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2635766577
Short name T256
Test name
Test status
Simulation time 19585692325 ps
CPU time 125.65 seconds
Started Jul 20 04:56:19 PM PDT 24
Finished Jul 20 04:58:26 PM PDT 24
Peak memory 228632 kb
Host smart-c123e13b-a689-40c1-856b-c20d5266d4ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635766577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2635766577
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3334360837
Short name T354
Test name
Test status
Simulation time 10670703027 ps
CPU time 25.77 seconds
Started Jul 20 04:56:17 PM PDT 24
Finished Jul 20 04:56:43 PM PDT 24
Peak memory 212336 kb
Host smart-d0d0872f-8706-45b7-9795-88358dd7a74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334360837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3334360837
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3445720454
Short name T176
Test name
Test status
Simulation time 4887110882 ps
CPU time 11.83 seconds
Started Jul 20 04:56:23 PM PDT 24
Finished Jul 20 04:56:35 PM PDT 24
Peak memory 211396 kb
Host smart-f7e7fc90-6f9e-4295-92d2-9e1c47187eb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445720454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3445720454
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.386781930
Short name T249
Test name
Test status
Simulation time 2797469742 ps
CPU time 25.26 seconds
Started Jul 20 04:56:20 PM PDT 24
Finished Jul 20 04:56:46 PM PDT 24
Peak memory 213100 kb
Host smart-2fdb3ed4-5fa0-40fc-8139-b8adc24001d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386781930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.386781930
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4248559214
Short name T246
Test name
Test status
Simulation time 5099775594 ps
CPU time 44.89 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 04:57:14 PM PDT 24
Peak memory 215140 kb
Host smart-d7994583-5b3b-4d78-b8ed-ef977fb8833c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248559214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4248559214
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2103568272
Short name T290
Test name
Test status
Simulation time 88093216 ps
CPU time 4.38 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 04:56:35 PM PDT 24
Peak memory 211292 kb
Host smart-d3ba2595-f178-4f41-a0a3-2d64c78363b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103568272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2103568272
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.355404026
Short name T219
Test name
Test status
Simulation time 13695399097 ps
CPU time 236.3 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 05:00:27 PM PDT 24
Peak memory 237820 kb
Host smart-4492a8e1-450c-4511-9624-fd3666aaf456
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355404026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.355404026
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1033047938
Short name T160
Test name
Test status
Simulation time 13039325014 ps
CPU time 29.31 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 04:56:59 PM PDT 24
Peak memory 212176 kb
Host smart-b5b9f66b-69a4-4d8a-846e-d067c44fd793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033047938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1033047938
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2291254458
Short name T360
Test name
Test status
Simulation time 1049022792 ps
CPU time 11.73 seconds
Started Jul 20 04:56:30 PM PDT 24
Finished Jul 20 04:56:42 PM PDT 24
Peak memory 211344 kb
Host smart-ba450628-2fa2-4336-87fc-503b20cac14a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291254458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2291254458
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2405076656
Short name T289
Test name
Test status
Simulation time 7922443923 ps
CPU time 22.19 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 04:56:52 PM PDT 24
Peak memory 214528 kb
Host smart-4830d059-4d4c-469d-8f92-4f02efcff712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405076656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2405076656
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.4005226608
Short name T217
Test name
Test status
Simulation time 8436670291 ps
CPU time 43.02 seconds
Started Jul 20 04:56:29 PM PDT 24
Finished Jul 20 04:57:12 PM PDT 24
Peak memory 213320 kb
Host smart-48926e78-2e4d-4718-a87f-f698e1032c96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005226608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.4005226608
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.233493438
Short name T52
Test name
Test status
Simulation time 9308646035 ps
CPU time 355.72 seconds
Started Jul 20 04:56:28 PM PDT 24
Finished Jul 20 05:02:25 PM PDT 24
Peak memory 232068 kb
Host smart-287eac7c-8fdc-4212-8788-bbad65e3e0ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233493438 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.233493438
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1596750598
Short name T330
Test name
Test status
Simulation time 1538294452 ps
CPU time 11.56 seconds
Started Jul 20 04:56:38 PM PDT 24
Finished Jul 20 04:56:50 PM PDT 24
Peak memory 211476 kb
Host smart-1ceb0cf3-9775-44c6-801d-62e9607830b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596750598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1596750598
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2287117311
Short name T118
Test name
Test status
Simulation time 115434258348 ps
CPU time 284.41 seconds
Started Jul 20 04:56:40 PM PDT 24
Finished Jul 20 05:01:25 PM PDT 24
Peak memory 237824 kb
Host smart-b3bb3ebf-a553-43ab-b0db-ca12095247da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287117311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2287117311
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3714818263
Short name T142
Test name
Test status
Simulation time 5144852278 ps
CPU time 10.42 seconds
Started Jul 20 04:56:37 PM PDT 24
Finished Jul 20 04:56:48 PM PDT 24
Peak memory 211476 kb
Host smart-3a32f8f1-4e1d-40d7-a353-80d8770ebfad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3714818263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3714818263
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.615147967
Short name T305
Test name
Test status
Simulation time 15153542598 ps
CPU time 34.65 seconds
Started Jul 20 04:56:28 PM PDT 24
Finished Jul 20 04:57:03 PM PDT 24
Peak memory 214308 kb
Host smart-1aaba687-de4f-425f-bdf4-ffe0a0739c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615147967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.615147967
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.473496995
Short name T328
Test name
Test status
Simulation time 1368470052 ps
CPU time 21.81 seconds
Started Jul 20 04:56:30 PM PDT 24
Finished Jul 20 04:56:53 PM PDT 24
Peak memory 211348 kb
Host smart-8e155eb2-0d4c-4397-85f5-c6142083e1bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473496995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.473496995
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2257573191
Short name T207
Test name
Test status
Simulation time 138162378 ps
CPU time 4.2 seconds
Started Jul 20 04:56:38 PM PDT 24
Finished Jul 20 04:56:43 PM PDT 24
Peak memory 211300 kb
Host smart-4f017b00-f2fc-4c80-b218-033f82c72e08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257573191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2257573191
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2602259577
Short name T36
Test name
Test status
Simulation time 142306726595 ps
CPU time 415.32 seconds
Started Jul 20 04:56:37 PM PDT 24
Finished Jul 20 05:03:33 PM PDT 24
Peak memory 228608 kb
Host smart-f4637971-e1c6-4e1f-88fe-f424f0aabe67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602259577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2602259577
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1309555823
Short name T329
Test name
Test status
Simulation time 1030376268 ps
CPU time 11.4 seconds
Started Jul 20 04:56:39 PM PDT 24
Finished Jul 20 04:56:51 PM PDT 24
Peak memory 211400 kb
Host smart-44e3581b-a03e-4064-98d5-703073f31562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309555823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1309555823
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1149253031
Short name T202
Test name
Test status
Simulation time 1597420953 ps
CPU time 19.53 seconds
Started Jul 20 04:56:37 PM PDT 24
Finished Jul 20 04:56:57 PM PDT 24
Peak memory 213452 kb
Host smart-971ee94d-19c2-4c42-a252-bdd2b5e0c303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149253031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1149253031
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2111797325
Short name T225
Test name
Test status
Simulation time 990552499 ps
CPU time 10.14 seconds
Started Jul 20 04:55:43 PM PDT 24
Finished Jul 20 04:55:54 PM PDT 24
Peak memory 211356 kb
Host smart-350be638-446e-4a26-aaac-acbffe4c4037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111797325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2111797325
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2924500742
Short name T241
Test name
Test status
Simulation time 9954503211 ps
CPU time 148.29 seconds
Started Jul 20 04:55:42 PM PDT 24
Finished Jul 20 04:58:12 PM PDT 24
Peak memory 238148 kb
Host smart-a822eea8-25b8-4cb3-bbea-774c74864613
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924500742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2924500742
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.914701393
Short name T3
Test name
Test status
Simulation time 2502787209 ps
CPU time 23.94 seconds
Started Jul 20 04:55:41 PM PDT 24
Finished Jul 20 04:56:06 PM PDT 24
Peak memory 212128 kb
Host smart-bb284aa0-dbbd-4835-815c-51150d71c70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914701393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.914701393
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2871211882
Short name T314
Test name
Test status
Simulation time 193557120 ps
CPU time 5.43 seconds
Started Jul 20 04:55:42 PM PDT 24
Finished Jul 20 04:55:48 PM PDT 24
Peak memory 211328 kb
Host smart-7033f75f-f838-41dc-b265-f0dcf0a446d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871211882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2871211882
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2233070615
Short name T78
Test name
Test status
Simulation time 7941605167 ps
CPU time 24 seconds
Started Jul 20 04:55:40 PM PDT 24
Finished Jul 20 04:56:05 PM PDT 24
Peak memory 213580 kb
Host smart-3c867733-ff9e-4014-952f-5f6fe986cff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233070615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2233070615
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3028718264
Short name T339
Test name
Test status
Simulation time 6650852138 ps
CPU time 69.93 seconds
Started Jul 20 04:55:42 PM PDT 24
Finished Jul 20 04:56:53 PM PDT 24
Peak memory 215272 kb
Host smart-c2c2cf8e-aaaf-4055-9c46-b985a20394b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028718264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3028718264
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.4024719055
Short name T177
Test name
Test status
Simulation time 1911388083 ps
CPU time 15.31 seconds
Started Jul 20 04:56:44 PM PDT 24
Finished Jul 20 04:57:00 PM PDT 24
Peak memory 211304 kb
Host smart-f69bee15-069f-44b0-9a37-cbd49ba3e3c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024719055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.4024719055
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3082710673
Short name T293
Test name
Test status
Simulation time 67504697705 ps
CPU time 355.77 seconds
Started Jul 20 04:56:40 PM PDT 24
Finished Jul 20 05:02:36 PM PDT 24
Peak memory 225412 kb
Host smart-d3004b1e-d341-463c-a163-04476e92c14d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082710673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3082710673
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.207937571
Short name T349
Test name
Test status
Simulation time 172376556 ps
CPU time 9.44 seconds
Started Jul 20 04:56:48 PM PDT 24
Finished Jul 20 04:56:57 PM PDT 24
Peak memory 211972 kb
Host smart-3fed18b9-ada9-4acb-80b5-ec14a4dc711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207937571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.207937571
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4210062068
Short name T166
Test name
Test status
Simulation time 5002960011 ps
CPU time 13.17 seconds
Started Jul 20 04:56:48 PM PDT 24
Finished Jul 20 04:57:02 PM PDT 24
Peak memory 211472 kb
Host smart-6bb3c5dd-b893-4b4b-951c-1c1748fb7c50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4210062068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4210062068
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1536657179
Short name T265
Test name
Test status
Simulation time 6559402776 ps
CPU time 23.29 seconds
Started Jul 20 04:56:39 PM PDT 24
Finished Jul 20 04:57:02 PM PDT 24
Peak memory 214388 kb
Host smart-01ca8987-4d2d-47b2-a7bc-116498e1f84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536657179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1536657179
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3565008372
Short name T5
Test name
Test status
Simulation time 377298976 ps
CPU time 20.68 seconds
Started Jul 20 04:56:37 PM PDT 24
Finished Jul 20 04:56:59 PM PDT 24
Peak memory 215148 kb
Host smart-07f46312-268a-4cc2-9c30-28b24bdc21ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565008372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3565008372
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3053630746
Short name T50
Test name
Test status
Simulation time 30483340355 ps
CPU time 1094.75 seconds
Started Jul 20 04:56:48 PM PDT 24
Finished Jul 20 05:15:03 PM PDT 24
Peak memory 235888 kb
Host smart-54debf3a-1491-45b0-b1d7-ce8c6e3a4d49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053630746 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3053630746
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.4018613801
Short name T270
Test name
Test status
Simulation time 598610232 ps
CPU time 7.85 seconds
Started Jul 20 04:56:46 PM PDT 24
Finished Jul 20 04:56:54 PM PDT 24
Peak memory 211340 kb
Host smart-603f1835-f670-4edd-add5-b2b85d6dd50b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018613801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.4018613801
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.820423775
Short name T133
Test name
Test status
Simulation time 9896859031 ps
CPU time 120.98 seconds
Started Jul 20 04:56:44 PM PDT 24
Finished Jul 20 04:58:46 PM PDT 24
Peak memory 237412 kb
Host smart-2391538c-be26-4b25-9e27-423c8d73a436
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820423775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.820423775
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.3469724442
Short name T47
Test name
Test status
Simulation time 26343857190 ps
CPU time 18.4 seconds
Started Jul 20 04:56:44 PM PDT 24
Finished Jul 20 04:57:02 PM PDT 24
Peak memory 215212 kb
Host smart-90e2f0cf-2682-4f1f-8648-c124811da2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469724442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.3469724442
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.201605512
Short name T230
Test name
Test status
Simulation time 8414810228 ps
CPU time 15.89 seconds
Started Jul 20 04:56:44 PM PDT 24
Finished Jul 20 04:57:00 PM PDT 24
Peak memory 211392 kb
Host smart-1592208d-f6e5-49ee-b32c-e03921135b95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201605512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.201605512
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1806190294
Short name T6
Test name
Test status
Simulation time 353679453 ps
CPU time 9.73 seconds
Started Jul 20 04:56:44 PM PDT 24
Finished Jul 20 04:56:54 PM PDT 24
Peak memory 213852 kb
Host smart-04b0086c-9e9d-4f3d-ad78-e5f434acffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806190294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1806190294
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3233556672
Short name T16
Test name
Test status
Simulation time 10151431170 ps
CPU time 39.5 seconds
Started Jul 20 04:56:46 PM PDT 24
Finished Jul 20 04:57:26 PM PDT 24
Peak memory 217132 kb
Host smart-52099ceb-ddc9-4dfc-8331-d36dd032abe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233556672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3233556672
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3761103652
Short name T218
Test name
Test status
Simulation time 3214233657 ps
CPU time 9.17 seconds
Started Jul 20 04:56:46 PM PDT 24
Finished Jul 20 04:56:56 PM PDT 24
Peak memory 211416 kb
Host smart-be72f196-cd97-4a1e-82aa-db1ba34f49c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761103652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3761103652
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.900233315
Short name T182
Test name
Test status
Simulation time 20042356642 ps
CPU time 112.3 seconds
Started Jul 20 04:56:44 PM PDT 24
Finished Jul 20 04:58:37 PM PDT 24
Peak memory 237832 kb
Host smart-8e4c1e87-533d-447c-95e4-7f4a25ee5409
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900233315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.900233315
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2342234062
Short name T344
Test name
Test status
Simulation time 1319267210 ps
CPU time 18.74 seconds
Started Jul 20 04:56:48 PM PDT 24
Finished Jul 20 04:57:08 PM PDT 24
Peak memory 211832 kb
Host smart-081a6c41-cd80-42a3-b060-83142e75607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342234062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2342234062
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3046470434
Short name T283
Test name
Test status
Simulation time 473829730 ps
CPU time 8.02 seconds
Started Jul 20 04:56:48 PM PDT 24
Finished Jul 20 04:56:57 PM PDT 24
Peak memory 211384 kb
Host smart-61e7e653-5c85-4af4-89f4-85a63922fbe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3046470434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3046470434
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2868989727
Short name T287
Test name
Test status
Simulation time 7925645484 ps
CPU time 26.91 seconds
Started Jul 20 04:56:46 PM PDT 24
Finished Jul 20 04:57:14 PM PDT 24
Peak memory 214204 kb
Host smart-5291e0bf-34fd-4066-a20e-fb90a4276d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868989727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2868989727
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2170433871
Short name T195
Test name
Test status
Simulation time 785689079 ps
CPU time 22.38 seconds
Started Jul 20 04:56:43 PM PDT 24
Finished Jul 20 04:57:06 PM PDT 24
Peak memory 215612 kb
Host smart-14a9eb5b-0dbd-4d02-82a1-8380fb151c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170433871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2170433871
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4026162726
Short name T53
Test name
Test status
Simulation time 123700029467 ps
CPU time 4752.91 seconds
Started Jul 20 04:56:44 PM PDT 24
Finished Jul 20 06:15:57 PM PDT 24
Peak memory 235796 kb
Host smart-0bc25f6d-f512-4cec-8119-167215c7f307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026162726 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.4026162726
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2497119472
Short name T134
Test name
Test status
Simulation time 9094456101 ps
CPU time 14.63 seconds
Started Jul 20 04:56:51 PM PDT 24
Finished Jul 20 04:57:07 PM PDT 24
Peak memory 211400 kb
Host smart-b52543bd-2808-4ba6-bc1f-60ebd77f3006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497119472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2497119472
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3835763426
Short name T165
Test name
Test status
Simulation time 1815701184 ps
CPU time 100.82 seconds
Started Jul 20 04:56:44 PM PDT 24
Finished Jul 20 04:58:26 PM PDT 24
Peak memory 228548 kb
Host smart-517a71b8-e102-453c-a047-e7a9b0d13cd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835763426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3835763426
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1035400425
Short name T131
Test name
Test status
Simulation time 387363865 ps
CPU time 9.59 seconds
Started Jul 20 04:56:46 PM PDT 24
Finished Jul 20 04:56:56 PM PDT 24
Peak memory 211980 kb
Host smart-fbdc5969-cf58-4072-bda2-1c4d8df8f975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035400425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1035400425
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.311220213
Short name T342
Test name
Test status
Simulation time 1180656105 ps
CPU time 7.22 seconds
Started Jul 20 04:56:46 PM PDT 24
Finished Jul 20 04:56:53 PM PDT 24
Peak memory 211404 kb
Host smart-dd3c4b52-de8d-497b-a2bb-59c6c7896bea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311220213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.311220213
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1305752811
Short name T333
Test name
Test status
Simulation time 3848365611 ps
CPU time 31.32 seconds
Started Jul 20 04:56:44 PM PDT 24
Finished Jul 20 04:57:15 PM PDT 24
Peak memory 213340 kb
Host smart-07fd325d-d88b-4321-93dc-73e41f6c89fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305752811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1305752811
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2459546777
Short name T200
Test name
Test status
Simulation time 2734389787 ps
CPU time 29.96 seconds
Started Jul 20 04:56:43 PM PDT 24
Finished Jul 20 04:57:13 PM PDT 24
Peak memory 216448 kb
Host smart-dd1edc5d-ac27-4952-be76-dce8db928212
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459546777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2459546777
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2211953525
Short name T62
Test name
Test status
Simulation time 715579251 ps
CPU time 8.83 seconds
Started Jul 20 04:56:50 PM PDT 24
Finished Jul 20 04:56:59 PM PDT 24
Peak memory 211508 kb
Host smart-38c1f331-df22-4843-84a2-699ad66d4f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211953525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2211953525
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4283328068
Short name T18
Test name
Test status
Simulation time 10269155201 ps
CPU time 54.03 seconds
Started Jul 20 04:56:52 PM PDT 24
Finished Jul 20 04:57:46 PM PDT 24
Peak memory 212656 kb
Host smart-1c33818a-b376-4447-b5f5-c6b33ea0a42a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283328068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4283328068
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2294989593
Short name T257
Test name
Test status
Simulation time 13576334317 ps
CPU time 33.52 seconds
Started Jul 20 04:56:51 PM PDT 24
Finished Jul 20 04:57:25 PM PDT 24
Peak memory 212188 kb
Host smart-2808b19e-f0ed-47ca-919e-66f4b8c2e724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294989593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2294989593
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1988657223
Short name T129
Test name
Test status
Simulation time 8263587325 ps
CPU time 15.67 seconds
Started Jul 20 04:56:50 PM PDT 24
Finished Jul 20 04:57:06 PM PDT 24
Peak memory 211304 kb
Host smart-8d8a7441-a7f5-42aa-8146-7ad5f5c5fd9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988657223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1988657223
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3201181998
Short name T153
Test name
Test status
Simulation time 11583654535 ps
CPU time 16.75 seconds
Started Jul 20 04:56:50 PM PDT 24
Finished Jul 20 04:57:07 PM PDT 24
Peak memory 214180 kb
Host smart-a3cf6018-12a6-4804-b2a4-f473ee7575a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201181998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3201181998
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.412089163
Short name T76
Test name
Test status
Simulation time 1300269327 ps
CPU time 22.2 seconds
Started Jul 20 04:56:51 PM PDT 24
Finished Jul 20 04:57:13 PM PDT 24
Peak memory 213440 kb
Host smart-f64e3647-e7e3-49ea-bc87-e76deb32f29d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412089163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.412089163
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.40437860
Short name T147
Test name
Test status
Simulation time 1798020808 ps
CPU time 9.68 seconds
Started Jul 20 04:56:59 PM PDT 24
Finished Jul 20 04:57:09 PM PDT 24
Peak memory 211292 kb
Host smart-52222d58-e8fb-4852-be8e-60c017f01511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40437860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.40437860
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3439818750
Short name T303
Test name
Test status
Simulation time 138463104203 ps
CPU time 239.14 seconds
Started Jul 20 04:56:51 PM PDT 24
Finished Jul 20 05:00:51 PM PDT 24
Peak memory 228592 kb
Host smart-f0ed5644-c002-4899-86ab-1dea3d21ca9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439818750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3439818750
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1190228996
Short name T161
Test name
Test status
Simulation time 4761747895 ps
CPU time 24.42 seconds
Started Jul 20 04:56:58 PM PDT 24
Finished Jul 20 04:57:23 PM PDT 24
Peak memory 212332 kb
Host smart-02dc9f4b-c96a-4edd-a524-d48147377764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190228996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1190228996
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1087850056
Short name T143
Test name
Test status
Simulation time 1665164505 ps
CPU time 8.41 seconds
Started Jul 20 04:56:51 PM PDT 24
Finished Jul 20 04:57:00 PM PDT 24
Peak memory 211412 kb
Host smart-a8ed4a56-83b5-4f35-bbea-7726fe4ae880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087850056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1087850056
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3291610141
Short name T319
Test name
Test status
Simulation time 245540923 ps
CPU time 10.07 seconds
Started Jul 20 04:56:50 PM PDT 24
Finished Jul 20 04:57:01 PM PDT 24
Peak memory 212284 kb
Host smart-69cae665-6429-4e01-869c-00249deb5f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291610141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3291610141
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.894273451
Short name T136
Test name
Test status
Simulation time 1748502224 ps
CPU time 26.17 seconds
Started Jul 20 04:56:50 PM PDT 24
Finished Jul 20 04:57:17 PM PDT 24
Peak memory 214508 kb
Host smart-b91489cb-85a0-4c74-a1ee-692fceebf7ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894273451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.894273451
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.229450518
Short name T157
Test name
Test status
Simulation time 576423101 ps
CPU time 7.85 seconds
Started Jul 20 04:56:59 PM PDT 24
Finished Jul 20 04:57:07 PM PDT 24
Peak memory 211316 kb
Host smart-b390dff3-7b76-40da-8ccb-767e1d8077b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229450518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.229450518
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2991700349
Short name T187
Test name
Test status
Simulation time 60486186140 ps
CPU time 195.43 seconds
Started Jul 20 04:56:59 PM PDT 24
Finished Jul 20 05:00:15 PM PDT 24
Peak memory 233736 kb
Host smart-17c73eb4-1136-4ba6-942f-bad678fd3561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991700349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2991700349
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.67480168
Short name T30
Test name
Test status
Simulation time 3830058795 ps
CPU time 30.13 seconds
Started Jul 20 04:56:58 PM PDT 24
Finished Jul 20 04:57:29 PM PDT 24
Peak memory 212140 kb
Host smart-e0e5c308-9430-430b-b52a-7b9e8f8e7db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67480168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.67480168
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.830517937
Short name T132
Test name
Test status
Simulation time 386697475 ps
CPU time 5.6 seconds
Started Jul 20 04:56:57 PM PDT 24
Finished Jul 20 04:57:03 PM PDT 24
Peak memory 211528 kb
Host smart-ff90a906-7ede-4d42-945e-d27e4d183e84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830517937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.830517937
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1550483139
Short name T191
Test name
Test status
Simulation time 16989451593 ps
CPU time 33.88 seconds
Started Jul 20 04:56:59 PM PDT 24
Finished Jul 20 04:57:34 PM PDT 24
Peak memory 214064 kb
Host smart-fc9c1287-06d1-4901-b807-03aedc34f0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550483139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1550483139
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4115331933
Short name T188
Test name
Test status
Simulation time 58289656750 ps
CPU time 31.85 seconds
Started Jul 20 04:57:03 PM PDT 24
Finished Jul 20 04:57:35 PM PDT 24
Peak memory 213484 kb
Host smart-a0962304-4b63-4ff3-97e2-968f0de33b2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115331933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4115331933
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4163824357
Short name T309
Test name
Test status
Simulation time 171122595 ps
CPU time 4.29 seconds
Started Jul 20 04:57:00 PM PDT 24
Finished Jul 20 04:57:05 PM PDT 24
Peak memory 211224 kb
Host smart-fc6d35dc-668d-4894-8a81-77c440dfcf91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163824357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4163824357
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2164371337
Short name T352
Test name
Test status
Simulation time 4131387510 ps
CPU time 31.75 seconds
Started Jul 20 04:56:58 PM PDT 24
Finished Jul 20 04:57:30 PM PDT 24
Peak memory 211880 kb
Host smart-3d8aeabe-ac4d-4032-a6f9-c65453807761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164371337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2164371337
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3481163404
Short name T124
Test name
Test status
Simulation time 1908625646 ps
CPU time 11 seconds
Started Jul 20 04:56:58 PM PDT 24
Finished Jul 20 04:57:10 PM PDT 24
Peak memory 211400 kb
Host smart-1f91c4d9-f2b5-4e58-a34e-f1884579307c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3481163404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3481163404
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.275829453
Short name T302
Test name
Test status
Simulation time 61091198290 ps
CPU time 31.79 seconds
Started Jul 20 04:56:59 PM PDT 24
Finished Jul 20 04:57:31 PM PDT 24
Peak memory 213696 kb
Host smart-2ea3dcd4-7938-497b-a8a8-95179ff7ea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275829453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.275829453
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3746285002
Short name T120
Test name
Test status
Simulation time 13410704817 ps
CPU time 13.37 seconds
Started Jul 20 04:56:59 PM PDT 24
Finished Jul 20 04:57:13 PM PDT 24
Peak memory 212688 kb
Host smart-7d200b36-29bf-49e5-b4ee-de91d2802f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746285002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3746285002
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.893216541
Short name T322
Test name
Test status
Simulation time 115865233766 ps
CPU time 1221 seconds
Started Jul 20 04:57:04 PM PDT 24
Finished Jul 20 05:17:26 PM PDT 24
Peak memory 235800 kb
Host smart-97d55df5-845a-43a2-8e78-52b38dcb86ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893216541 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.893216541
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.983995509
Short name T222
Test name
Test status
Simulation time 3830719959 ps
CPU time 15.63 seconds
Started Jul 20 04:57:09 PM PDT 24
Finished Jul 20 04:57:25 PM PDT 24
Peak memory 211352 kb
Host smart-41618a6a-ba37-48cb-895f-9da012e88cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983995509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.983995509
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1331789562
Short name T40
Test name
Test status
Simulation time 143260233859 ps
CPU time 347.19 seconds
Started Jul 20 04:57:10 PM PDT 24
Finished Jul 20 05:02:58 PM PDT 24
Peak memory 234852 kb
Host smart-f96bb1c7-0c5d-4433-a960-c8e3c9942d04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331789562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.1331789562
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3785008033
Short name T46
Test name
Test status
Simulation time 3925909273 ps
CPU time 31.83 seconds
Started Jul 20 04:57:10 PM PDT 24
Finished Jul 20 04:57:43 PM PDT 24
Peak memory 211884 kb
Host smart-2f69984d-00ce-4d6c-b8a4-ada09397d23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785008033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3785008033
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1331521533
Short name T334
Test name
Test status
Simulation time 94931809 ps
CPU time 5.35 seconds
Started Jul 20 04:57:10 PM PDT 24
Finished Jul 20 04:57:16 PM PDT 24
Peak memory 211388 kb
Host smart-fa8cd1e6-8b7f-4f60-8add-10ea53943570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331521533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1331521533
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3860069716
Short name T77
Test name
Test status
Simulation time 742627743 ps
CPU time 10.25 seconds
Started Jul 20 04:57:09 PM PDT 24
Finished Jul 20 04:57:20 PM PDT 24
Peak memory 213516 kb
Host smart-520d0a52-450c-4e02-bd14-b4b9b7cca3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860069716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3860069716
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3191978017
Short name T224
Test name
Test status
Simulation time 1070497035 ps
CPU time 21.74 seconds
Started Jul 20 04:57:10 PM PDT 24
Finished Jul 20 04:57:32 PM PDT 24
Peak memory 215144 kb
Host smart-0cdf5cea-e2c8-430b-9e93-0a1a2cfb8d7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191978017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3191978017
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3550146927
Short name T51
Test name
Test status
Simulation time 103484673255 ps
CPU time 3347.28 seconds
Started Jul 20 04:57:09 PM PDT 24
Finished Jul 20 05:52:57 PM PDT 24
Peak memory 235844 kb
Host smart-f49a0786-d2b6-4231-8ebd-9c806d87eaf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550146927 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3550146927
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1883769226
Short name T288
Test name
Test status
Simulation time 332528124 ps
CPU time 4.36 seconds
Started Jul 20 04:57:09 PM PDT 24
Finished Jul 20 04:57:14 PM PDT 24
Peak memory 211368 kb
Host smart-33376bbe-a51a-4d1e-b4e6-d5c1a5b51c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883769226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1883769226
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.758526014
Short name T179
Test name
Test status
Simulation time 141801004424 ps
CPU time 339.62 seconds
Started Jul 20 04:57:09 PM PDT 24
Finished Jul 20 05:02:49 PM PDT 24
Peak memory 228636 kb
Host smart-f9c968cf-0317-40d6-aa8d-f58ed0e8693a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758526014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.758526014
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3580819181
Short name T24
Test name
Test status
Simulation time 3190711367 ps
CPU time 28.26 seconds
Started Jul 20 04:57:10 PM PDT 24
Finished Jul 20 04:57:39 PM PDT 24
Peak memory 212236 kb
Host smart-5e4e1f87-957f-4b04-aa12-02b214bd2f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580819181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3580819181
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3977188772
Short name T140
Test name
Test status
Simulation time 7875850198 ps
CPU time 16.49 seconds
Started Jul 20 04:57:08 PM PDT 24
Finished Jul 20 04:57:25 PM PDT 24
Peak memory 211460 kb
Host smart-79064993-656b-4885-8a28-f8fbed9eccff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977188772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3977188772
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1716260719
Short name T156
Test name
Test status
Simulation time 2791448427 ps
CPU time 26.26 seconds
Started Jul 20 04:57:09 PM PDT 24
Finished Jul 20 04:57:36 PM PDT 24
Peak memory 213168 kb
Host smart-b542eb56-a6aa-49e7-937b-98cb52610fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716260719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1716260719
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.2782642804
Short name T216
Test name
Test status
Simulation time 17006073189 ps
CPU time 38.68 seconds
Started Jul 20 04:57:11 PM PDT 24
Finished Jul 20 04:57:50 PM PDT 24
Peak memory 217212 kb
Host smart-5d571888-949c-4586-a55b-9a5855ee3073
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782642804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.2782642804
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3695353425
Short name T135
Test name
Test status
Simulation time 346576959 ps
CPU time 4.07 seconds
Started Jul 20 04:55:42 PM PDT 24
Finished Jul 20 04:55:47 PM PDT 24
Peak memory 211300 kb
Host smart-09505c2c-0693-41cf-9ef4-85406a1a08ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695353425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3695353425
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2603779976
Short name T180
Test name
Test status
Simulation time 45238620159 ps
CPU time 214.85 seconds
Started Jul 20 04:55:43 PM PDT 24
Finished Jul 20 04:59:19 PM PDT 24
Peak memory 225164 kb
Host smart-8aa22bbb-f4d2-4125-bb75-928d943a50c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603779976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2603779976
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2762128002
Short name T214
Test name
Test status
Simulation time 57858458888 ps
CPU time 33.28 seconds
Started Jul 20 04:55:41 PM PDT 24
Finished Jul 20 04:56:15 PM PDT 24
Peak memory 212168 kb
Host smart-521f6e10-ae1c-40fc-9768-a79188c97bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762128002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2762128002
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3784201400
Short name T335
Test name
Test status
Simulation time 7883995992 ps
CPU time 16.27 seconds
Started Jul 20 04:55:42 PM PDT 24
Finished Jul 20 04:55:59 PM PDT 24
Peak memory 211420 kb
Host smart-9b2b96e1-bc85-4ff3-888d-63305ed56d3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784201400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3784201400
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3546773521
Short name T26
Test name
Test status
Simulation time 6389708971 ps
CPU time 62.39 seconds
Started Jul 20 04:55:42 PM PDT 24
Finished Jul 20 04:56:45 PM PDT 24
Peak memory 236820 kb
Host smart-bc6f74dd-af6e-4107-90c8-286255589ad3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546773521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3546773521
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3082469686
Short name T8
Test name
Test status
Simulation time 176043350 ps
CPU time 9.69 seconds
Started Jul 20 04:55:43 PM PDT 24
Finished Jul 20 04:55:54 PM PDT 24
Peak memory 213660 kb
Host smart-a9c1b5ab-69fd-4426-b264-0aabf6d54ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082469686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3082469686
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1933760806
Short name T315
Test name
Test status
Simulation time 514910527 ps
CPU time 6.71 seconds
Started Jul 20 04:55:40 PM PDT 24
Finished Jul 20 04:55:48 PM PDT 24
Peak memory 211392 kb
Host smart-d62521bd-d600-4b8b-a60d-3b58771ef93e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933760806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1933760806
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2126307277
Short name T65
Test name
Test status
Simulation time 2390975070 ps
CPU time 8.11 seconds
Started Jul 20 04:57:16 PM PDT 24
Finished Jul 20 04:57:25 PM PDT 24
Peak memory 211440 kb
Host smart-f3a52d0d-3e2c-47b0-9dd1-5dbf895c62c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126307277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2126307277
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.955913021
Short name T253
Test name
Test status
Simulation time 40780260556 ps
CPU time 147.99 seconds
Started Jul 20 04:57:14 PM PDT 24
Finished Jul 20 04:59:42 PM PDT 24
Peak memory 237768 kb
Host smart-edad9335-3619-4a8b-82c9-f86c71a10400
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955913021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.955913021
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2557952417
Short name T44
Test name
Test status
Simulation time 14866681735 ps
CPU time 30.04 seconds
Started Jul 20 04:57:16 PM PDT 24
Finished Jul 20 04:57:47 PM PDT 24
Peak memory 212172 kb
Host smart-faf71d62-6e81-4951-9672-e4e176276746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557952417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2557952417
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1500087657
Short name T232
Test name
Test status
Simulation time 4654578170 ps
CPU time 12.02 seconds
Started Jul 20 04:57:15 PM PDT 24
Finished Jul 20 04:57:28 PM PDT 24
Peak memory 211448 kb
Host smart-b77bbd3b-3fe4-437b-8ef6-75dd284034cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500087657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1500087657
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.633592040
Short name T254
Test name
Test status
Simulation time 3857753921 ps
CPU time 30.81 seconds
Started Jul 20 04:57:09 PM PDT 24
Finished Jul 20 04:57:40 PM PDT 24
Peak memory 213416 kb
Host smart-c7281feb-b6fe-4c67-91c8-e2229b894b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633592040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.633592040
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3352219937
Short name T173
Test name
Test status
Simulation time 405345916 ps
CPU time 19.68 seconds
Started Jul 20 04:57:15 PM PDT 24
Finished Jul 20 04:57:35 PM PDT 24
Peak memory 213468 kb
Host smart-2c39f92b-6f0f-48e0-a87c-1308227c6d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352219937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3352219937
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3756632733
Short name T138
Test name
Test status
Simulation time 378904882 ps
CPU time 4.35 seconds
Started Jul 20 04:57:16 PM PDT 24
Finished Jul 20 04:57:21 PM PDT 24
Peak memory 211372 kb
Host smart-6ab36e73-1b1b-4626-a067-244f1a1026ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756632733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3756632733
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3943657320
Short name T193
Test name
Test status
Simulation time 53793410260 ps
CPU time 529.27 seconds
Started Jul 20 04:57:16 PM PDT 24
Finished Jul 20 05:06:06 PM PDT 24
Peak memory 234908 kb
Host smart-6649864e-59ed-4972-ae58-ae342717b04e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943657320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3943657320
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.465878239
Short name T168
Test name
Test status
Simulation time 2872173064 ps
CPU time 25.83 seconds
Started Jul 20 04:57:15 PM PDT 24
Finished Jul 20 04:57:42 PM PDT 24
Peak memory 212064 kb
Host smart-3e21afcf-d35e-49dc-b56f-97f6693129e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465878239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.465878239
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1128680021
Short name T301
Test name
Test status
Simulation time 360108056 ps
CPU time 7.68 seconds
Started Jul 20 04:57:14 PM PDT 24
Finished Jul 20 04:57:22 PM PDT 24
Peak memory 211400 kb
Host smart-48f1b2b2-7f6d-4fef-a141-41c63f73fcdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1128680021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1128680021
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3490268600
Short name T323
Test name
Test status
Simulation time 9560982254 ps
CPU time 15.02 seconds
Started Jul 20 04:57:16 PM PDT 24
Finished Jul 20 04:57:32 PM PDT 24
Peak memory 213400 kb
Host smart-87707e33-a7a3-4f4f-9943-5cae95b8f72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490268600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3490268600
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.983335445
Short name T336
Test name
Test status
Simulation time 30011548150 ps
CPU time 63.89 seconds
Started Jul 20 04:57:16 PM PDT 24
Finished Jul 20 04:58:20 PM PDT 24
Peak memory 219276 kb
Host smart-5bab0051-cf77-4d19-a6f4-94013d0edc1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983335445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.983335445
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.1819912472
Short name T353
Test name
Test status
Simulation time 1184085528 ps
CPU time 8.18 seconds
Started Jul 20 04:57:17 PM PDT 24
Finished Jul 20 04:57:25 PM PDT 24
Peak memory 211324 kb
Host smart-6e43ea00-d3b5-42bb-a464-8715db30e3c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819912472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.1819912472
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3605085989
Short name T121
Test name
Test status
Simulation time 15108695629 ps
CPU time 244.01 seconds
Started Jul 20 04:57:17 PM PDT 24
Finished Jul 20 05:01:22 PM PDT 24
Peak memory 237820 kb
Host smart-a41db238-8414-432a-bb0d-2b87f10a8293
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605085989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3605085989
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3014077566
Short name T359
Test name
Test status
Simulation time 593790708 ps
CPU time 9.58 seconds
Started Jul 20 04:57:14 PM PDT 24
Finished Jul 20 04:57:24 PM PDT 24
Peak memory 211952 kb
Host smart-ab08fa5a-af06-4a9a-b6c0-c172ae1e6a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014077566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3014077566
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3772471283
Short name T345
Test name
Test status
Simulation time 9506360170 ps
CPU time 16.78 seconds
Started Jul 20 04:57:16 PM PDT 24
Finished Jul 20 04:57:34 PM PDT 24
Peak memory 211472 kb
Host smart-38026d3f-d944-4fd1-91c9-7ee1122b795b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772471283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3772471283
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4220012310
Short name T79
Test name
Test status
Simulation time 221541983 ps
CPU time 10.31 seconds
Started Jul 20 04:57:15 PM PDT 24
Finished Jul 20 04:57:26 PM PDT 24
Peak memory 214020 kb
Host smart-138ab1e1-bdb3-491a-a44b-801f9a97d730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220012310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4220012310
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.777693200
Short name T167
Test name
Test status
Simulation time 6527014809 ps
CPU time 30.18 seconds
Started Jul 20 04:57:14 PM PDT 24
Finished Jul 20 04:57:44 PM PDT 24
Peak memory 214488 kb
Host smart-de50ffd5-8857-4ed4-bc91-029849ab7a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777693200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.777693200
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.858381694
Short name T308
Test name
Test status
Simulation time 518924155 ps
CPU time 4.17 seconds
Started Jul 20 04:57:23 PM PDT 24
Finished Jul 20 04:57:28 PM PDT 24
Peak memory 211368 kb
Host smart-a15392de-3ac2-4d3e-90f7-c3cf5dad810e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858381694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.858381694
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2753625683
Short name T117
Test name
Test status
Simulation time 24045402162 ps
CPU time 141.8 seconds
Started Jul 20 04:57:25 PM PDT 24
Finished Jul 20 04:59:48 PM PDT 24
Peak memory 237860 kb
Host smart-24f1afda-c802-4d35-a5d5-136ed53bfd45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753625683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2753625683
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3338296046
Short name T35
Test name
Test status
Simulation time 4277023010 ps
CPU time 34.56 seconds
Started Jul 20 04:57:23 PM PDT 24
Finished Jul 20 04:57:58 PM PDT 24
Peak memory 211908 kb
Host smart-4f52d129-5424-421d-b627-230906cd41bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338296046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3338296046
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3405262814
Short name T112
Test name
Test status
Simulation time 12291980496 ps
CPU time 17.75 seconds
Started Jul 20 04:57:24 PM PDT 24
Finished Jul 20 04:57:43 PM PDT 24
Peak memory 211460 kb
Host smart-417df616-af91-4a0f-a19d-6ddcf2e640da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3405262814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3405262814
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1987259205
Short name T255
Test name
Test status
Simulation time 1737298139 ps
CPU time 15.94 seconds
Started Jul 20 04:57:18 PM PDT 24
Finished Jul 20 04:57:34 PM PDT 24
Peak memory 214000 kb
Host smart-383b104d-b3c3-4683-b71c-9bda94098cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987259205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1987259205
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1665950610
Short name T148
Test name
Test status
Simulation time 874555453 ps
CPU time 25.18 seconds
Started Jul 20 04:57:16 PM PDT 24
Finished Jul 20 04:57:42 PM PDT 24
Peak memory 214956 kb
Host smart-a6ca6ea1-c25a-44ab-b281-b8676b48d4ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665950610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1665950610
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.285307002
Short name T204
Test name
Test status
Simulation time 9624616347 ps
CPU time 109.82 seconds
Started Jul 20 04:57:26 PM PDT 24
Finished Jul 20 04:59:17 PM PDT 24
Peak memory 232712 kb
Host smart-da269dd7-7e8e-401d-87c5-5188f907bc57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285307002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.285307002
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2536119182
Short name T213
Test name
Test status
Simulation time 2134969379 ps
CPU time 22.31 seconds
Started Jul 20 04:57:24 PM PDT 24
Finished Jul 20 04:57:47 PM PDT 24
Peak memory 212080 kb
Host smart-e246db1c-e7ce-4575-b126-5ebf33f683d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536119182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2536119182
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4099409108
Short name T280
Test name
Test status
Simulation time 3475723003 ps
CPU time 11.6 seconds
Started Jul 20 04:57:26 PM PDT 24
Finished Jul 20 04:57:38 PM PDT 24
Peak memory 211460 kb
Host smart-218a454e-5f08-4e0a-b4d6-95191b6420c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4099409108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4099409108
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1216660979
Short name T297
Test name
Test status
Simulation time 18138437744 ps
CPU time 29.25 seconds
Started Jul 20 04:57:26 PM PDT 24
Finished Jul 20 04:57:56 PM PDT 24
Peak memory 214232 kb
Host smart-35cae537-302b-4560-b92c-6cacad2235ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216660979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1216660979
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2737693859
Short name T201
Test name
Test status
Simulation time 18643807682 ps
CPU time 49.75 seconds
Started Jul 20 04:57:25 PM PDT 24
Finished Jul 20 04:58:16 PM PDT 24
Peak memory 217568 kb
Host smart-b4dc1cc9-cbb6-40ed-b1df-7ce0a991a99c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737693859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2737693859
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1979454357
Short name T119
Test name
Test status
Simulation time 3210750781 ps
CPU time 13.97 seconds
Started Jul 20 04:57:31 PM PDT 24
Finished Jul 20 04:57:46 PM PDT 24
Peak memory 211440 kb
Host smart-0ff74857-02ae-45f3-a6b0-9737515486ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979454357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1979454357
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.171880050
Short name T220
Test name
Test status
Simulation time 54001245817 ps
CPU time 278.08 seconds
Started Jul 20 04:57:23 PM PDT 24
Finished Jul 20 05:02:02 PM PDT 24
Peak memory 225624 kb
Host smart-fdfd40e6-4f89-49ab-bb13-130c40f483e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171880050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.171880050
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3012658987
Short name T327
Test name
Test status
Simulation time 8364246410 ps
CPU time 34.34 seconds
Started Jul 20 04:57:24 PM PDT 24
Finished Jul 20 04:57:59 PM PDT 24
Peak memory 212476 kb
Host smart-1903b806-b9ba-49df-8e6c-0946b8f711c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012658987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3012658987
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2485623744
Short name T130
Test name
Test status
Simulation time 5114134966 ps
CPU time 11.63 seconds
Started Jul 20 04:57:23 PM PDT 24
Finished Jul 20 04:57:35 PM PDT 24
Peak memory 211396 kb
Host smart-e2a756ae-5296-4219-8289-ec068770ec55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2485623744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2485623744
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2917826152
Short name T155
Test name
Test status
Simulation time 3392628834 ps
CPU time 31.04 seconds
Started Jul 20 04:57:24 PM PDT 24
Finished Jul 20 04:57:56 PM PDT 24
Peak memory 213972 kb
Host smart-1741a877-28a9-48bb-8874-8c935b5dce73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917826152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2917826152
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3281469984
Short name T348
Test name
Test status
Simulation time 3486864961 ps
CPU time 11.47 seconds
Started Jul 20 04:57:24 PM PDT 24
Finished Jul 20 04:57:36 PM PDT 24
Peak memory 211304 kb
Host smart-a641a6a6-e140-49d1-8be0-ff766a4207b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281469984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3281469984
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1567174002
Short name T240
Test name
Test status
Simulation time 1642759424 ps
CPU time 14.01 seconds
Started Jul 20 04:57:33 PM PDT 24
Finished Jul 20 04:57:47 PM PDT 24
Peak memory 211368 kb
Host smart-f297074b-deaa-4d09-b6a8-5e464103ee51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567174002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1567174002
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3318770721
Short name T126
Test name
Test status
Simulation time 388525831 ps
CPU time 9.54 seconds
Started Jul 20 04:57:32 PM PDT 24
Finished Jul 20 04:57:42 PM PDT 24
Peak memory 212088 kb
Host smart-4d2f4c6d-18c7-460a-a3f7-73659708eb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318770721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3318770721
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2062395892
Short name T15
Test name
Test status
Simulation time 35493941123 ps
CPU time 17.82 seconds
Started Jul 20 04:57:33 PM PDT 24
Finished Jul 20 04:57:51 PM PDT 24
Peak memory 211384 kb
Host smart-22974973-c5da-498e-81a4-0d00d7c9b9d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2062395892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2062395892
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2185246863
Short name T227
Test name
Test status
Simulation time 25104453682 ps
CPU time 44.89 seconds
Started Jul 20 04:57:31 PM PDT 24
Finished Jul 20 04:58:16 PM PDT 24
Peak memory 214744 kb
Host smart-ef6f685c-d48d-4ee4-ba77-84d094499807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185246863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2185246863
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1449340664
Short name T158
Test name
Test status
Simulation time 704768420 ps
CPU time 11.5 seconds
Started Jul 20 04:57:31 PM PDT 24
Finished Jul 20 04:57:43 PM PDT 24
Peak memory 212060 kb
Host smart-0ed6221a-f580-4300-aca2-b178ba2e0bd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449340664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1449340664
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.554593940
Short name T275
Test name
Test status
Simulation time 35245698904 ps
CPU time 1072.62 seconds
Started Jul 20 04:57:29 PM PDT 24
Finished Jul 20 05:15:22 PM PDT 24
Peak memory 234228 kb
Host smart-fada3194-82bd-4d8f-aaaf-cbc995d506e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554593940 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.554593940
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3428224839
Short name T114
Test name
Test status
Simulation time 6497669928 ps
CPU time 13.86 seconds
Started Jul 20 04:57:30 PM PDT 24
Finished Jul 20 04:57:44 PM PDT 24
Peak memory 211356 kb
Host smart-513664e9-9016-4b60-9272-77c1c0a69fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428224839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3428224839
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3130857455
Short name T9
Test name
Test status
Simulation time 14058290923 ps
CPU time 107.75 seconds
Started Jul 20 04:57:31 PM PDT 24
Finished Jul 20 04:59:19 PM PDT 24
Peak memory 234884 kb
Host smart-a8aca65f-8fae-400d-a023-3e2fd5b7db49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130857455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3130857455
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3900797588
Short name T171
Test name
Test status
Simulation time 2907612875 ps
CPU time 27.53 seconds
Started Jul 20 04:57:30 PM PDT 24
Finished Jul 20 04:57:58 PM PDT 24
Peak memory 211460 kb
Host smart-34d4bc7c-d70e-4995-bb84-805b6969a2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900797588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3900797588
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.4106581253
Short name T351
Test name
Test status
Simulation time 1720517925 ps
CPU time 14.54 seconds
Started Jul 20 04:57:32 PM PDT 24
Finished Jul 20 04:57:47 PM PDT 24
Peak memory 211336 kb
Host smart-d5b4e32a-e05b-4c32-abce-a556be944840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106581253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.4106581253
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1324004679
Short name T116
Test name
Test status
Simulation time 3616229285 ps
CPU time 22.05 seconds
Started Jul 20 04:57:31 PM PDT 24
Finished Jul 20 04:57:54 PM PDT 24
Peak memory 213256 kb
Host smart-2dda4020-c9d0-47f2-a7cf-08c57c6e44ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324004679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1324004679
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.508931198
Short name T196
Test name
Test status
Simulation time 4136958073 ps
CPU time 24.48 seconds
Started Jul 20 04:57:31 PM PDT 24
Finished Jul 20 04:57:56 PM PDT 24
Peak memory 213888 kb
Host smart-988c8e85-18e4-4f7a-8fc1-a3ecd990cf7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508931198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.508931198
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1561713988
Short name T197
Test name
Test status
Simulation time 8362922257 ps
CPU time 15.1 seconds
Started Jul 20 04:57:41 PM PDT 24
Finished Jul 20 04:57:58 PM PDT 24
Peak memory 211376 kb
Host smart-490a7d4f-4c40-4afb-a281-bb58440f8c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561713988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1561713988
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2729628611
Short name T357
Test name
Test status
Simulation time 38736794770 ps
CPU time 212.14 seconds
Started Jul 20 04:57:31 PM PDT 24
Finished Jul 20 05:01:04 PM PDT 24
Peak memory 236672 kb
Host smart-aaa029ff-10b4-4fce-9607-d6e6f73620fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729628611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2729628611
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2589871133
Short name T295
Test name
Test status
Simulation time 2073454315 ps
CPU time 9.23 seconds
Started Jul 20 04:57:32 PM PDT 24
Finished Jul 20 04:57:42 PM PDT 24
Peak memory 211968 kb
Host smart-b83e8dce-986c-4584-8e0f-b0b2547fc8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589871133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2589871133
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.856454616
Short name T185
Test name
Test status
Simulation time 1713352509 ps
CPU time 14.34 seconds
Started Jul 20 04:57:31 PM PDT 24
Finished Jul 20 04:57:46 PM PDT 24
Peak memory 211404 kb
Host smart-49d5b1f4-738e-43c9-97c6-94568c404ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=856454616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.856454616
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.45127777
Short name T223
Test name
Test status
Simulation time 16361021421 ps
CPU time 37.51 seconds
Started Jul 20 04:57:31 PM PDT 24
Finished Jul 20 04:58:09 PM PDT 24
Peak memory 214292 kb
Host smart-891f0183-b51e-45d8-8f19-01ddff490af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45127777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.45127777
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2987813226
Short name T317
Test name
Test status
Simulation time 485051235 ps
CPU time 25.63 seconds
Started Jul 20 04:57:33 PM PDT 24
Finished Jul 20 04:57:59 PM PDT 24
Peak memory 214624 kb
Host smart-7becccd0-80e2-49cb-8808-ca567389c7a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987813226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2987813226
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1034894966
Short name T23
Test name
Test status
Simulation time 25353451980 ps
CPU time 494.53 seconds
Started Jul 20 04:57:31 PM PDT 24
Finished Jul 20 05:05:46 PM PDT 24
Peak memory 228412 kb
Host smart-939f5a92-8e61-4d38-b9d8-6192ecd851de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034894966 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1034894966
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.604453096
Short name T320
Test name
Test status
Simulation time 168737694 ps
CPU time 4.26 seconds
Started Jul 20 04:57:41 PM PDT 24
Finished Jul 20 04:57:47 PM PDT 24
Peak memory 211304 kb
Host smart-424b1321-3a43-4f44-b63c-8696e1a17ea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604453096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.604453096
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1453909997
Short name T250
Test name
Test status
Simulation time 297937844444 ps
CPU time 211.75 seconds
Started Jul 20 04:57:43 PM PDT 24
Finished Jul 20 05:01:16 PM PDT 24
Peak memory 213568 kb
Host smart-7f23a29a-6a88-4aca-adbd-077dbf6b30c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453909997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1453909997
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.606390587
Short name T356
Test name
Test status
Simulation time 26565998723 ps
CPU time 28.12 seconds
Started Jul 20 04:57:44 PM PDT 24
Finished Jul 20 04:58:12 PM PDT 24
Peak memory 212496 kb
Host smart-25360657-9dde-439d-b448-008f7659fa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606390587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.606390587
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2031801312
Short name T248
Test name
Test status
Simulation time 1845927186 ps
CPU time 15.7 seconds
Started Jul 20 04:57:43 PM PDT 24
Finished Jul 20 04:58:00 PM PDT 24
Peak memory 211400 kb
Host smart-6caa6666-238f-481b-a8d5-17558a1613d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031801312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2031801312
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1999271639
Short name T272
Test name
Test status
Simulation time 1689985078 ps
CPU time 14.04 seconds
Started Jul 20 04:57:42 PM PDT 24
Finished Jul 20 04:57:58 PM PDT 24
Peak memory 213660 kb
Host smart-df424652-f14e-4ec0-8b84-dff1ca11e5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999271639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1999271639
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1431506034
Short name T205
Test name
Test status
Simulation time 37010785165 ps
CPU time 65.62 seconds
Started Jul 20 04:57:42 PM PDT 24
Finished Jul 20 04:58:49 PM PDT 24
Peak memory 219520 kb
Host smart-d17cb9cb-4b8b-49c5-ae38-f52e30d42be5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431506034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1431506034
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2452135251
Short name T137
Test name
Test status
Simulation time 4384680525 ps
CPU time 8.53 seconds
Started Jul 20 04:55:42 PM PDT 24
Finished Jul 20 04:55:52 PM PDT 24
Peak memory 211416 kb
Host smart-87e837b0-a8b8-4fd4-8dae-c1ab24dff41b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452135251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2452135251
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.58809125
Short name T210
Test name
Test status
Simulation time 112258263057 ps
CPU time 249.06 seconds
Started Jul 20 04:55:41 PM PDT 24
Finished Jul 20 04:59:51 PM PDT 24
Peak memory 225636 kb
Host smart-a9ea5d96-07df-48b8-9b9c-396f9ec9c7a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58809125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_cor
rupt_sig_fatal_chk.58809125
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4231186259
Short name T310
Test name
Test status
Simulation time 7368331943 ps
CPU time 27.98 seconds
Started Jul 20 04:55:43 PM PDT 24
Finished Jul 20 04:56:12 PM PDT 24
Peak memory 212280 kb
Host smart-95d8a90c-5ca5-41ac-86b4-6e13173e43d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231186259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4231186259
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.830415940
Short name T300
Test name
Test status
Simulation time 96332561 ps
CPU time 5.95 seconds
Started Jul 20 04:55:41 PM PDT 24
Finished Jul 20 04:55:47 PM PDT 24
Peak memory 211400 kb
Host smart-20a4beee-4d62-44e7-8841-c064f0cd7574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830415940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.830415940
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3007393418
Short name T19
Test name
Test status
Simulation time 1938937936 ps
CPU time 61.73 seconds
Started Jul 20 04:55:40 PM PDT 24
Finished Jul 20 04:56:43 PM PDT 24
Peak memory 236568 kb
Host smart-5e6efddd-f895-47be-8b29-bcbb0e3d92a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007393418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3007393418
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1146792582
Short name T251
Test name
Test status
Simulation time 11439212182 ps
CPU time 30.83 seconds
Started Jul 20 04:55:43 PM PDT 24
Finished Jul 20 04:56:15 PM PDT 24
Peak memory 214444 kb
Host smart-ba0eca6f-1ae7-41cc-b582-c5ff60113196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146792582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1146792582
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2243394810
Short name T111
Test name
Test status
Simulation time 499148057 ps
CPU time 28.13 seconds
Started Jul 20 04:55:43 PM PDT 24
Finished Jul 20 04:56:12 PM PDT 24
Peak memory 215636 kb
Host smart-5920d04c-fad6-4947-9c2c-c046fcf72088
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243394810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2243394810
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1406220797
Short name T350
Test name
Test status
Simulation time 347880367 ps
CPU time 4.18 seconds
Started Jul 20 04:57:41 PM PDT 24
Finished Jul 20 04:57:45 PM PDT 24
Peak memory 211368 kb
Host smart-bb599528-e64a-408f-bd8f-b43f446f0ded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406220797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1406220797
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3957621258
Short name T340
Test name
Test status
Simulation time 203577442968 ps
CPU time 507.66 seconds
Started Jul 20 04:57:41 PM PDT 24
Finished Jul 20 05:06:09 PM PDT 24
Peak memory 237820 kb
Host smart-a9c1b795-81aa-4a73-9939-882d2c4ae139
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957621258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3957621258
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2309853837
Short name T198
Test name
Test status
Simulation time 2632918761 ps
CPU time 17.94 seconds
Started Jul 20 04:57:42 PM PDT 24
Finished Jul 20 04:58:01 PM PDT 24
Peak memory 212060 kb
Host smart-1ae9b3df-29a5-455b-accf-d1e99d8ae292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309853837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2309853837
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1998826287
Short name T294
Test name
Test status
Simulation time 559283431 ps
CPU time 8.72 seconds
Started Jul 20 04:57:42 PM PDT 24
Finished Jul 20 04:57:52 PM PDT 24
Peak memory 211380 kb
Host smart-314bab9d-46bf-43b2-989f-e8e283b175dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998826287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1998826287
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.431780991
Short name T178
Test name
Test status
Simulation time 10760182812 ps
CPU time 31.87 seconds
Started Jul 20 04:57:42 PM PDT 24
Finished Jul 20 04:58:15 PM PDT 24
Peak memory 214688 kb
Host smart-1d8fae77-0de9-481a-94ac-bf0e88db8a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431780991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.431780991
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1723254005
Short name T145
Test name
Test status
Simulation time 5395720659 ps
CPU time 23.77 seconds
Started Jul 20 04:57:40 PM PDT 24
Finished Jul 20 04:58:05 PM PDT 24
Peak memory 216752 kb
Host smart-0a5d4720-36d2-41b9-b934-0c8e52992f5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723254005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1723254005
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2481592566
Short name T260
Test name
Test status
Simulation time 5303536235 ps
CPU time 12.07 seconds
Started Jul 20 04:57:51 PM PDT 24
Finished Jul 20 04:58:04 PM PDT 24
Peak memory 211352 kb
Host smart-c929ad9d-8a4d-49ff-862d-57d0de8549b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481592566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2481592566
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.4045456663
Short name T279
Test name
Test status
Simulation time 5061766791 ps
CPU time 112.02 seconds
Started Jul 20 04:57:51 PM PDT 24
Finished Jul 20 04:59:43 PM PDT 24
Peak memory 234100 kb
Host smart-49f304b5-0207-471c-aba9-d490fd6edc98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045456663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.4045456663
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1609507716
Short name T296
Test name
Test status
Simulation time 3426464867 ps
CPU time 28.81 seconds
Started Jul 20 04:57:49 PM PDT 24
Finished Jul 20 04:58:18 PM PDT 24
Peak memory 211988 kb
Host smart-b651561f-d4d8-4fc1-81dd-084d122f8daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609507716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1609507716
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2106995165
Short name T17
Test name
Test status
Simulation time 464497888 ps
CPU time 8.12 seconds
Started Jul 20 04:57:41 PM PDT 24
Finished Jul 20 04:57:51 PM PDT 24
Peak memory 211384 kb
Host smart-bcb593d6-33bd-49c3-be6d-37eb7e49fef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2106995165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2106995165
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.783493480
Short name T12
Test name
Test status
Simulation time 1132718586 ps
CPU time 16.57 seconds
Started Jul 20 04:57:42 PM PDT 24
Finished Jul 20 04:58:00 PM PDT 24
Peak memory 213092 kb
Host smart-67ece79f-e95e-4fa7-9e27-9a62f65ab274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783493480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.783493480
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.97040965
Short name T242
Test name
Test status
Simulation time 145505554 ps
CPU time 7.23 seconds
Started Jul 20 04:57:41 PM PDT 24
Finished Jul 20 04:57:50 PM PDT 24
Peak memory 211404 kb
Host smart-9e2740b5-0880-454b-92e0-eeb2042cba2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97040965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.rom_ctrl_stress_all.97040965
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.232036088
Short name T321
Test name
Test status
Simulation time 1818675187 ps
CPU time 7.32 seconds
Started Jul 20 04:57:51 PM PDT 24
Finished Jul 20 04:57:59 PM PDT 24
Peak memory 211352 kb
Host smart-69a107f4-527c-43ed-8814-a628ddf4ff85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232036088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.232036088
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.4002578012
Short name T318
Test name
Test status
Simulation time 19844267070 ps
CPU time 254.67 seconds
Started Jul 20 04:57:51 PM PDT 24
Finished Jul 20 05:02:06 PM PDT 24
Peak memory 225656 kb
Host smart-294f60d4-863a-4e31-adca-2290918850d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002578012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.4002578012
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2972629628
Short name T45
Test name
Test status
Simulation time 207120947 ps
CPU time 9.65 seconds
Started Jul 20 04:57:52 PM PDT 24
Finished Jul 20 04:58:02 PM PDT 24
Peak memory 211876 kb
Host smart-0145024a-a9a7-4672-87d9-0520f6eae953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972629628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2972629628
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3894286588
Short name T228
Test name
Test status
Simulation time 4829361078 ps
CPU time 9.4 seconds
Started Jul 20 04:57:52 PM PDT 24
Finished Jul 20 04:58:02 PM PDT 24
Peak memory 211384 kb
Host smart-db62c653-98a9-46e0-ba76-071662e53400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894286588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3894286588
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2367233036
Short name T304
Test name
Test status
Simulation time 187641388 ps
CPU time 10.12 seconds
Started Jul 20 04:57:50 PM PDT 24
Finished Jul 20 04:58:01 PM PDT 24
Peak memory 213024 kb
Host smart-107a49a7-3cc3-40d3-8e3a-0fbd963080e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367233036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2367233036
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1954633704
Short name T33
Test name
Test status
Simulation time 23817480767 ps
CPU time 28.24 seconds
Started Jul 20 04:57:48 PM PDT 24
Finished Jul 20 04:58:16 PM PDT 24
Peak memory 214812 kb
Host smart-fbb20b46-87b4-4ed8-82f4-8b2c11bc9b54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954633704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1954633704
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.837689694
Short name T183
Test name
Test status
Simulation time 2473502338 ps
CPU time 12.3 seconds
Started Jul 20 04:57:51 PM PDT 24
Finished Jul 20 04:58:04 PM PDT 24
Peak memory 211416 kb
Host smart-01cabc4e-6442-4183-904d-e2ca4d8f44b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837689694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.837689694
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3824874437
Short name T355
Test name
Test status
Simulation time 49988720602 ps
CPU time 178.73 seconds
Started Jul 20 04:57:52 PM PDT 24
Finished Jul 20 05:00:52 PM PDT 24
Peak memory 212680 kb
Host smart-caee0be6-b041-4153-aa4f-3dc9aeb0c58f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824874437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3824874437
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1688623377
Short name T127
Test name
Test status
Simulation time 692566369 ps
CPU time 9.07 seconds
Started Jul 20 04:57:52 PM PDT 24
Finished Jul 20 04:58:02 PM PDT 24
Peak memory 211848 kb
Host smart-8fa180a2-f337-45c6-b43f-630d37778e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688623377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1688623377
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3409184797
Short name T324
Test name
Test status
Simulation time 1330330211 ps
CPU time 12.7 seconds
Started Jul 20 04:57:50 PM PDT 24
Finished Jul 20 04:58:03 PM PDT 24
Peak memory 211404 kb
Host smart-6663f8be-85db-4432-a0a4-5b1548d3e6e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409184797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3409184797
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2212140333
Short name T235
Test name
Test status
Simulation time 17381429816 ps
CPU time 22.92 seconds
Started Jul 20 04:57:49 PM PDT 24
Finished Jul 20 04:58:13 PM PDT 24
Peak memory 214164 kb
Host smart-96c6b1df-0084-4d8b-9222-d37880aea5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212140333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2212140333
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.215214433
Short name T331
Test name
Test status
Simulation time 18644739652 ps
CPU time 48.35 seconds
Started Jul 20 04:57:50 PM PDT 24
Finished Jul 20 04:58:39 PM PDT 24
Peak memory 217652 kb
Host smart-238fe842-6b70-4187-a084-4dd3ad4cb164
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215214433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.215214433
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.659089889
Short name T66
Test name
Test status
Simulation time 171600840 ps
CPU time 4.13 seconds
Started Jul 20 04:57:58 PM PDT 24
Finished Jul 20 04:58:03 PM PDT 24
Peak memory 211356 kb
Host smart-74887125-0eaf-409b-9166-38e6e93c3a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659089889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.659089889
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1871908834
Short name T170
Test name
Test status
Simulation time 43347242162 ps
CPU time 157.74 seconds
Started Jul 20 04:58:01 PM PDT 24
Finished Jul 20 05:00:40 PM PDT 24
Peak memory 238268 kb
Host smart-fa94a44c-c2ff-4816-95fb-2df31cfc6a4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871908834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1871908834
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2569067686
Short name T211
Test name
Test status
Simulation time 791839779 ps
CPU time 9.53 seconds
Started Jul 20 04:57:57 PM PDT 24
Finished Jul 20 04:58:07 PM PDT 24
Peak memory 211948 kb
Host smart-94091324-c137-475a-bf24-1c7d6a712b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569067686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2569067686
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.559911597
Short name T48
Test name
Test status
Simulation time 1002726801 ps
CPU time 11.06 seconds
Started Jul 20 04:57:58 PM PDT 24
Finished Jul 20 04:58:10 PM PDT 24
Peak memory 211396 kb
Host smart-a08535d4-51d5-42a3-a8d2-01130573bcfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559911597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.559911597
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1243270370
Short name T347
Test name
Test status
Simulation time 3999137611 ps
CPU time 22.26 seconds
Started Jul 20 04:57:51 PM PDT 24
Finished Jul 20 04:58:14 PM PDT 24
Peak memory 213908 kb
Host smart-6f4cf086-f86d-4305-a98b-2a2e17469e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243270370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1243270370
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4169549439
Short name T237
Test name
Test status
Simulation time 6528888890 ps
CPU time 28.96 seconds
Started Jul 20 04:57:50 PM PDT 24
Finished Jul 20 04:58:20 PM PDT 24
Peak memory 213224 kb
Host smart-98af05e5-8d80-4015-adc5-0fd924efa02c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169549439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4169549439
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3456038392
Short name T189
Test name
Test status
Simulation time 4622942799 ps
CPU time 11.62 seconds
Started Jul 20 04:58:00 PM PDT 24
Finished Jul 20 04:58:12 PM PDT 24
Peak memory 211440 kb
Host smart-0b6a01fb-dd30-4f5f-803b-1402147764af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456038392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3456038392
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3483081863
Short name T164
Test name
Test status
Simulation time 2094424567 ps
CPU time 128.01 seconds
Started Jul 20 04:58:01 PM PDT 24
Finished Jul 20 05:00:10 PM PDT 24
Peak memory 234856 kb
Host smart-0206e4d9-2a97-4274-a622-db3271af9e0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483081863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3483081863
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2717344490
Short name T307
Test name
Test status
Simulation time 1657433703 ps
CPU time 12.07 seconds
Started Jul 20 04:58:00 PM PDT 24
Finished Jul 20 04:58:13 PM PDT 24
Peak memory 211868 kb
Host smart-aaba639c-7e63-472d-a47d-267578441f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717344490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2717344490
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3109743425
Short name T313
Test name
Test status
Simulation time 556745326 ps
CPU time 5.21 seconds
Started Jul 20 04:57:58 PM PDT 24
Finished Jul 20 04:58:04 PM PDT 24
Peak memory 211400 kb
Host smart-1f30c73f-9952-4a1a-a53a-43e5158ffcd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109743425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3109743425
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2849534695
Short name T34
Test name
Test status
Simulation time 7617994187 ps
CPU time 35.54 seconds
Started Jul 20 04:57:57 PM PDT 24
Finished Jul 20 04:58:33 PM PDT 24
Peak memory 212776 kb
Host smart-7b79037b-8ee7-43e1-b3ff-15f27788cba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849534695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2849534695
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3712908602
Short name T184
Test name
Test status
Simulation time 4522979048 ps
CPU time 58.77 seconds
Started Jul 20 04:57:59 PM PDT 24
Finished Jul 20 04:58:58 PM PDT 24
Peak memory 214380 kb
Host smart-2cc5aeae-e79e-4dfb-a3f6-6dce78ce9637
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712908602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3712908602
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.4025157719
Short name T236
Test name
Test status
Simulation time 1313670131 ps
CPU time 11.8 seconds
Started Jul 20 04:58:07 PM PDT 24
Finished Jul 20 04:58:19 PM PDT 24
Peak memory 211296 kb
Host smart-9417199e-cd68-410e-9855-caff9cf7fe5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025157719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.4025157719
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2439780125
Short name T37
Test name
Test status
Simulation time 16361366890 ps
CPU time 220.21 seconds
Started Jul 20 04:57:57 PM PDT 24
Finished Jul 20 05:01:37 PM PDT 24
Peak memory 237432 kb
Host smart-e3c35b94-37cb-4c88-bcdb-5d8e6f027301
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439780125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2439780125
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.450244656
Short name T32
Test name
Test status
Simulation time 8180879306 ps
CPU time 32.43 seconds
Started Jul 20 04:58:05 PM PDT 24
Finished Jul 20 04:58:38 PM PDT 24
Peak memory 212692 kb
Host smart-023723c2-0a23-4ec0-9d77-56c79919a629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450244656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.450244656
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4038771175
Short name T277
Test name
Test status
Simulation time 350319556 ps
CPU time 7.95 seconds
Started Jul 20 04:57:57 PM PDT 24
Finished Jul 20 04:58:05 PM PDT 24
Peak memory 211348 kb
Host smart-4f5163d1-1567-4497-af93-c6dfe3b5ff6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038771175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4038771175
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.21786502
Short name T282
Test name
Test status
Simulation time 189090994 ps
CPU time 10.16 seconds
Started Jul 20 04:58:00 PM PDT 24
Finished Jul 20 04:58:11 PM PDT 24
Peak memory 211996 kb
Host smart-10e59424-29e2-46ab-8fad-4f53ed268eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21786502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.21786502
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3506198360
Short name T194
Test name
Test status
Simulation time 1430091369 ps
CPU time 24.02 seconds
Started Jul 20 04:57:58 PM PDT 24
Finished Jul 20 04:58:22 PM PDT 24
Peak memory 213348 kb
Host smart-380f5c7b-0819-4283-9355-b7330c80d224
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506198360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3506198360
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1647742044
Short name T139
Test name
Test status
Simulation time 1153736543 ps
CPU time 11.73 seconds
Started Jul 20 04:58:06 PM PDT 24
Finished Jul 20 04:58:18 PM PDT 24
Peak memory 211356 kb
Host smart-44eea5db-9412-435d-bba3-fa5bea4ada3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647742044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1647742044
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3252171522
Short name T221
Test name
Test status
Simulation time 37454247393 ps
CPU time 181.16 seconds
Started Jul 20 04:58:04 PM PDT 24
Finished Jul 20 05:01:06 PM PDT 24
Peak memory 227412 kb
Host smart-6cbcf10e-3554-4f83-afe8-a3dc28b70d01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252171522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3252171522
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3650745212
Short name T252
Test name
Test status
Simulation time 856165411 ps
CPU time 14.78 seconds
Started Jul 20 04:58:06 PM PDT 24
Finished Jul 20 04:58:21 PM PDT 24
Peak memory 211900 kb
Host smart-2a72b07e-1bc0-47f7-8b0b-a94bfc73a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650745212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3650745212
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.4223057071
Short name T186
Test name
Test status
Simulation time 1646973631 ps
CPU time 9.81 seconds
Started Jul 20 04:58:05 PM PDT 24
Finished Jul 20 04:58:16 PM PDT 24
Peak memory 211400 kb
Host smart-585fa2a1-fadf-42c8-b99b-75161cade4fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4223057071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.4223057071
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2094273219
Short name T285
Test name
Test status
Simulation time 9846169196 ps
CPU time 24.24 seconds
Started Jul 20 04:58:03 PM PDT 24
Finished Jul 20 04:58:28 PM PDT 24
Peak memory 213768 kb
Host smart-55acdffe-62f2-4596-bd7e-76b1e645d330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094273219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2094273219
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3501489856
Short name T292
Test name
Test status
Simulation time 376108738 ps
CPU time 8.34 seconds
Started Jul 20 04:58:05 PM PDT 24
Finished Jul 20 04:58:14 PM PDT 24
Peak memory 211368 kb
Host smart-ff82a71c-ecc9-4b27-aece-be3f61914ea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501489856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3501489856
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3983715658
Short name T22
Test name
Test status
Simulation time 71746356845 ps
CPU time 1342.99 seconds
Started Jul 20 04:58:05 PM PDT 24
Finished Jul 20 05:20:29 PM PDT 24
Peak memory 235860 kb
Host smart-b7a3a59c-dd76-485b-95d7-39c320bfac9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983715658 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3983715658
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1581908034
Short name T273
Test name
Test status
Simulation time 1641485957 ps
CPU time 13.18 seconds
Started Jul 20 04:58:09 PM PDT 24
Finished Jul 20 04:58:22 PM PDT 24
Peak memory 211316 kb
Host smart-86bc6e31-e28d-4e51-b43c-c9156fff525d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581908034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1581908034
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3134594259
Short name T38
Test name
Test status
Simulation time 103062885911 ps
CPU time 191.17 seconds
Started Jul 20 04:58:05 PM PDT 24
Finished Jul 20 05:01:17 PM PDT 24
Peak memory 237244 kb
Host smart-b9f56306-1ce3-415b-adc6-959b25977c4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134594259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3134594259
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.844522468
Short name T163
Test name
Test status
Simulation time 11269428347 ps
CPU time 25.36 seconds
Started Jul 20 04:58:04 PM PDT 24
Finished Jul 20 04:58:30 PM PDT 24
Peak memory 212236 kb
Host smart-65945cb9-1914-4385-bb57-727eee0cca55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844522468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.844522468
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1546075595
Short name T343
Test name
Test status
Simulation time 395379151 ps
CPU time 5.76 seconds
Started Jul 20 04:58:08 PM PDT 24
Finished Jul 20 04:58:14 PM PDT 24
Peak memory 211396 kb
Host smart-2d68e834-5b70-4f24-8569-473333d20437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1546075595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1546075595
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2919775674
Short name T259
Test name
Test status
Simulation time 1984406514 ps
CPU time 10.03 seconds
Started Jul 20 04:58:04 PM PDT 24
Finished Jul 20 04:58:15 PM PDT 24
Peak memory 213956 kb
Host smart-653e05ad-3882-48d7-8c48-d39c7fe3a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919775674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2919775674
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2420971983
Short name T243
Test name
Test status
Simulation time 59392744614 ps
CPU time 49.53 seconds
Started Jul 20 04:58:07 PM PDT 24
Finished Jul 20 04:58:57 PM PDT 24
Peak memory 213784 kb
Host smart-071bfc42-e08a-452d-9c6e-7029e9b6e56c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420971983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2420971983
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3043967034
Short name T266
Test name
Test status
Simulation time 818368636 ps
CPU time 7.14 seconds
Started Jul 20 04:58:12 PM PDT 24
Finished Jul 20 04:58:20 PM PDT 24
Peak memory 211368 kb
Host smart-2fd25e87-c8a9-4289-9159-4c9ffe140b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043967034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3043967034
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3544249300
Short name T261
Test name
Test status
Simulation time 49312777820 ps
CPU time 292.85 seconds
Started Jul 20 04:58:07 PM PDT 24
Finished Jul 20 05:03:00 PM PDT 24
Peak memory 234812 kb
Host smart-9975cc25-ec60-42bd-b8fb-ef530b0e86d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544249300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3544249300
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1739308194
Short name T281
Test name
Test status
Simulation time 4025867838 ps
CPU time 32.76 seconds
Started Jul 20 04:58:15 PM PDT 24
Finished Jul 20 04:58:48 PM PDT 24
Peak memory 211916 kb
Host smart-244b9df4-5ba6-48d3-88b1-d7c579ced55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739308194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1739308194
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.321258942
Short name T199
Test name
Test status
Simulation time 4364419678 ps
CPU time 17.05 seconds
Started Jul 20 04:58:06 PM PDT 24
Finished Jul 20 04:58:23 PM PDT 24
Peak memory 211448 kb
Host smart-202bf787-73a2-45a2-900f-e157f081875b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=321258942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.321258942
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3648149181
Short name T159
Test name
Test status
Simulation time 1856771071 ps
CPU time 20.63 seconds
Started Jul 20 04:58:05 PM PDT 24
Finished Jul 20 04:58:27 PM PDT 24
Peak memory 213892 kb
Host smart-6b60b7a7-b48a-4a58-a923-45b7f2a3ceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648149181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3648149181
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.204399023
Short name T208
Test name
Test status
Simulation time 1337141910 ps
CPU time 36.31 seconds
Started Jul 20 04:58:05 PM PDT 24
Finished Jul 20 04:58:42 PM PDT 24
Peak memory 216192 kb
Host smart-3963c0f3-ea82-4990-a474-6d6426362740
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204399023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.204399023
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3257310742
Short name T149
Test name
Test status
Simulation time 1056774540 ps
CPU time 10.71 seconds
Started Jul 20 04:55:48 PM PDT 24
Finished Jul 20 04:56:00 PM PDT 24
Peak memory 211280 kb
Host smart-0123ab27-ca0e-4487-b1b9-5874f8ec54cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257310742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3257310742
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3701952730
Short name T306
Test name
Test status
Simulation time 12621414710 ps
CPU time 188.26 seconds
Started Jul 20 04:55:50 PM PDT 24
Finished Jul 20 04:58:59 PM PDT 24
Peak memory 234888 kb
Host smart-22cfeb88-ca12-4e3a-8710-ff3f5bd9bece
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701952730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3701952730
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.407201896
Short name T229
Test name
Test status
Simulation time 4103093583 ps
CPU time 32.39 seconds
Started Jul 20 04:55:51 PM PDT 24
Finished Jul 20 04:56:24 PM PDT 24
Peak memory 211844 kb
Host smart-9058d226-fdd3-47b7-ae90-6a85d42fccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407201896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.407201896
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4054352941
Short name T234
Test name
Test status
Simulation time 4308837521 ps
CPU time 17.37 seconds
Started Jul 20 04:55:50 PM PDT 24
Finished Jul 20 04:56:08 PM PDT 24
Peak memory 211392 kb
Host smart-b976d984-54db-4182-904f-259c5a2e95c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054352941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4054352941
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2196562852
Short name T209
Test name
Test status
Simulation time 6106913199 ps
CPU time 31.57 seconds
Started Jul 20 04:55:43 PM PDT 24
Finished Jul 20 04:56:15 PM PDT 24
Peak memory 213904 kb
Host smart-2dc31692-4f44-410f-847d-772e6e2579ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196562852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2196562852
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3518713120
Short name T13
Test name
Test status
Simulation time 35878417994 ps
CPU time 37.38 seconds
Started Jul 20 04:55:49 PM PDT 24
Finished Jul 20 04:56:28 PM PDT 24
Peak memory 214880 kb
Host smart-78d5f8ec-ed9f-4a95-b179-1bae0a394b10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518713120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3518713120
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2660785006
Short name T332
Test name
Test status
Simulation time 7505489974 ps
CPU time 14.76 seconds
Started Jul 20 04:55:52 PM PDT 24
Finished Jul 20 04:56:08 PM PDT 24
Peak memory 211308 kb
Host smart-504c6df5-f7f9-4c68-b1ea-ff186239719f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660785006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2660785006
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3982068334
Short name T245
Test name
Test status
Simulation time 1661639941 ps
CPU time 83.71 seconds
Started Jul 20 04:55:49 PM PDT 24
Finished Jul 20 04:57:14 PM PDT 24
Peak memory 237056 kb
Host smart-ac9e11b6-1a7e-456f-a55a-e789a4e4a24e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982068334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3982068334
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1029920933
Short name T274
Test name
Test status
Simulation time 1875858674 ps
CPU time 12.29 seconds
Started Jul 20 04:55:49 PM PDT 24
Finished Jul 20 04:56:03 PM PDT 24
Peak memory 212020 kb
Host smart-6e9275ff-7d6a-4f7b-b511-c089389d7595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029920933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1029920933
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3898711497
Short name T316
Test name
Test status
Simulation time 1803632768 ps
CPU time 15.45 seconds
Started Jul 20 04:55:48 PM PDT 24
Finished Jul 20 04:56:03 PM PDT 24
Peak memory 211556 kb
Host smart-fc84aa7b-2590-4183-ace5-74a416cfa79d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898711497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3898711497
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2180265891
Short name T276
Test name
Test status
Simulation time 13687417630 ps
CPU time 30.22 seconds
Started Jul 20 04:55:50 PM PDT 24
Finished Jul 20 04:56:21 PM PDT 24
Peak memory 212944 kb
Host smart-5719c607-be12-4b78-b125-f8401fb8d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180265891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2180265891
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.197193690
Short name T341
Test name
Test status
Simulation time 9475081847 ps
CPU time 89.59 seconds
Started Jul 20 04:55:53 PM PDT 24
Finished Jul 20 04:57:23 PM PDT 24
Peak memory 216152 kb
Host smart-73779c97-e4a9-4e9d-ae28-fa7df988752f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197193690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.197193690
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2805395005
Short name T7
Test name
Test status
Simulation time 5822507284 ps
CPU time 13.44 seconds
Started Jul 20 04:55:50 PM PDT 24
Finished Jul 20 04:56:04 PM PDT 24
Peak memory 211364 kb
Host smart-96a58520-6c77-4174-a0b3-a673044775a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805395005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2805395005
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.723456993
Short name T268
Test name
Test status
Simulation time 20460064518 ps
CPU time 226.96 seconds
Started Jul 20 04:55:50 PM PDT 24
Finished Jul 20 04:59:38 PM PDT 24
Peak memory 237784 kb
Host smart-bd9c58ad-6d01-4c3f-b0f2-1d50312d309c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723456993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.723456993
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.571762929
Short name T162
Test name
Test status
Simulation time 15139653054 ps
CPU time 34.05 seconds
Started Jul 20 04:55:51 PM PDT 24
Finished Jul 20 04:56:25 PM PDT 24
Peak memory 212212 kb
Host smart-234c1879-6835-4086-af94-ddcc43588187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571762929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.571762929
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.699995897
Short name T325
Test name
Test status
Simulation time 3314078783 ps
CPU time 15.18 seconds
Started Jul 20 04:55:49 PM PDT 24
Finished Jul 20 04:56:05 PM PDT 24
Peak memory 211392 kb
Host smart-65f3f4b6-6dc7-41ad-9073-d45378ee4a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699995897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.699995897
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.280326762
Short name T278
Test name
Test status
Simulation time 351704360 ps
CPU time 10.12 seconds
Started Jul 20 04:55:49 PM PDT 24
Finished Jul 20 04:56:01 PM PDT 24
Peak memory 213760 kb
Host smart-739247ff-86e7-468d-a3cc-ee518fd5f4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280326762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.280326762
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1401551754
Short name T141
Test name
Test status
Simulation time 3043007641 ps
CPU time 13.91 seconds
Started Jul 20 04:55:49 PM PDT 24
Finished Jul 20 04:56:05 PM PDT 24
Peak memory 211416 kb
Host smart-79750f16-54ce-42dd-8467-7bb8b79ff2a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401551754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1401551754
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1326184906
Short name T291
Test name
Test status
Simulation time 1184300078 ps
CPU time 11.72 seconds
Started Jul 20 04:55:59 PM PDT 24
Finished Jul 20 04:56:12 PM PDT 24
Peak memory 211236 kb
Host smart-4ffa9e69-ae58-4692-8496-07bd73cbdbcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326184906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1326184906
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2565901659
Short name T238
Test name
Test status
Simulation time 121608287799 ps
CPU time 204.93 seconds
Started Jul 20 04:55:59 PM PDT 24
Finished Jul 20 04:59:25 PM PDT 24
Peak memory 240376 kb
Host smart-29d3b2f6-c01f-428b-8f46-07eab543d017
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565901659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2565901659
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1071147431
Short name T258
Test name
Test status
Simulation time 9851943660 ps
CPU time 32.79 seconds
Started Jul 20 04:55:58 PM PDT 24
Finished Jul 20 04:56:32 PM PDT 24
Peak memory 212296 kb
Host smart-cec4e451-de55-43c2-8aeb-aa45a637f672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071147431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1071147431
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3133113579
Short name T233
Test name
Test status
Simulation time 21006806387 ps
CPU time 17.89 seconds
Started Jul 20 04:55:58 PM PDT 24
Finished Jul 20 04:56:17 PM PDT 24
Peak memory 211460 kb
Host smart-6550394a-af91-4358-a254-321ea47c30a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133113579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3133113579
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.329224557
Short name T269
Test name
Test status
Simulation time 186864812 ps
CPU time 10.4 seconds
Started Jul 20 04:55:49 PM PDT 24
Finished Jul 20 04:56:01 PM PDT 24
Peak memory 213656 kb
Host smart-8c758f62-9b9d-4597-8416-64179604276a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329224557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.329224557
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1474748327
Short name T28
Test name
Test status
Simulation time 1196883713 ps
CPU time 34.81 seconds
Started Jul 20 04:55:59 PM PDT 24
Finished Jul 20 04:56:35 PM PDT 24
Peak memory 215348 kb
Host smart-f390ec36-2d78-4d91-be7b-50402facad80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474748327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1474748327
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.849337769
Short name T231
Test name
Test status
Simulation time 8696458154 ps
CPU time 11.34 seconds
Started Jul 20 04:55:59 PM PDT 24
Finished Jul 20 04:56:12 PM PDT 24
Peak memory 211408 kb
Host smart-5e4dce58-c527-4f08-bf24-9c4a7d799f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849337769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.849337769
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2960895634
Short name T206
Test name
Test status
Simulation time 21511686194 ps
CPU time 151.47 seconds
Started Jul 20 04:55:58 PM PDT 24
Finished Jul 20 04:58:31 PM PDT 24
Peak memory 224840 kb
Host smart-f5883187-1fc7-41be-b06b-4ee63f05c9b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960895634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2960895634
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1590292145
Short name T174
Test name
Test status
Simulation time 346986814 ps
CPU time 9.48 seconds
Started Jul 20 04:55:57 PM PDT 24
Finished Jul 20 04:56:07 PM PDT 24
Peak memory 211972 kb
Host smart-5de5d0d1-995c-4994-9828-5215cbbd4337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590292145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1590292145
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2200320613
Short name T154
Test name
Test status
Simulation time 102959917 ps
CPU time 5.83 seconds
Started Jul 20 04:55:57 PM PDT 24
Finished Jul 20 04:56:04 PM PDT 24
Peak memory 211544 kb
Host smart-2c8f924e-9964-4dac-8f40-d518ba20ce05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200320613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2200320613
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.561380206
Short name T175
Test name
Test status
Simulation time 1498903695 ps
CPU time 18.52 seconds
Started Jul 20 04:56:00 PM PDT 24
Finished Jul 20 04:56:19 PM PDT 24
Peak memory 213076 kb
Host smart-8418ea19-8076-4318-a911-e447a19f595a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561380206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.561380206
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3852978661
Short name T42
Test name
Test status
Simulation time 30848191061 ps
CPU time 1202.75 seconds
Started Jul 20 04:56:01 PM PDT 24
Finished Jul 20 05:16:05 PM PDT 24
Peak memory 235712 kb
Host smart-4a571e75-981f-4989-b8ab-2d9f552cb5b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852978661 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3852978661
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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