Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 51649 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1023959 1 T1 22 T2 15 T3 13



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 289645 1 T1 288 T2 180 T3 153
values[0x0] 386203 1 T6 16263 T11 19720 T12 28692
values[0x1] 399760 1 T6 16673 T11 20438 T12 29717



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 25795 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1049813 1 T1 178 T2 108 T3 98



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 4236 1 T6 206 T103 2 T11 208
valid_sources[0x01] 4487 1 T6 229 T77 1 T117 2
valid_sources[0x02] 4886 1 T1 2 T6 174 T47 1
valid_sources[0x03] 3611 1 T6 212 T103 4 T118 3
valid_sources[0x04] 3423 1 T6 110 T117 1 T118 2
valid_sources[0x05] 3865 1 T6 155 T14 1 T104 2
valid_sources[0x06] 4217 1 T6 94 T7 1 T104 1
valid_sources[0x07] 4073 1 T6 200 T117 1 T103 1
valid_sources[0x08] 4198 1 T5 1 T6 201 T7 1
valid_sources[0x09] 3783 1 T6 152 T7 2 T103 2
valid_sources[0x0a] 4729 1 T6 145 T117 1 T119 4
valid_sources[0x0b] 4245 1 T6 163 T7 1 T77 1
valid_sources[0x0c] 4127 1 T2 4 T6 189 T7 4
valid_sources[0x0d] 4598 1 T6 211 T104 1 T117 2
valid_sources[0x0e] 4021 1 T6 200 T7 1 T117 2
valid_sources[0x0f] 4714 1 T3 15 T6 230 T77 1
valid_sources[0x10] 3610 1 T1 20 T2 5 T5 3
valid_sources[0x11] 4542 1 T6 133 T117 3 T103 2
valid_sources[0x12] 4556 1 T6 193 T7 2 T117 1
valid_sources[0x13] 4140 1 T4 21 T6 174 T118 2
valid_sources[0x14] 3896 1 T6 205 T7 3 T10 5
valid_sources[0x15] 3968 1 T6 155 T104 1 T117 1
valid_sources[0x16] 5170 1 T6 177 T117 1 T119 4
valid_sources[0x17] 5279 1 T6 190 T7 4 T10 1
valid_sources[0x18] 3757 1 T6 178 T7 1 T117 1
valid_sources[0x19] 4538 1 T6 137 T10 18 T104 1
valid_sources[0x1a] 3580 1 T6 135 T7 5 T104 1
valid_sources[0x1b] 4244 1 T6 179 T7 1 T104 1
valid_sources[0x1c] 4173 1 T6 165 T7 2 T104 1
valid_sources[0x1d] 3953 1 T4 38 T6 222 T7 1
valid_sources[0x1e] 3508 1 T6 116 T7 2 T104 1
valid_sources[0x1f] 3545 1 T6 148 T7 1 T103 5
valid_sources[0x20] 3924 1 T6 135 T7 1 T101 11
valid_sources[0x21] 4368 1 T6 163 T7 1 T101 12
valid_sources[0x22] 4046 1 T2 4 T6 170 T7 1
valid_sources[0x23] 3855 1 T6 154 T14 2 T117 1
valid_sources[0x24] 4525 1 T1 2 T6 233 T102 20
valid_sources[0x25] 5579 1 T2 1 T6 159 T7 2
valid_sources[0x26] 3669 1 T6 114 T7 2 T14 1
valid_sources[0x27] 4546 1 T1 6 T6 198 T7 3
valid_sources[0x28] 3781 1 T6 136 T117 2 T103 2
valid_sources[0x29] 5166 1 T2 10 T6 142 T78 1
valid_sources[0x2a] 5506 1 T6 183 T7 3 T104 1
valid_sources[0x2b] 4350 1 T1 10 T6 179 T7 1
valid_sources[0x2c] 3856 1 T6 157 T77 1 T117 1
valid_sources[0x2d] 3960 1 T2 5 T6 162 T7 2
valid_sources[0x2e] 5478 1 T6 172 T7 3 T104 1
valid_sources[0x2f] 3918 1 T2 15 T6 137 T7 1
valid_sources[0x30] 3947 1 T6 239 T7 2 T9 36
valid_sources[0x31] 3561 1 T6 158 T11 198 T27 1
valid_sources[0x32] 3576 1 T6 136 T7 2 T77 3
valid_sources[0x33] 3949 1 T6 194 T7 1 T103 1
valid_sources[0x34] 4053 1 T2 3 T5 2 T6 193
valid_sources[0x35] 3637 1 T5 2 T6 169 T7 1
valid_sources[0x36] 4093 1 T6 144 T103 1 T11 225
valid_sources[0x37] 3692 1 T6 205 T7 1 T103 1
valid_sources[0x38] 4367 1 T6 200 T7 1 T119 2
valid_sources[0x39] 4433 1 T5 3 T6 200 T7 1
valid_sources[0x3a] 4482 1 T5 2 T6 127 T7 1
valid_sources[0x3b] 3466 1 T2 3 T5 1 T6 181
valid_sources[0x3c] 4825 1 T6 151 T15 1 T11 215
valid_sources[0x3d] 3984 1 T5 2 T6 130 T119 4
valid_sources[0x3e] 3841 1 T6 162 T7 2 T42 8
valid_sources[0x3f] 4059 1 T6 174 T7 2 T42 1
valid_sources[0x40] 4297 1 T2 1 T5 2 T6 157
valid_sources[0x41] 4132 1 T6 265 T7 1 T11 224
valid_sources[0x42] 4259 1 T6 143 T7 3 T103 1
valid_sources[0x43] 5037 1 T6 209 T104 3 T78 1
valid_sources[0x44] 4115 1 T6 211 T7 3 T103 4
valid_sources[0x45] 4069 1 T6 162 T77 2 T103 2
valid_sources[0x46] 4731 1 T5 5 T6 177 T7 1
valid_sources[0x47] 4104 1 T6 152 T104 1 T103 1
valid_sources[0x48] 3898 1 T6 141 T118 1 T11 199
valid_sources[0x49] 4103 1 T2 6 T6 209 T7 3
valid_sources[0x4a] 4653 1 T1 3 T4 67 T6 172
valid_sources[0x4b] 5063 1 T6 151 T7 1 T117 1
valid_sources[0x4c] 4403 1 T1 3 T6 183 T7 1
valid_sources[0x4d] 4189 1 T6 151 T7 1 T42 2
valid_sources[0x4e] 3865 1 T6 148 T7 2 T104 1
valid_sources[0x4f] 5923 1 T6 143 T117 1 T119 7
valid_sources[0x50] 3761 1 T6 214 T7 2 T14 1
valid_sources[0x51] 4888 1 T6 123 T104 1 T119 3
valid_sources[0x52] 3621 1 T6 219 T7 2 T117 2
valid_sources[0x53] 3982 1 T6 201 T7 2 T104 1
valid_sources[0x54] 4100 1 T1 21 T6 187 T7 1
valid_sources[0x55] 4009 1 T6 149 T10 4 T104 2
valid_sources[0x56] 4337 1 T6 146 T7 1 T11 150
valid_sources[0x57] 4045 1 T6 191 T7 2 T10 20
valid_sources[0x58] 4255 1 T1 1 T6 149 T104 3
valid_sources[0x59] 4039 1 T2 2 T5 2 T6 189
valid_sources[0x5a] 3893 1 T6 187 T7 1 T104 1
valid_sources[0x5b] 4624 1 T1 16 T2 3 T6 206
valid_sources[0x5c] 3913 1 T2 1 T5 1 T6 146
valid_sources[0x5d] 3870 1 T2 5 T6 230 T7 2
valid_sources[0x5e] 4572 1 T1 17 T3 15 T6 164
valid_sources[0x5f] 4412 1 T6 137 T7 2 T101 24
valid_sources[0x60] 3979 1 T1 7 T6 142 T42 1
valid_sources[0x61] 4223 1 T6 160 T7 1 T103 1
valid_sources[0x62] 4176 1 T1 12 T6 157 T42 2
valid_sources[0x63] 4350 1 T6 198 T7 1 T117 2
valid_sources[0x64] 5295 1 T1 3 T6 204 T7 1
valid_sources[0x65] 4671 1 T4 12 T6 178 T7 5
valid_sources[0x66] 3639 1 T6 196 T7 1 T117 1
valid_sources[0x67] 4154 1 T5 1 T6 180 T7 2
valid_sources[0x68] 4179 1 T2 2 T6 186 T42 9
valid_sources[0x69] 4869 1 T6 142 T7 1 T117 3
valid_sources[0x6a] 4171 1 T6 187 T7 1 T104 1
valid_sources[0x6b] 4893 1 T6 253 T7 1 T77 1
valid_sources[0x6c] 4081 1 T6 157 T117 1 T103 1
valid_sources[0x6d] 4028 1 T2 9 T6 162 T77 3
valid_sources[0x6e] 4382 1 T6 170 T117 1 T78 2
valid_sources[0x6f] 3665 1 T6 164 T77 1 T103 1
valid_sources[0x70] 3729 1 T4 10 T6 184 T7 2
valid_sources[0x71] 4112 1 T1 3 T6 185 T10 3
valid_sources[0x72] 4372 1 T6 175 T7 3 T11 186
valid_sources[0x73] 4321 1 T4 34 T6 188 T104 1
valid_sources[0x74] 4089 1 T2 3 T6 192 T9 25
valid_sources[0x75] 4455 1 T6 105 T42 4 T104 1
valid_sources[0x76] 3541 1 T6 233 T47 1 T104 1
valid_sources[0x77] 4431 1 T6 142 T7 5 T117 1
valid_sources[0x78] 3824 1 T2 3 T5 1 T6 168
valid_sources[0x79] 4082 1 T1 5 T6 208 T117 1
valid_sources[0x7a] 5031 1 T6 147 T103 1 T119 5
valid_sources[0x7b] 4865 1 T1 8 T6 154 T7 1
valid_sources[0x7c] 3905 1 T6 173 T7 1 T104 1
valid_sources[0x7d] 3811 1 T5 7 T6 143 T117 3
valid_sources[0x7e] 3656 1 T6 205 T7 3 T119 4
valid_sources[0x7f] 4431 1 T6 197 T104 2 T77 2
valid_sources[0x80] 4911 1 T5 2 T6 262 T7 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 258284 1 T1 22 T2 15 T3 13
values[0x0] all_enables biggest_size 382906 1 T6 16117 T11 19562 T12 28439
values[0x1] all_enables biggest_size 382769 1 T6 15960 T11 19618 T12 28412


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 78404 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 778844 1 T1 58 T2 30 T3 33



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 216728 1 T1 128 T2 64 T3 64
values[0x0] 297114 1 T6 13505 T19 8 T20 6
values[0x1] 343406 1 T6 15772 T19 4 T20 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 36372 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 820876 1 T1 75 T2 37 T3 36



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3557 1 T1 2 T2 1 T6 153
valid_sources[0x01] 3755 1 T6 160 T11 208 T120 3
valid_sources[0x02] 3260 1 T6 154 T11 133 T79 7
valid_sources[0x03] 3770 1 T6 92 T11 204 T121 1
valid_sources[0x04] 3796 1 T3 2 T6 124 T11 180
valid_sources[0x05] 2913 1 T6 77 T11 164 T115 1
valid_sources[0x06] 2538 1 T1 4 T6 136 T11 169
valid_sources[0x07] 3389 1 T6 39 T11 114 T122 1
valid_sources[0x08] 3720 1 T2 1 T6 172 T11 172
valid_sources[0x09] 2901 1 T6 195 T7 1 T11 147
valid_sources[0x0a] 3708 1 T6 36 T7 2 T11 197
valid_sources[0x0b] 3256 1 T2 1 T6 175 T51 2
valid_sources[0x0c] 2641 1 T6 105 T11 176 T123 1
valid_sources[0x0d] 2794 1 T1 1 T6 62 T7 2
valid_sources[0x0e] 2694 1 T6 17 T11 161 T120 2
valid_sources[0x0f] 3144 1 T6 193 T14 2 T64 1
valid_sources[0x10] 3243 1 T2 1 T3 1 T6 95
valid_sources[0x11] 4128 1 T2 1 T6 121 T11 229
valid_sources[0x12] 3643 1 T6 205 T11 201 T82 1
valid_sources[0x13] 3227 1 T6 43 T65 1 T11 191
valid_sources[0x14] 3733 1 T2 1 T5 1 T6 145
valid_sources[0x15] 3399 1 T6 169 T11 170 T124 1
valid_sources[0x16] 3087 1 T6 130 T7 1 T11 165
valid_sources[0x17] 3044 1 T3 1 T6 269 T11 154
valid_sources[0x18] 3254 1 T6 129 T11 194 T68 1
valid_sources[0x19] 2921 1 T1 3 T6 230 T7 1
valid_sources[0x1a] 3976 1 T6 416 T11 178 T12 275
valid_sources[0x1b] 3562 1 T6 98 T11 175 T12 281
valid_sources[0x1c] 3785 1 T2 1 T3 1 T5 1
valid_sources[0x1d] 2981 1 T1 1 T6 87 T15 3
valid_sources[0x1e] 2811 1 T1 3 T2 1 T5 2
valid_sources[0x1f] 4152 1 T1 1 T5 1 T6 162
valid_sources[0x20] 3333 1 T2 1 T6 25 T7 1
valid_sources[0x21] 3552 1 T1 1 T6 222 T7 9
valid_sources[0x22] 3763 1 T6 34 T11 161 T122 1
valid_sources[0x23] 3318 1 T6 229 T50 4 T11 136
valid_sources[0x24] 3533 1 T2 1 T3 5 T6 629
valid_sources[0x25] 2862 1 T6 313 T11 203 T121 1
valid_sources[0x26] 3575 1 T1 5 T3 1 T6 182
valid_sources[0x27] 2566 1 T1 1 T2 1 T6 115
valid_sources[0x28] 3273 1 T6 331 T11 194 T80 1
valid_sources[0x29] 3391 1 T2 1 T3 3 T6 43
valid_sources[0x2a] 2774 1 T1 3 T6 100 T11 194
valid_sources[0x2b] 3899 1 T6 258 T11 142 T125 1
valid_sources[0x2c] 3625 1 T1 1 T3 1 T6 168
valid_sources[0x2d] 2722 1 T6 131 T11 147 T121 1
valid_sources[0x2e] 3635 1 T6 208 T7 1 T11 164
valid_sources[0x2f] 3469 1 T6 25 T11 129 T121 1
valid_sources[0x30] 3339 1 T6 160 T7 3 T11 164
valid_sources[0x31] 3617 1 T6 172 T7 1 T11 170
valid_sources[0x32] 3481 1 T6 210 T51 1 T11 197
valid_sources[0x33] 3348 1 T1 1 T2 2 T3 1
valid_sources[0x34] 3731 1 T5 1 T6 121 T11 196
valid_sources[0x35] 3469 1 T6 114 T11 116 T122 2
valid_sources[0x36] 3403 1 T1 1 T6 190 T11 275
valid_sources[0x37] 2975 1 T6 32 T7 1 T11 147
valid_sources[0x38] 3119 1 T2 1 T3 2 T5 1
valid_sources[0x39] 2748 1 T6 47 T47 18 T35 1
valid_sources[0x3a] 4402 1 T6 264 T15 1 T11 134
valid_sources[0x3b] 2835 1 T6 130 T11 148 T125 2
valid_sources[0x3c] 3222 1 T6 259 T11 173 T120 1
valid_sources[0x3d] 2848 1 T6 132 T11 118 T126 1
valid_sources[0x3e] 3436 1 T6 146 T7 4 T11 137
valid_sources[0x3f] 2815 1 T3 1 T6 161 T35 1
valid_sources[0x40] 3632 1 T6 128 T65 2 T11 218
valid_sources[0x41] 3844 1 T2 1 T3 3 T6 156
valid_sources[0x42] 3159 1 T1 3 T6 152 T7 5
valid_sources[0x43] 2511 1 T6 131 T11 111 T125 1
valid_sources[0x44] 3355 1 T6 197 T51 1 T11 184
valid_sources[0x45] 3356 1 T1 1 T2 1 T3 3
valid_sources[0x46] 3022 1 T6 287 T10 1 T11 169
valid_sources[0x47] 2560 1 T6 130 T11 191 T127 1
valid_sources[0x48] 3198 1 T6 51 T11 196 T41 2
valid_sources[0x49] 3029 1 T6 154 T11 162 T12 251
valid_sources[0x4a] 3749 1 T6 254 T7 1 T11 198
valid_sources[0x4b] 3360 1 T6 134 T15 1 T11 205
valid_sources[0x4c] 3236 1 T5 1 T6 177 T11 138
valid_sources[0x4d] 2730 1 T6 83 T7 1 T35 1
valid_sources[0x4e] 3571 1 T6 108 T7 5 T11 215
valid_sources[0x4f] 3433 1 T1 2 T6 245 T11 223
valid_sources[0x50] 2819 1 T2 1 T6 168 T11 147
valid_sources[0x51] 3025 1 T6 257 T11 109 T68 1
valid_sources[0x52] 2694 1 T5 1 T6 119 T11 179
valid_sources[0x53] 3792 1 T1 5 T6 206 T11 192
valid_sources[0x54] 3684 1 T1 3 T6 152 T15 1
valid_sources[0x55] 3095 1 T1 2 T2 1 T6 199
valid_sources[0x56] 3473 1 T6 43 T11 178 T127 1
valid_sources[0x57] 3190 1 T6 149 T64 1 T11 148
valid_sources[0x58] 2464 1 T6 43 T51 1 T78 64
valid_sources[0x59] 3742 1 T5 1 T6 104 T11 236
valid_sources[0x5a] 3337 1 T6 90 T11 129 T115 1
valid_sources[0x5b] 3108 1 T3 1 T6 202 T7 2
valid_sources[0x5c] 2956 1 T6 134 T11 121 T38 23
valid_sources[0x5d] 3941 1 T6 9 T7 1 T11 126
valid_sources[0x5e] 3083 1 T1 4 T6 154 T7 1
valid_sources[0x5f] 2779 1 T1 1 T3 2 T6 57
valid_sources[0x60] 2883 1 T6 96 T7 1 T11 167
valid_sources[0x61] 3044 1 T6 133 T7 1 T11 199
valid_sources[0x62] 4285 1 T1 2 T6 139 T7 1
valid_sources[0x63] 3085 1 T1 3 T2 1 T6 115
valid_sources[0x64] 3289 1 T1 1 T6 95 T11 184
valid_sources[0x65] 3284 1 T1 5 T5 2 T6 114
valid_sources[0x66] 3638 1 T1 1 T5 1 T6 212
valid_sources[0x67] 3772 1 T3 1 T6 194 T11 186
valid_sources[0x68] 3468 1 T1 3 T6 182 T11 163
valid_sources[0x69] 3574 1 T6 218 T11 166 T27 2
valid_sources[0x6a] 3246 1 T1 1 T6 96 T35 3
valid_sources[0x6b] 3247 1 T2 1 T6 43 T11 148
valid_sources[0x6c] 3003 1 T2 1 T6 113 T11 200
valid_sources[0x6d] 2709 1 T1 4 T2 1 T3 2
valid_sources[0x6e] 3000 1 T6 117 T11 148 T121 1
valid_sources[0x6f] 3510 1 T6 134 T21 1 T51 1
valid_sources[0x70] 2429 1 T1 1 T6 45 T51 2
valid_sources[0x71] 3047 1 T5 1 T6 61 T7 1
valid_sources[0x72] 2967 1 T2 1 T6 260 T11 164
valid_sources[0x73] 3487 1 T2 1 T6 6 T64 1
valid_sources[0x74] 3190 1 T6 71 T10 1 T11 188
valid_sources[0x75] 2772 1 T1 1 T6 126 T11 164
valid_sources[0x76] 3140 1 T6 44 T7 1 T15 1
valid_sources[0x77] 3412 1 T2 1 T6 127 T35 2
valid_sources[0x78] 3717 1 T6 203 T15 2 T11 213
valid_sources[0x79] 2957 1 T6 11 T10 2 T11 157
valid_sources[0x7a] 3262 1 T6 157 T7 1 T11 147
valid_sources[0x7b] 3930 1 T2 1 T6 113 T11 161
valid_sources[0x7c] 3676 1 T2 1 T6 60 T7 4
valid_sources[0x7d] 3524 1 T6 242 T11 167 T121 1
valid_sources[0x7e] 3176 1 T1 4 T2 1 T6 70
valid_sources[0x7f] 3667 1 T6 181 T20 11 T11 207
valid_sources[0x80] 2864 1 T2 1 T6 42 T11 231



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 197125 1 T1 58 T2 30 T3 33
values[0x0] all_enables biggest_size 290804 1 T6 13278 T19 4 T20 4
values[0x1] all_enables biggest_size 290915 1 T6 13518 T19 1 T64 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%