Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3779563

1

T2

57

T4

67

T6

259

full_word

2403786

1

T2

4

T3

8

T4

13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6183059	1			T2	61		T3	8		T4	80
auto[TlIntgErrCmd]	92	1			T53	4		T54	6		T55	7
auto[TlIntgErrData]	102	1			T53	3		T54	6		T55	10
auto[TlIntgErrBoth]	96	1			T53	3		T54	8		T55	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

981030

1

T2

61

T3

8

T4

80

auto[1]

5202319

1

T7

405384

T11

291389

T12

111040

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	413499	1			T2	57		T4	67		T6	259
auto[TlIntgErrNone]	partial	auto[1]	3365799	1			T7	263369		T11	191547		T12	71489
auto[TlIntgErrNone]	full_word	auto[0]	567392	1			T2	4		T3	8		T4	13
auto[TlIntgErrNone]	full_word	auto[1]	1836369	1			T7	142015		T11	99842		T12	39551
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T53	2		T54	2		T55	4
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T53	2		T54	4		T55	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T55	1		T102	1		T111	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T107	1		T112	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1			T53	3		T54	3		T55	4
auto[TlIntgErrData]	partial	auto[1]	41	1			T54	2		T55	6		T102	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T54	1		T113	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T103	1		T107	1		T114	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T54	5		T55	2		T102	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T53	2		T54	2		T55	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T112	1		T110	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T53	1		T54	1		T102	2