Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	77566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1987135

1

T2

16

T3

8

T5

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	536219	1			T2	170		T3	69		T5	212
values[0x0]	749348	1			T16	48029		T17	58665		T18	26027
values[0x1]	779134	1			T16	49360		T17	61384		T18	27030

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2023975

1

T2

102

T3

47

T5

127

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7876	1			T48	1		T16	505		T63	1
valid_sources[0x01]	8252	1			T3	3		T5	4		T7	1
valid_sources[0x02]	7896	1			T6	3		T47	43		T48	1
valid_sources[0x03]	7434	1			T7	1		T16	518		T65	1
valid_sources[0x04]	8340	1			T5	7		T20	1		T21	6
valid_sources[0x05]	9011	1			T5	7		T6	4		T21	1
valid_sources[0x06]	7761	1			T6	1		T8	3		T10	1
valid_sources[0x07]	8005	1			T3	1		T8	2		T20	3
valid_sources[0x08]	7643	1			T7	2		T8	1		T20	1
valid_sources[0x09]	8248	1			T21	1		T16	528		T34	3
valid_sources[0x0a]	7832	1			T5	3		T6	4		T8	1
valid_sources[0x0b]	8285	1			T6	1		T8	1		T20	3
valid_sources[0x0c]	7714	1			T5	2		T6	3		T10	1
valid_sources[0x0d]	8138	1			T20	1		T16	506		T66	1
valid_sources[0x0e]	8516	1			T8	1		T10	1		T21	1
valid_sources[0x0f]	7544	1			T2	13		T5	1		T6	1
valid_sources[0x10]	8051	1			T10	1		T20	1		T21	2
valid_sources[0x11]	8409	1			T20	1		T22	1		T48	1
valid_sources[0x12]	7489	1			T10	1		T21	3		T48	1
valid_sources[0x13]	7786	1			T5	1		T6	2		T22	1
valid_sources[0x14]	8276	1			T5	3		T6	1		T7	2
valid_sources[0x15]	8713	1			T3	1		T20	5		T48	1
valid_sources[0x16]	7894	1			T8	1		T21	1		T49	1
valid_sources[0x17]	7845	1			T5	2		T21	2		T49	6
valid_sources[0x18]	7707	1			T3	1		T20	2		T21	2
valid_sources[0x19]	7703	1			T21	1		T49	1		T116	1
valid_sources[0x1a]	7638	1			T7	1		T8	2		T20	2
valid_sources[0x1b]	7908	1			T5	3		T6	2		T10	1
valid_sources[0x1c]	8271	1			T6	2		T20	1		T21	3
valid_sources[0x1d]	8008	1			T20	1		T21	1		T16	480
valid_sources[0x1e]	7989	1			T5	1		T7	3		T8	2
valid_sources[0x1f]	7550	1			T7	5		T20	1		T21	3
valid_sources[0x20]	8126	1			T20	2		T48	1		T70	2
valid_sources[0x21]	7796	1			T6	1		T7	3		T8	2
valid_sources[0x22]	9081	1			T2	5		T6	1		T20	1
valid_sources[0x23]	8419	1			T3	1		T5	3		T21	2
valid_sources[0x24]	8133	1			T3	6		T7	1		T10	1
valid_sources[0x25]	8007	1			T6	2		T10	1		T20	1
valid_sources[0x26]	8111	1			T16	532		T66	1		T34	1
valid_sources[0x27]	7657	1			T7	4		T8	2		T10	1
valid_sources[0x28]	7750	1			T20	2		T16	478		T52	18
valid_sources[0x29]	7704	1			T20	2		T21	1		T116	1
valid_sources[0x2a]	8160	1			T5	1		T6	3		T8	1
valid_sources[0x2b]	9126	1			T3	1		T5	2		T21	4
valid_sources[0x2c]	7876	1			T21	1		T49	1		T70	2
valid_sources[0x2d]	8448	1			T21	2		T49	5		T16	546
valid_sources[0x2e]	7600	1			T3	1		T21	1		T16	500
valid_sources[0x2f]	7669	1			T5	2		T7	1		T20	1
valid_sources[0x30]	7824	1			T5	3		T7	1		T20	1
valid_sources[0x31]	7604	1			T3	1		T7	1		T20	1
valid_sources[0x32]	8052	1			T5	1		T6	1		T7	2
valid_sources[0x33]	8033	1			T6	3		T21	1		T16	513
valid_sources[0x34]	7916	1			T7	1		T10	1		T20	1
valid_sources[0x35]	7667	1			T6	1		T20	1		T22	1
valid_sources[0x36]	8235	1			T3	1		T6	3		T8	2
valid_sources[0x37]	7854	1			T6	2		T16	542		T66	4
valid_sources[0x38]	7851	1			T5	1		T6	1		T7	1
valid_sources[0x39]	7686	1			T6	1		T10	1		T20	1
valid_sources[0x3a]	8086	1			T8	2		T21	1		T16	509
valid_sources[0x3b]	7761	1			T5	2		T10	1		T20	2
valid_sources[0x3c]	8177	1			T10	2		T20	2		T21	1
valid_sources[0x3d]	7779	1			T5	1		T21	1		T49	1
valid_sources[0x3e]	8325	1			T3	1		T7	1		T20	2
valid_sources[0x3f]	8252	1			T2	1		T5	6		T6	2
valid_sources[0x40]	7615	1			T20	1		T21	2		T16	488
valid_sources[0x41]	8281	1			T6	4		T21	1		T48	1
valid_sources[0x42]	7784	1			T7	2		T20	1		T21	3
valid_sources[0x43]	8209	1			T20	2		T21	1		T16	518
valid_sources[0x44]	7572	1			T2	4		T6	3		T10	1
valid_sources[0x45]	7730	1			T7	1		T10	2		T20	1
valid_sources[0x46]	8546	1			T16	499		T66	1		T30	5
valid_sources[0x47]	7407	1			T6	1		T7	1		T49	4
valid_sources[0x48]	7815	1			T3	1		T5	1		T7	8
valid_sources[0x49]	8048	1			T3	2		T20	1		T21	1
valid_sources[0x4a]	7749	1			T3	2		T7	1		T70	2
valid_sources[0x4b]	7789	1			T48	1		T49	5		T70	2
valid_sources[0x4c]	8584	1			T8	2		T10	2		T20	1
valid_sources[0x4d]	7485	1			T6	1		T20	2		T21	2
valid_sources[0x4e]	8117	1			T7	1		T20	1		T21	2
valid_sources[0x4f]	8961	1			T6	2		T70	3		T116	13
valid_sources[0x50]	7613	1			T20	1		T70	1		T16	503
valid_sources[0x51]	7600	1			T6	4		T7	2		T70	1
valid_sources[0x52]	7455	1			T7	2		T10	1		T20	2
valid_sources[0x53]	7660	1			T2	9		T6	3		T20	1
valid_sources[0x54]	7911	1			T2	1		T6	1		T8	2
valid_sources[0x55]	7649	1			T2	4		T6	2		T20	2
valid_sources[0x56]	8355	1			T3	1		T20	1		T21	1
valid_sources[0x57]	8994	1			T3	1		T7	1		T49	1
valid_sources[0x58]	9625	1			T6	2		T16	491		T132	2
valid_sources[0x59]	8099	1			T20	1		T21	1		T16	522
valid_sources[0x5a]	8231	1			T5	6		T6	1		T8	3
valid_sources[0x5b]	7639	1			T5	1		T6	1		T10	1
valid_sources[0x5c]	7933	1			T6	6		T7	1		T20	2
valid_sources[0x5d]	7995	1			T5	1		T10	1		T70	1
valid_sources[0x5e]	8482	1			T2	15		T8	1		T21	1
valid_sources[0x5f]	7835	1			T5	4		T21	1		T49	6
valid_sources[0x60]	8932	1			T5	4		T6	2		T10	1
valid_sources[0x61]	8288	1			T7	1		T21	1		T48	1
valid_sources[0x62]	7708	1			T7	1		T20	1		T48	1
valid_sources[0x63]	7875	1			T7	3		T10	1		T16	510
valid_sources[0x64]	8480	1			T6	1		T7	1		T20	2
valid_sources[0x65]	7896	1			T3	1		T6	1		T21	2
valid_sources[0x66]	7546	1			T8	1		T10	1		T20	1
valid_sources[0x67]	7840	1			T3	1		T7	6		T20	2
valid_sources[0x68]	8140	1			T21	1		T70	7		T16	493
valid_sources[0x69]	9160	1			T3	3		T20	1		T21	3
valid_sources[0x6a]	7749	1			T5	8		T8	1		T10	1
valid_sources[0x6b]	8508	1			T8	2		T21	3		T48	1
valid_sources[0x6c]	7858	1			T8	1		T20	2		T21	1
valid_sources[0x6d]	7698	1			T5	1		T10	1		T20	1
valid_sources[0x6e]	8414	1			T10	2		T20	3		T21	1
valid_sources[0x6f]	8360	1			T5	1		T6	1		T7	1
valid_sources[0x70]	7721	1			T6	5		T20	2		T21	2
valid_sources[0x71]	8309	1			T7	1		T70	6		T16	493
valid_sources[0x72]	8668	1			T2	4		T5	7		T16	522
valid_sources[0x73]	8646	1			T6	1		T8	3		T20	2
valid_sources[0x74]	7897	1			T6	5		T7	1		T21	1
valid_sources[0x75]	7685	1			T7	1		T48	1		T49	4
valid_sources[0x76]	7880	1			T5	1		T6	1		T10	1
valid_sources[0x77]	8204	1			T8	1		T49	3		T16	478
valid_sources[0x78]	7876	1			T2	2		T6	2		T20	1
valid_sources[0x79]	8640	1			T6	2		T7	1		T21	2
valid_sources[0x7a]	7885	1			T3	3		T5	5		T21	2
valid_sources[0x7b]	7769	1			T6	2		T10	1		T20	1
valid_sources[0x7c]	8097	1			T6	1		T8	4		T21	2
valid_sources[0x7d]	8131	1			T6	1		T21	1		T16	519
valid_sources[0x7e]	8052	1			T6	2		T7	7		T20	2
valid_sources[0x7f]	8434	1			T7	1		T21	1		T16	519
valid_sources[0x80]	8279	1			T5	6		T20	2		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

499455

1

T2

16

T3

8

T5

17

values[0x0]

all_enables

biggest_size

742683

1

T16

47651

T17

58098

T18

25783

values[0x1]

all_enables

biggest_size

744997

1

T16

47213

T17

58721

T18

25958

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147147	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1507253

1

T1

5

T3

16

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	411073	1			T3	32		T4	1		T5	96
values[0x0]	575362	1			T1	9		T9	7		T26	7
values[0x1]	667965	1			T1	12		T9	4		T26	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64847	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1589553

1

T1

7

T3

16

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7026	1			T3	1		T5	1		T10	1
valid_sources[0x01]	7205	1			T116	1		T16	554		T17	547
valid_sources[0x02]	7143	1			T6	1		T8	1		T11	1
valid_sources[0x03]	5580	1			T5	1		T6	3		T48	2
valid_sources[0x04]	6294	1			T5	2		T8	1		T26	1
valid_sources[0x05]	5797	1			T5	1		T13	3		T116	1
valid_sources[0x06]	6551	1			T3	2		T5	2		T16	124
valid_sources[0x07]	6253	1			T70	1		T16	262		T37	1
valid_sources[0x08]	5853	1			T16	369		T133	1		T17	466
valid_sources[0x09]	6663	1			T3	1		T5	1		T6	1
valid_sources[0x0a]	6305	1			T47	2		T16	405		T133	1
valid_sources[0x0b]	6371	1			T16	554		T37	1		T134	3
valid_sources[0x0c]	6761	1			T5	1		T116	1		T16	636
valid_sources[0x0d]	5681	1			T16	231		T33	1		T39	2
valid_sources[0x0e]	7119	1			T14	32		T116	1		T16	772
valid_sources[0x0f]	6053	1			T8	1		T116	2		T16	311
valid_sources[0x10]	6453	1			T5	2		T6	2		T26	1
valid_sources[0x11]	8490	1			T6	1		T116	1		T16	776
valid_sources[0x12]	6894	1			T116	2		T16	1029		T17	428
valid_sources[0x13]	7058	1			T5	1		T6	2		T70	2
valid_sources[0x14]	5963	1			T116	1		T16	70		T33	2
valid_sources[0x15]	6830	1			T6	1		T26	3		T16	98
valid_sources[0x16]	5641	1			T8	1		T70	1		T116	2
valid_sources[0x17]	6044	1			T6	2		T16	825		T135	4
valid_sources[0x18]	6265	1			T47	2		T16	446		T62	1
valid_sources[0x19]	5112	1			T8	1		T70	3		T16	345
valid_sources[0x1a]	6653	1			T3	1		T5	1		T10	2
valid_sources[0x1b]	6777	1			T6	1		T10	1		T16	127
valid_sources[0x1c]	6755	1			T3	1		T5	3		T16	451
valid_sources[0x1d]	6735	1			T5	1		T6	1		T8	1
valid_sources[0x1e]	6514	1			T3	1		T16	233		T17	233
valid_sources[0x1f]	5696	1			T16	70		T33	1		T135	6
valid_sources[0x20]	6816	1			T116	1		T16	725		T17	55
valid_sources[0x21]	6517	1			T16	254		T37	2		T17	75
valid_sources[0x22]	6570	1			T70	9		T16	401		T64	2
valid_sources[0x23]	7456	1			T16	250		T17	706		T18	504
valid_sources[0x24]	6441	1			T16	200		T133	1		T17	239
valid_sources[0x25]	5285	1			T1	21		T10	1		T16	455
valid_sources[0x26]	6012	1			T47	1		T70	2		T116	1
valid_sources[0x27]	6945	1			T47	1		T48	1		T16	199
valid_sources[0x28]	7625	1			T5	1		T116	3		T16	1110
valid_sources[0x29]	5841	1			T16	689		T133	1		T17	424
valid_sources[0x2a]	6713	1			T48	2		T16	995		T133	1
valid_sources[0x2b]	5599	1			T5	1		T70	1		T16	246
valid_sources[0x2c]	5343	1			T8	1		T12	2		T48	1
valid_sources[0x2d]	6974	1			T6	1		T70	5		T116	1
valid_sources[0x2e]	6182	1			T5	1		T116	1		T16	850
valid_sources[0x2f]	6391	1			T48	1		T16	840		T133	1
valid_sources[0x30]	5298	1			T116	1		T16	111		T17	285
valid_sources[0x31]	6488	1			T5	1		T6	2		T116	2
valid_sources[0x32]	6009	1			T116	1		T16	286		T64	2
valid_sources[0x33]	7172	1			T8	1		T46	7		T16	578
valid_sources[0x34]	6002	1			T13	4		T16	328		T136	2
valid_sources[0x35]	6647	1			T5	2		T26	2		T16	472
valid_sources[0x36]	5935	1			T116	1		T16	98		T33	6
valid_sources[0x37]	6259	1			T116	1		T16	40		T135	1
valid_sources[0x38]	6170	1			T16	455		T36	1		T37	1
valid_sources[0x39]	5471	1			T5	1		T70	1		T16	207
valid_sources[0x3a]	6713	1			T5	1		T8	3		T16	640
valid_sources[0x3b]	6843	1			T6	1		T8	1		T16	781
valid_sources[0x3c]	6191	1			T5	1		T46	3		T116	1
valid_sources[0x3d]	7061	1			T6	1		T116	1		T16	171
valid_sources[0x3e]	7173	1			T5	1		T16	306		T77	10
valid_sources[0x3f]	6817	1			T5	1		T16	340		T137	1
valid_sources[0x40]	6853	1			T116	1		T16	424		T36	1
valid_sources[0x41]	7975	1			T5	1		T6	2		T16	1019
valid_sources[0x42]	6416	1			T16	728		T136	1		T133	1
valid_sources[0x43]	6426	1			T5	1		T6	1		T8	1
valid_sources[0x44]	6424	1			T3	1		T6	2		T116	1
valid_sources[0x45]	6432	1			T16	592		T39	1		T133	1
valid_sources[0x46]	6889	1			T8	1		T116	1		T16	420
valid_sources[0x47]	7210	1			T12	1		T16	245		T17	230
valid_sources[0x48]	7351	1			T6	1		T70	2		T16	568
valid_sources[0x49]	7222	1			T5	1		T8	1		T10	1
valid_sources[0x4a]	5751	1			T5	1		T6	1		T47	1
valid_sources[0x4b]	6544	1			T3	1		T5	1		T6	2
valid_sources[0x4c]	6406	1			T116	2		T16	502		T64	1
valid_sources[0x4d]	6376	1			T26	3		T16	40		T17	513
valid_sources[0x4e]	6548	1			T8	2		T116	1		T16	164
valid_sources[0x4f]	7815	1			T6	1		T16	553		T33	3
valid_sources[0x50]	6837	1			T6	3		T8	1		T116	1
valid_sources[0x51]	5689	1			T5	2		T6	2		T12	1
valid_sources[0x52]	5190	1			T47	1		T116	1		T16	113
valid_sources[0x53]	7115	1			T6	2		T48	1		T116	1
valid_sources[0x54]	5374	1			T16	108		T64	3		T33	1
valid_sources[0x55]	5970	1			T70	3		T16	84		T137	1
valid_sources[0x56]	6113	1			T8	1		T47	1		T116	1
valid_sources[0x57]	5632	1			T5	1		T6	1		T70	7
valid_sources[0x58]	6552	1			T3	2		T5	1		T116	1
valid_sources[0x59]	5808	1			T8	1		T10	1		T22	23
valid_sources[0x5a]	6834	1			T5	2		T16	17		T137	2
valid_sources[0x5b]	5864	1			T12	1		T16	163		T133	1
valid_sources[0x5c]	5982	1			T3	1		T116	2		T16	328
valid_sources[0x5d]	7027	1			T6	2		T12	1		T16	853
valid_sources[0x5e]	6440	1			T5	2		T16	369		T17	668
valid_sources[0x5f]	6048	1			T6	1		T8	3		T16	63
valid_sources[0x60]	5655	1			T16	217		T17	480		T18	289
valid_sources[0x61]	5678	1			T48	2		T16	135		T36	1
valid_sources[0x62]	6228	1			T5	1		T8	1		T16	368
valid_sources[0x63]	5630	1			T5	1		T8	2		T47	1
valid_sources[0x64]	7029	1			T5	1		T8	1		T13	3
valid_sources[0x65]	4891	1			T70	3		T16	237		T37	1
valid_sources[0x66]	7698	1			T5	1		T6	1		T10	1
valid_sources[0x67]	6567	1			T5	1		T6	4		T8	1
valid_sources[0x68]	6864	1			T3	1		T47	1		T16	362
valid_sources[0x69]	6961	1			T5	1		T6	3		T15	1
valid_sources[0x6a]	6753	1			T5	1		T8	1		T16	272
valid_sources[0x6b]	7100	1			T116	1		T16	478		T136	1
valid_sources[0x6c]	7013	1			T3	1		T6	1		T47	1
valid_sources[0x6d]	8082	1			T8	2		T116	1		T16	116
valid_sources[0x6e]	6750	1			T16	365		T36	1		T17	933
valid_sources[0x6f]	7221	1			T16	432		T64	2		T17	648
valid_sources[0x70]	6819	1			T5	1		T116	1		T16	1076
valid_sources[0x71]	6753	1			T10	2		T16	230		T17	257
valid_sources[0x72]	6420	1			T26	1		T70	2		T16	311
valid_sources[0x73]	6098	1			T47	1		T116	1		T16	694
valid_sources[0x74]	6085	1			T6	1		T7	64		T10	4
valid_sources[0x75]	6547	1			T5	1		T8	1		T48	1
valid_sources[0x76]	6053	1			T5	1		T6	1		T48	1
valid_sources[0x77]	6748	1			T5	1		T48	1		T16	497
valid_sources[0x78]	6436	1			T116	3		T16	287		T17	543
valid_sources[0x79]	5675	1			T5	1		T13	4		T16	327
valid_sources[0x7a]	6535	1			T16	291		T133	1		T17	466
valid_sources[0x7b]	6567	1			T5	1		T8	1		T116	1
valid_sources[0x7c]	6816	1			T116	1		T16	554		T17	852
valid_sources[0x7d]	6228	1			T3	1		T16	88		T36	1
valid_sources[0x7e]	6438	1			T8	3		T16	131		T36	1
valid_sources[0x7f]	5963	1			T13	1		T116	1		T16	453
valid_sources[0x80]	6879	1			T3	1		T5	1		T48	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

379796

1

T3

16

T4

1

T5

45

values[0x0]

all_enables

biggest_size

563823

1

T1

3

T9

3

T26

4

values[0x1]

all_enables

biggest_size

563634

1

T1

2

T26

1

T74

1