Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3629342

1

T2

154

T3

61

T5

195

full_word

2319060

1

T2

16

T3

8

T5

17

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5948132	1			T2	170		T3	69		T5	212
auto[TlIntgErrCmd]	96	1			T67	3		T68	5		T69	7
auto[TlIntgErrData]	84	1			T67	4		T68	3		T69	6
auto[TlIntgErrBoth]	90	1			T67	3		T68	2		T69	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

938385

1

T2

170

T3

69

T5

212

auto[1]

5010017

1

T16

314468

T17

391853

T18

168181

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	390732	1			T2	154		T3	61		T5	195
auto[TlIntgErrNone]	partial	auto[1]	3238361	1			T16	202171		T17	252717		T18	107035
auto[TlIntgErrNone]	full_word	auto[0]	547537	1			T2	16		T3	8		T5	17
auto[TlIntgErrNone]	full_word	auto[1]	1771502	1			T16	112297		T17	139136		T18	61146
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T68	2		T69	2		T119	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T67	3		T68	3		T69	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T125	1		T126	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T69	1		T125	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T67	2		T68	1		T69	4
auto[TlIntgErrData]	partial	auto[1]	41	1			T67	2		T68	2		T69	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T127	1		T128	1		T129	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T130	1		T129	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T67	2		T69	2		T123	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T67	1		T68	2		T69	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T69	1		T129	1		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T120	1		-	-		-	-