Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2244727

1

T6

250

T7

72

T8

69

full_word

1410808

1

T4

2

T6

20

T7

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3655235	1			T4	2		T6	270		T7	80
auto[TlIntgErrCmd]	99	1			T54	8		T55	5		T56	8
auto[TlIntgErrData]	117	1			T54	5		T55	3		T56	8
auto[TlIntgErrBoth]	84	1			T54	7		T55	2		T56	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

588434

1

T4

2

T6

270

T7

80

auto[1]

3067101

1

T14

87197

T11

229919

T23

142851

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	254896	1			T6	250		T7	72		T8	69
auto[TlIntgErrNone]	partial	auto[1]	1989552	1			T14	56490		T11	150487		T23	91629
auto[TlIntgErrNone]	full_word	auto[0]	333410	1			T4	2		T6	20		T7	8
auto[TlIntgErrNone]	full_word	auto[1]	1077377	1			T14	30707		T11	79432		T23	51222
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T54	2		T55	1		T56	6
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T54	6		T55	3		T56	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T117	1		T118	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T55	1		T56	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T54	1		T55	1		T56	4
auto[TlIntgErrData]	partial	auto[1]	57	1			T54	4		T55	2		T56	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T113	1		T116	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T112	2		T111	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T54	3		T112	2		T111	3
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T54	4		T55	2		T56	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T111	1		T115	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T56	1		T120	1		-	-