Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4320210

1

T3

178

T7

92077

T9

50

full_word

2761130

1

T3

24

T4

4

T7

57385

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7081030	1			T3	202		T4	4		T7	149462
auto[TlIntgErrCmd]	97	1			T49	4		T50	8		T51	2
auto[TlIntgErrData]	97	1			T49	2		T50	4		T51	5
auto[TlIntgErrBoth]	116	1			T49	4		T50	8		T51	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1117093

1

T3

202

T4

4

T7

23171

auto[1]

5964247

1

T7

126291

T12

30601

T14

126969

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	464188	1			T3	178		T7	9555		T9	50
auto[TlIntgErrNone]	partial	auto[1]	3855728	1			T7	82522		T12	19423		T14	82843
auto[TlIntgErrNone]	full_word	auto[0]	652775	1			T3	24		T4	4		T7	13616
auto[TlIntgErrNone]	full_word	auto[1]	2108339	1			T7	43769		T12	11178		T14	44126
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T49	3		T50	4		T116	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T49	1		T50	4		T51	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T117	1		T118	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T120	2		T121	1		T122	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T49	2		T50	1		T51	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T50	2		T51	1		T116	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T51	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T50	1		T123	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T49	2		T50	4		T51	1
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T49	2		T50	3		T51	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T50	1		T51	1		T117	1