Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	94758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2385231

1

T1

155860

T2

17

T4

17375

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	645555	1			T1	39372		T2	171		T4	4930
values[0x0]	901420	1			T1	58925		T4	6538		T11	4401
values[0x1]	933014	1			T1	61240		T4	6789		T11	4549

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49194	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2430795

1

T1

157480

T2

98

T4

17830

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9115	1			T1	608		T4	66		T5	1
valid_sources[0x01]	9792	1			T1	655		T4	61		T15	2
valid_sources[0x02]	9552	1			T1	692		T4	91		T5	1
valid_sources[0x03]	9651	1			T1	606		T2	7		T4	91
valid_sources[0x04]	9315	1			T1	598		T4	66		T5	1
valid_sources[0x05]	9617	1			T1	641		T4	58		T17	1
valid_sources[0x06]	9143	1			T1	595		T2	11		T4	75
valid_sources[0x07]	9781	1			T1	625		T4	65		T5	1
valid_sources[0x08]	9394	1			T1	590		T4	68		T11	57
valid_sources[0x09]	9517	1			T1	649		T4	59		T11	21
valid_sources[0x0a]	9211	1			T1	615		T4	64		T10	1
valid_sources[0x0b]	10076	1			T1	632		T4	71		T5	1
valid_sources[0x0c]	9774	1			T1	668		T2	1		T4	69
valid_sources[0x0d]	10473	1			T1	674		T4	66		T5	1
valid_sources[0x0e]	10346	1			T1	661		T4	63		T5	2
valid_sources[0x0f]	10457	1			T1	638		T4	78		T17	1
valid_sources[0x10]	9775	1			T1	556		T4	65		T5	2
valid_sources[0x11]	9428	1			T1	634		T2	1		T4	65
valid_sources[0x12]	9716	1			T1	637		T2	10		T4	77
valid_sources[0x13]	9207	1			T1	607		T2	3		T4	65
valid_sources[0x14]	9567	1			T1	521		T4	76		T5	2
valid_sources[0x15]	9236	1			T1	679		T4	78		T5	4
valid_sources[0x16]	10600	1			T1	603		T4	63		T11	46
valid_sources[0x17]	9310	1			T1	595		T4	76		T11	48
valid_sources[0x18]	10240	1			T1	653		T4	68		T5	2
valid_sources[0x19]	9466	1			T1	596		T4	88		T5	1
valid_sources[0x1a]	9706	1			T1	686		T4	67		T17	1
valid_sources[0x1b]	9356	1			T1	670		T4	70		T5	2
valid_sources[0x1c]	10069	1			T1	672		T4	60		T11	45
valid_sources[0x1d]	9501	1			T1	584		T4	54		T5	1
valid_sources[0x1e]	9423	1			T1	638		T4	66		T5	1
valid_sources[0x1f]	10873	1			T1	614		T4	75		T5	2
valid_sources[0x20]	9332	1			T1	664		T4	74		T11	22
valid_sources[0x21]	10521	1			T1	594		T4	63		T5	1
valid_sources[0x22]	9453	1			T1	635		T4	96		T10	1
valid_sources[0x23]	9736	1			T1	586		T2	6		T4	53
valid_sources[0x24]	10297	1			T1	635		T4	55		T5	1
valid_sources[0x25]	10346	1			T1	654		T4	68		T11	65
valid_sources[0x26]	10916	1			T1	670		T4	81		T11	59
valid_sources[0x27]	9957	1			T1	602		T2	2		T4	65
valid_sources[0x28]	9917	1			T1	564		T4	66		T10	2
valid_sources[0x29]	9992	1			T1	560		T4	55		T11	58
valid_sources[0x2a]	9687	1			T1	612		T4	67		T11	48
valid_sources[0x2b]	9647	1			T1	562		T4	56		T5	1
valid_sources[0x2c]	9550	1			T1	596		T4	57		T5	2
valid_sources[0x2d]	9233	1			T1	607		T4	78		T11	44
valid_sources[0x2e]	11616	1			T1	622		T4	79		T5	3
valid_sources[0x2f]	9512	1			T1	666		T2	5		T4	75
valid_sources[0x30]	10108	1			T1	682		T4	83		T10	2
valid_sources[0x31]	9302	1			T1	661		T2	3		T4	82
valid_sources[0x32]	9067	1			T1	609		T4	40		T15	1
valid_sources[0x33]	9571	1			T1	599		T2	5		T4	51
valid_sources[0x34]	10286	1			T1	562		T4	81		T15	2
valid_sources[0x35]	9232	1			T1	683		T4	93		T5	1
valid_sources[0x36]	9658	1			T1	606		T4	58		T5	4
valid_sources[0x37]	10340	1			T1	573		T4	58		T5	2
valid_sources[0x38]	9738	1			T1	678		T4	62		T5	2
valid_sources[0x39]	9840	1			T1	554		T4	57		T11	49
valid_sources[0x3a]	9861	1			T1	651		T4	88		T5	2
valid_sources[0x3b]	10504	1			T1	690		T4	72		T10	1
valid_sources[0x3c]	9033	1			T1	647		T4	79		T10	1
valid_sources[0x3d]	9702	1			T1	615		T2	1		T4	80
valid_sources[0x3e]	9811	1			T1	696		T4	65		T10	1
valid_sources[0x3f]	11620	1			T1	596		T4	64		T10	1
valid_sources[0x40]	9649	1			T1	642		T2	14		T4	67
valid_sources[0x41]	9519	1			T1	622		T4	72		T15	3
valid_sources[0x42]	9532	1			T1	683		T4	66		T5	1
valid_sources[0x43]	9489	1			T1	607		T4	83		T5	2
valid_sources[0x44]	9137	1			T1	631		T4	74		T5	3
valid_sources[0x45]	9393	1			T1	584		T4	75		T5	1
valid_sources[0x46]	9646	1			T1	649		T4	62		T5	2
valid_sources[0x47]	9035	1			T1	635		T4	71		T5	1
valid_sources[0x48]	9885	1			T1	752		T4	67		T11	57
valid_sources[0x49]	9320	1			T1	639		T4	78		T11	23
valid_sources[0x4a]	9654	1			T1	601		T4	81		T11	40
valid_sources[0x4b]	9060	1			T1	642		T4	66		T5	2
valid_sources[0x4c]	9208	1			T1	597		T4	79		T5	2
valid_sources[0x4d]	10514	1			T1	636		T4	58		T5	4
valid_sources[0x4e]	10152	1			T1	607		T4	68		T5	1
valid_sources[0x4f]	10083	1			T1	655		T4	70		T5	1
valid_sources[0x50]	9186	1			T1	603		T2	8		T4	66
valid_sources[0x51]	10478	1			T1	616		T4	77		T5	1
valid_sources[0x52]	9309	1			T1	626		T4	64		T10	2
valid_sources[0x53]	9351	1			T1	655		T4	98		T15	4
valid_sources[0x54]	9836	1			T1	633		T4	83		T5	1
valid_sources[0x55]	9991	1			T1	583		T4	71		T10	2
valid_sources[0x56]	9775	1			T1	662		T4	48		T5	3
valid_sources[0x57]	10222	1			T1	613		T4	79		T5	2
valid_sources[0x58]	11123	1			T1	657		T4	75		T11	54
valid_sources[0x59]	10466	1			T1	650		T4	77		T5	1
valid_sources[0x5a]	9703	1			T1	694		T4	70		T10	1
valid_sources[0x5b]	9290	1			T1	648		T4	57		T10	1
valid_sources[0x5c]	9697	1			T1	544		T2	5		T4	79
valid_sources[0x5d]	9724	1			T1	599		T4	76		T5	1
valid_sources[0x5e]	9620	1			T1	677		T4	78		T5	1
valid_sources[0x5f]	9480	1			T1	627		T2	15		T4	73
valid_sources[0x60]	9236	1			T1	612		T4	81		T11	53
valid_sources[0x61]	10358	1			T1	627		T2	6		T4	56
valid_sources[0x62]	9801	1			T1	587		T4	63		T10	1
valid_sources[0x63]	9167	1			T1	644		T4	77		T5	2
valid_sources[0x64]	10091	1			T1	695		T4	71		T5	1
valid_sources[0x65]	9471	1			T1	616		T4	92		T5	2
valid_sources[0x66]	9360	1			T1	571		T4	79		T11	49
valid_sources[0x67]	9978	1			T1	562		T4	63		T5	1
valid_sources[0x68]	9544	1			T1	625		T4	65		T5	2
valid_sources[0x69]	9919	1			T1	594		T4	59		T10	2
valid_sources[0x6a]	10099	1			T1	614		T4	69		T11	51
valid_sources[0x6b]	9528	1			T1	626		T4	87		T5	2
valid_sources[0x6c]	9350	1			T1	602		T4	68		T11	27
valid_sources[0x6d]	9652	1			T1	602		T4	68		T10	1
valid_sources[0x6e]	9262	1			T1	617		T4	72		T5	3
valid_sources[0x6f]	9696	1			T1	599		T4	73		T5	1
valid_sources[0x70]	9749	1			T1	795		T4	78		T5	1
valid_sources[0x71]	9468	1			T1	649		T4	54		T5	1
valid_sources[0x72]	9559	1			T1	574		T4	76		T5	4
valid_sources[0x73]	9609	1			T1	648		T4	75		T5	2
valid_sources[0x74]	10121	1			T1	617		T4	50		T11	41
valid_sources[0x75]	9933	1			T1	551		T4	82		T11	73
valid_sources[0x76]	10801	1			T1	581		T4	63		T5	3
valid_sources[0x77]	9456	1			T1	612		T4	77		T10	1
valid_sources[0x78]	9707	1			T1	658		T4	75		T11	4
valid_sources[0x79]	9397	1			T1	686		T4	83		T11	49
valid_sources[0x7a]	9505	1			T1	585		T4	64		T5	2
valid_sources[0x7b]	9458	1			T1	640		T4	60		T5	2
valid_sources[0x7c]	9409	1			T1	666		T4	74		T11	73
valid_sources[0x7d]	9568	1			T1	585		T4	59		T5	1
valid_sources[0x7e]	9921	1			T1	595		T4	71		T5	1
valid_sources[0x7f]	9116	1			T1	554		T4	67		T5	6
valid_sources[0x80]	9600	1			T1	573		T4	46		T11	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

599427

1

T1

38833

T2

17

T4

4406

values[0x0]

all_enables

biggest_size

893728

1

T1

58443

T4

6488

T11

4364

values[0x1]

all_enables

biggest_size

892076

1

T1

58584

T4

6481

T11

4373

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	176708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1812615

1

T1

117516

T2

35

T4

13445

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	496829	1			T1	31115		T2	64		T4	3811
values[0x0]	690805	1			T1	44972		T3	8		T4	4986
values[0x1]	801689	1			T1	52447		T3	8		T4	5913

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	78640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1910683

1

T1

123939

T2

44

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8064	1			T1	606		T11	35		T18	1
valid_sources[0x01]	7846	1			T1	502		T11	19		T19	123
valid_sources[0x02]	7346	1			T1	452		T4	5		T11	59
valid_sources[0x03]	6912	1			T1	640		T11	32		T19	100
valid_sources[0x04]	8219	1			T1	611		T11	30		T18	1
valid_sources[0x05]	8050	1			T1	467		T11	27		T19	110
valid_sources[0x06]	7663	1			T1	501		T11	29		T19	113
valid_sources[0x07]	7460	1			T1	499		T4	3		T11	24
valid_sources[0x08]	7389	1			T1	480		T4	199		T11	21
valid_sources[0x09]	8278	1			T1	452		T11	34		T19	112
valid_sources[0x0a]	7254	1			T1	440		T11	62		T19	125
valid_sources[0x0b]	7662	1			T1	616		T11	48		T19	122
valid_sources[0x0c]	7964	1			T1	559		T4	5		T17	2
valid_sources[0x0d]	7364	1			T1	507		T11	56		T19	124
valid_sources[0x0e]	7819	1			T1	565		T11	57		T19	125
valid_sources[0x0f]	8014	1			T1	536		T11	42		T19	121
valid_sources[0x10]	7691	1			T1	526		T11	34		T18	1
valid_sources[0x11]	7348	1			T1	412		T4	77		T11	38
valid_sources[0x12]	8010	1			T1	513		T11	22		T19	117
valid_sources[0x13]	8427	1			T1	534		T11	26		T19	111
valid_sources[0x14]	8417	1			T1	474		T4	246		T11	38
valid_sources[0x15]	8323	1			T1	502		T11	31		T19	149
valid_sources[0x16]	8232	1			T1	510		T4	49		T11	17
valid_sources[0x17]	8024	1			T1	471		T11	26		T19	136
valid_sources[0x18]	7593	1			T1	407		T4	2		T11	44
valid_sources[0x19]	7525	1			T1	487		T4	128		T11	45
valid_sources[0x1a]	8412	1			T1	499		T4	135		T11	44
valid_sources[0x1b]	7461	1			T1	461		T4	4		T11	48
valid_sources[0x1c]	7458	1			T1	587		T11	27		T19	122
valid_sources[0x1d]	6622	1			T1	420		T4	2		T11	23
valid_sources[0x1e]	7939	1			T1	421		T4	132		T11	24
valid_sources[0x1f]	7533	1			T1	518		T11	45		T19	131
valid_sources[0x20]	8553	1			T1	514		T4	114		T11	75
valid_sources[0x21]	8668	1			T1	461		T4	164		T5	96
valid_sources[0x22]	7638	1			T1	469		T4	3		T11	27
valid_sources[0x23]	7580	1			T1	518		T11	55		T19	134
valid_sources[0x24]	7164	1			T1	447		T4	148		T11	33
valid_sources[0x25]	7352	1			T1	524		T11	48		T18	1
valid_sources[0x26]	6801	1			T1	550		T11	43		T18	1
valid_sources[0x27]	7352	1			T1	431		T4	156		T11	40
valid_sources[0x28]	8688	1			T1	493		T4	343		T11	44
valid_sources[0x29]	7966	1			T1	514		T11	27		T19	94
valid_sources[0x2a]	7105	1			T1	488		T4	149		T11	36
valid_sources[0x2b]	7562	1			T1	491		T4	115		T11	60
valid_sources[0x2c]	7425	1			T1	608		T11	29		T19	136
valid_sources[0x2d]	8616	1			T1	511		T4	28		T17	2
valid_sources[0x2e]	8650	1			T1	503		T11	44		T19	131
valid_sources[0x2f]	7633	1			T1	550		T11	25		T19	127
valid_sources[0x30]	8070	1			T1	439		T11	26		T19	125
valid_sources[0x31]	7413	1			T1	520		T4	94		T11	30
valid_sources[0x32]	8525	1			T1	435		T11	42		T19	117
valid_sources[0x33]	7938	1			T1	506		T4	266		T11	33
valid_sources[0x34]	7956	1			T1	458		T11	31		T19	123
valid_sources[0x35]	7209	1			T1	507		T11	31		T19	105
valid_sources[0x36]	7700	1			T1	440		T11	31		T19	78
valid_sources[0x37]	7442	1			T1	569		T4	73		T11	34
valid_sources[0x38]	7479	1			T1	466		T11	26		T19	90
valid_sources[0x39]	7985	1			T1	606		T11	27		T19	136
valid_sources[0x3a]	8549	1			T1	577		T4	148		T11	56
valid_sources[0x3b]	7855	1			T1	577		T11	26		T19	120
valid_sources[0x3c]	7672	1			T1	545		T11	39		T19	114
valid_sources[0x3d]	7323	1			T1	466		T4	7		T11	30
valid_sources[0x3e]	7476	1			T1	435		T11	22		T19	133
valid_sources[0x3f]	7999	1			T1	533		T11	23		T19	112
valid_sources[0x40]	8132	1			T1	498		T11	24		T19	128
valid_sources[0x41]	7354	1			T1	499		T15	96		T11	54
valid_sources[0x42]	7739	1			T1	526		T11	27		T18	3
valid_sources[0x43]	8118	1			T1	470		T11	34		T19	136
valid_sources[0x44]	7589	1			T1	446		T4	61		T11	25
valid_sources[0x45]	7977	1			T1	586		T10	16		T11	39
valid_sources[0x46]	7418	1			T1	482		T11	30		T19	124
valid_sources[0x47]	8282	1			T1	438		T4	201		T11	27
valid_sources[0x48]	8464	1			T1	548		T11	38		T18	1
valid_sources[0x49]	7260	1			T1	480		T11	30		T19	111
valid_sources[0x4a]	8084	1			T1	496		T4	163		T11	32
valid_sources[0x4b]	7980	1			T1	577		T4	30		T11	66
valid_sources[0x4c]	7693	1			T1	529		T4	4		T11	30
valid_sources[0x4d]	8211	1			T1	542		T4	335		T11	39
valid_sources[0x4e]	7313	1			T1	507		T11	43		T19	119
valid_sources[0x4f]	7646	1			T1	402		T11	42		T19	145
valid_sources[0x50]	7624	1			T1	422		T4	15		T11	25
valid_sources[0x51]	7418	1			T1	465		T11	16		T19	123
valid_sources[0x52]	8246	1			T1	595		T11	47		T19	127
valid_sources[0x53]	7904	1			T1	431		T11	17		T19	118
valid_sources[0x54]	6845	1			T1	406		T4	52		T11	41
valid_sources[0x55]	7502	1			T1	466		T4	188		T11	53
valid_sources[0x56]	8721	1			T1	522		T4	141		T11	61
valid_sources[0x57]	7792	1			T1	501		T4	7		T7	2
valid_sources[0x58]	7653	1			T1	461		T4	104		T11	48
valid_sources[0x59]	7736	1			T1	558		T4	125		T11	24
valid_sources[0x5a]	7749	1			T1	449		T11	35		T19	120
valid_sources[0x5b]	8425	1			T1	512		T4	75		T11	38
valid_sources[0x5c]	7972	1			T1	562		T4	28		T11	29
valid_sources[0x5d]	7517	1			T1	465		T4	34		T11	45
valid_sources[0x5e]	8659	1			T1	491		T4	3		T9	1
valid_sources[0x5f]	7994	1			T1	463		T11	32		T19	125
valid_sources[0x60]	7558	1			T1	670		T11	36		T19	127
valid_sources[0x61]	7621	1			T1	573		T11	35		T19	112
valid_sources[0x62]	6804	1			T1	562		T11	18		T19	95
valid_sources[0x63]	7328	1			T1	468		T4	212		T11	55
valid_sources[0x64]	8067	1			T1	462		T4	282		T11	19
valid_sources[0x65]	8842	1			T1	451		T4	2		T11	9
valid_sources[0x66]	7228	1			T1	414		T4	6		T11	37
valid_sources[0x67]	7426	1			T1	544		T11	25		T19	127
valid_sources[0x68]	7808	1			T1	568		T11	62		T19	127
valid_sources[0x69]	7568	1			T1	532		T4	1		T11	47
valid_sources[0x6a]	7480	1			T1	482		T4	296		T11	16
valid_sources[0x6b]	7685	1			T1	469		T4	104		T11	46
valid_sources[0x6c]	7863	1			T1	538		T4	434		T11	11
valid_sources[0x6d]	7953	1			T1	539		T4	112		T11	53
valid_sources[0x6e]	8022	1			T1	511		T4	268		T11	25
valid_sources[0x6f]	7622	1			T1	504		T4	3		T11	26
valid_sources[0x70]	7660	1			T1	553		T11	29		T19	128
valid_sources[0x71]	7298	1			T1	478		T11	37		T19	126
valid_sources[0x72]	7587	1			T1	415		T11	21		T19	114
valid_sources[0x73]	7635	1			T1	487		T7	4		T11	20
valid_sources[0x74]	7680	1			T1	525		T4	256		T11	51
valid_sources[0x75]	8980	1			T1	518		T4	212		T11	64
valid_sources[0x76]	7994	1			T1	504		T11	38		T19	111
valid_sources[0x77]	8198	1			T1	447		T11	42		T19	142
valid_sources[0x78]	8426	1			T1	394		T11	31		T19	136
valid_sources[0x79]	7691	1			T1	503		T11	47		T19	110
valid_sources[0x7a]	7407	1			T1	559		T4	237		T11	48
valid_sources[0x7b]	8307	1			T1	531		T4	144		T11	29
valid_sources[0x7c]	7507	1			T1	507		T11	23		T19	106
valid_sources[0x7d]	8095	1			T1	540		T4	37		T11	16
valid_sources[0x7e]	7599	1			T1	394		T4	3		T11	49
valid_sources[0x7f]	7789	1			T1	384		T11	57		T19	141
valid_sources[0x80]	7931	1			T1	520		T4	5		T11	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

458307

1

T1

29275

T2

35

T4

3477

values[0x0]

all_enables

biggest_size

676660

1

T1

44091

T4

4902

T6

2

values[0x1]

all_enables

biggest_size

677648

1

T1

44150

T4

5066

T7

1