Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4382703

1

T1

277998

T2

154

T4

31986

full_word

2785549

1

T1

181203

T2

17

T4

20354

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7167922	1			T1	459201		T2	171		T4	52340
auto[TlIntgErrCmd]	110	1			T56	9		T57	8		T58	8
auto[TlIntgErrData]	117	1			T56	6		T57	8		T58	6
auto[TlIntgErrBoth]	103	1			T56	5		T57	4		T58	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133359

1

T1

69989

T2

171

T4

8354

auto[1]

6034893

1

T1

389212

T4

43986

T11

29062

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	475409	1			T1	27575		T2	154		T4	3530
auto[TlIntgErrNone]	partial	auto[1]	3907003	1			T1	250423		T4	28456		T11	18680
auto[TlIntgErrNone]	full_word	auto[0]	657807	1			T1	42414		T2	17		T4	4824
auto[TlIntgErrNone]	full_word	auto[1]	2127703	1			T1	138789		T4	15530		T11	10382
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T56	5		T57	4		T58	3
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T56	4		T57	4		T58	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T104	1		T105	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T106	1		T107	1		T108	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T56	2		T57	5		T58	1
auto[TlIntgErrData]	partial	auto[1]	51	1			T56	2		T57	2		T58	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T58	2		T99	1		T103	1
auto[TlIntgErrData]	full_word	auto[1]	12	1			T56	2		T57	1		T97	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T56	2		T58	3		T97	7
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T56	2		T57	3		T58	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T101	1		T106	1		T105	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T56	1		T57	1		T58	2