Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	88359	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2285845

1

T1

63346

T2

9

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	615581	1			T1	17077		T2	121		T3	89
values[0x0]	864198	1			T1	23951		T5	14528		T6	36728
values[0x1]	894425	1			T1	24558		T5	15143		T6	37862

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46399	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2327805

1

T1

64373

T2

69

T3

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8925	1			T1	251		T2	1		T5	148
valid_sources[0x01]	9299	1			T1	249		T2	1		T5	175
valid_sources[0x02]	9262	1			T1	229		T2	1		T5	164
valid_sources[0x03]	8825	1			T1	257		T5	192		T6	350
valid_sources[0x04]	8255	1			T1	275		T2	1		T5	132
valid_sources[0x05]	9652	1			T1	271		T2	1		T5	148
valid_sources[0x06]	8918	1			T1	268		T5	140		T6	401
valid_sources[0x07]	8454	1			T1	240		T5	160		T6	413
valid_sources[0x08]	10580	1			T1	241		T5	167		T6	422
valid_sources[0x09]	8545	1			T1	233		T2	1		T5	129
valid_sources[0x0a]	9765	1			T1	258		T5	152		T6	357
valid_sources[0x0b]	8777	1			T1	242		T5	149		T6	357
valid_sources[0x0c]	9305	1			T1	284		T5	180		T6	357
valid_sources[0x0d]	11746	1			T1	207		T2	1		T5	168
valid_sources[0x0e]	9504	1			T1	228		T5	176		T6	358
valid_sources[0x0f]	8710	1			T1	317		T5	176		T6	390
valid_sources[0x10]	9150	1			T1	242		T2	1		T5	157
valid_sources[0x11]	9741	1			T1	248		T2	1		T5	173
valid_sources[0x12]	9761	1			T1	264		T5	151		T6	424
valid_sources[0x13]	9118	1			T1	242		T5	240		T6	368
valid_sources[0x14]	10157	1			T1	249		T5	142		T6	426
valid_sources[0x15]	9238	1			T1	272		T5	197		T6	376
valid_sources[0x16]	8593	1			T1	248		T5	161		T6	392
valid_sources[0x17]	9660	1			T1	261		T2	1		T5	145
valid_sources[0x18]	9307	1			T1	241		T5	120		T6	359
valid_sources[0x19]	10583	1			T1	290		T5	123		T6	379
valid_sources[0x1a]	9487	1			T1	260		T5	193		T6	353
valid_sources[0x1b]	10913	1			T1	288		T2	1		T5	130
valid_sources[0x1c]	10857	1			T1	270		T5	101		T6	427
valid_sources[0x1d]	9387	1			T1	259		T2	3		T5	202
valid_sources[0x1e]	8866	1			T1	233		T5	143		T6	350
valid_sources[0x1f]	9656	1			T1	253		T5	227		T6	409
valid_sources[0x20]	9841	1			T1	271		T2	1		T5	182
valid_sources[0x21]	9027	1			T1	230		T5	165		T6	373
valid_sources[0x22]	8767	1			T1	270		T2	1		T5	145
valid_sources[0x23]	9365	1			T1	292		T5	141		T6	362
valid_sources[0x24]	9497	1			T1	226		T5	136		T6	411
valid_sources[0x25]	9303	1			T1	274		T5	208		T6	338
valid_sources[0x26]	9373	1			T1	249		T5	134		T6	409
valid_sources[0x27]	9485	1			T1	228		T5	171		T6	465
valid_sources[0x28]	9831	1			T1	269		T5	220		T6	370
valid_sources[0x29]	10004	1			T1	282		T2	1		T5	147
valid_sources[0x2a]	9341	1			T1	296		T5	175		T6	439
valid_sources[0x2b]	9245	1			T1	257		T5	177		T6	352
valid_sources[0x2c]	9192	1			T1	213		T5	169		T6	372
valid_sources[0x2d]	8850	1			T1	281		T2	1		T5	184
valid_sources[0x2e]	9690	1			T1	267		T2	2		T5	148
valid_sources[0x2f]	10214	1			T1	258		T2	1		T5	209
valid_sources[0x30]	10682	1			T1	249		T5	139		T6	340
valid_sources[0x31]	8876	1			T1	288		T2	1		T5	151
valid_sources[0x32]	9066	1			T1	244		T5	158		T6	404
valid_sources[0x33]	10229	1			T1	216		T2	1		T5	122
valid_sources[0x34]	11056	1			T1	235		T5	198		T6	391
valid_sources[0x35]	8663	1			T1	268		T5	145		T6	378
valid_sources[0x36]	8958	1			T1	227		T5	138		T6	403
valid_sources[0x37]	9168	1			T1	256		T5	165		T6	348
valid_sources[0x38]	9329	1			T1	257		T2	1		T5	162
valid_sources[0x39]	8842	1			T1	254		T2	3		T5	177
valid_sources[0x3a]	9733	1			T1	294		T5	128		T6	343
valid_sources[0x3b]	9314	1			T1	249		T5	200		T6	369
valid_sources[0x3c]	9057	1			T1	264		T5	185		T6	365
valid_sources[0x3d]	8703	1			T1	295		T5	184		T6	410
valid_sources[0x3e]	9773	1			T1	259		T5	208		T6	399
valid_sources[0x3f]	8309	1			T1	237		T2	1		T5	116
valid_sources[0x40]	8126	1			T1	202		T5	181		T6	365
valid_sources[0x41]	8241	1			T1	240		T5	139		T6	402
valid_sources[0x42]	10230	1			T1	243		T5	149		T6	394
valid_sources[0x43]	8840	1			T1	298		T5	218		T6	323
valid_sources[0x44]	8390	1			T1	255		T5	129		T6	375
valid_sources[0x45]	9724	1			T1	269		T2	1		T5	108
valid_sources[0x46]	9644	1			T1	279		T5	127		T6	398
valid_sources[0x47]	9249	1			T1	267		T2	2		T5	138
valid_sources[0x48]	9528	1			T1	270		T2	2		T5	209
valid_sources[0x49]	10474	1			T1	264		T2	1		T5	152
valid_sources[0x4a]	8590	1			T1	230		T5	123		T6	373
valid_sources[0x4b]	8880	1			T1	210		T5	128		T6	411
valid_sources[0x4c]	9812	1			T1	254		T5	178		T6	392
valid_sources[0x4d]	11025	1			T1	281		T5	167		T6	400
valid_sources[0x4e]	8556	1			T1	235		T5	144		T6	355
valid_sources[0x4f]	8346	1			T1	304		T5	128		T6	351
valid_sources[0x50]	9072	1			T1	235		T5	206		T6	388
valid_sources[0x51]	10758	1			T1	265		T2	1		T5	184
valid_sources[0x52]	9131	1			T1	242		T2	1		T5	158
valid_sources[0x53]	8932	1			T1	274		T2	1		T5	174
valid_sources[0x54]	9939	1			T1	241		T5	135		T6	370
valid_sources[0x55]	8770	1			T1	295		T5	163		T6	412
valid_sources[0x56]	9053	1			T1	252		T5	84		T6	410
valid_sources[0x57]	9226	1			T1	239		T3	19		T5	184
valid_sources[0x58]	10393	1			T1	256		T5	124		T6	402
valid_sources[0x59]	8848	1			T1	272		T5	197		T6	386
valid_sources[0x5a]	12544	1			T1	242		T5	179		T6	328
valid_sources[0x5b]	8332	1			T1	254		T5	177		T6	382
valid_sources[0x5c]	9211	1			T1	237		T5	147		T6	386
valid_sources[0x5d]	8453	1			T1	256		T2	1		T5	107
valid_sources[0x5e]	8440	1			T1	275		T2	1		T5	202
valid_sources[0x5f]	9881	1			T1	298		T5	174		T6	413
valid_sources[0x60]	9596	1			T1	223		T5	194		T6	399
valid_sources[0x61]	8606	1			T1	244		T5	158		T6	387
valid_sources[0x62]	8361	1			T1	248		T5	154		T6	416
valid_sources[0x63]	8896	1			T1	237		T5	146		T6	377
valid_sources[0x64]	9854	1			T1	272		T5	161		T6	418
valid_sources[0x65]	9705	1			T1	315		T5	155		T6	444
valid_sources[0x66]	8979	1			T1	243		T5	173		T6	447
valid_sources[0x67]	8775	1			T1	255		T5	141		T6	429
valid_sources[0x68]	8937	1			T1	260		T5	154		T6	378
valid_sources[0x69]	8753	1			T1	254		T2	1		T3	25
valid_sources[0x6a]	9090	1			T1	237		T5	112		T6	419
valid_sources[0x6b]	8170	1			T1	252		T5	145		T6	323
valid_sources[0x6c]	9154	1			T1	276		T2	1		T5	149
valid_sources[0x6d]	9620	1			T1	239		T5	141		T6	361
valid_sources[0x6e]	10188	1			T1	284		T2	1		T5	168
valid_sources[0x6f]	9689	1			T1	277		T5	191		T6	343
valid_sources[0x70]	9070	1			T1	261		T5	142		T6	366
valid_sources[0x71]	8945	1			T1	248		T5	160		T6	405
valid_sources[0x72]	8761	1			T1	257		T2	1		T5	190
valid_sources[0x73]	9397	1			T1	243		T2	1		T5	151
valid_sources[0x74]	9133	1			T1	256		T2	2		T5	143
valid_sources[0x75]	9273	1			T1	252		T5	140		T6	365
valid_sources[0x76]	9161	1			T1	296		T2	1		T5	150
valid_sources[0x77]	8580	1			T1	270		T5	156		T6	394
valid_sources[0x78]	9390	1			T1	253		T2	1		T5	162
valid_sources[0x79]	10191	1			T1	256		T2	3		T5	106
valid_sources[0x7a]	9075	1			T1	261		T5	163		T6	389
valid_sources[0x7b]	9798	1			T1	245		T2	1		T5	161
valid_sources[0x7c]	8312	1			T1	289		T2	2		T5	183
valid_sources[0x7d]	8830	1			T1	286		T5	222		T6	380
valid_sources[0x7e]	9595	1			T1	309		T2	1		T5	114
valid_sources[0x7f]	8687	1			T1	239		T5	135		T6	430
valid_sources[0x80]	8830	1			T1	299		T5	116		T6	401

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

573977

1

T1

16102

T2

9

T3

6

values[0x0]

all_enables

biggest_size

856727

1

T1

23748

T5

14398

T6

36417

values[0x1]

all_enables

biggest_size

855141

1

T1

23496

T5

14443

T6

36278

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	168182	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1736249

1

T1

48456

T3

16

T4

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	475147	1			T1	13246		T3	32		T4	36
values[0x0]	661246	1			T1	18413		T5	10622		T6	25666
values[0x1]	768038	1			T1	21419		T5	12499		T6	29752

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	74591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1829840

1

T1

51087

T3

21

T4

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7518	1			T1	138		T3	3		T5	129
valid_sources[0x01]	7490	1			T1	285		T5	115		T6	284
valid_sources[0x02]	7676	1			T1	143		T5	114		T6	255
valid_sources[0x03]	8750	1			T1	170		T5	122		T6	314
valid_sources[0x04]	7235	1			T1	297		T5	127		T6	325
valid_sources[0x05]	7320	1			T1	332		T5	105		T6	259
valid_sources[0x06]	7972	1			T1	181		T5	131		T6	255
valid_sources[0x07]	7467	1			T1	267		T5	139		T6	311
valid_sources[0x08]	6874	1			T1	238		T5	123		T6	254
valid_sources[0x09]	7415	1			T1	232		T5	120		T6	275
valid_sources[0x0a]	6855	1			T1	158		T5	103		T6	304
valid_sources[0x0b]	7373	1			T1	154		T5	110		T6	295
valid_sources[0x0c]	7486	1			T1	267		T5	122		T6	270
valid_sources[0x0d]	7080	1			T1	127		T5	130		T6	262
valid_sources[0x0e]	7273	1			T1	195		T5	129		T6	291
valid_sources[0x0f]	7839	1			T1	293		T5	129		T6	290
valid_sources[0x10]	7110	1			T1	181		T5	121		T6	286
valid_sources[0x11]	7042	1			T1	208		T5	142		T6	229
valid_sources[0x12]	7841	1			T1	209		T5	130		T6	269
valid_sources[0x13]	7196	1			T1	212		T5	99		T6	268
valid_sources[0x14]	6938	1			T1	184		T5	130		T6	313
valid_sources[0x15]	7041	1			T1	163		T5	107		T6	290
valid_sources[0x16]	7207	1			T1	204		T5	125		T6	287
valid_sources[0x17]	7378	1			T1	110		T5	133		T6	262
valid_sources[0x18]	7622	1			T1	185		T5	111		T6	279
valid_sources[0x19]	7532	1			T1	182		T5	111		T6	272
valid_sources[0x1a]	7843	1			T1	235		T5	123		T6	263
valid_sources[0x1b]	8158	1			T1	285		T5	114		T6	291
valid_sources[0x1c]	6937	1			T1	192		T3	1		T5	115
valid_sources[0x1d]	8654	1			T1	374		T3	1		T5	118
valid_sources[0x1e]	7636	1			T1	213		T5	115		T6	248
valid_sources[0x1f]	7220	1			T1	227		T5	108		T6	296
valid_sources[0x20]	7496	1			T1	199		T5	124		T6	256
valid_sources[0x21]	7102	1			T1	215		T5	125		T6	306
valid_sources[0x22]	7620	1			T1	186		T5	127		T6	290
valid_sources[0x23]	7324	1			T1	295		T3	1		T5	133
valid_sources[0x24]	7896	1			T1	250		T5	139		T6	269
valid_sources[0x25]	7269	1			T1	237		T5	116		T6	285
valid_sources[0x26]	7387	1			T1	224		T5	114		T6	277
valid_sources[0x27]	7380	1			T1	165		T5	104		T6	293
valid_sources[0x28]	7445	1			T1	148		T3	2		T5	115
valid_sources[0x29]	7331	1			T1	286		T5	118		T6	280
valid_sources[0x2a]	6966	1			T1	98		T5	125		T6	275
valid_sources[0x2b]	7142	1			T1	297		T5	110		T6	290
valid_sources[0x2c]	6962	1			T1	214		T5	127		T6	264
valid_sources[0x2d]	7887	1			T1	285		T5	116		T6	322
valid_sources[0x2e]	6850	1			T1	146		T5	125		T6	297
valid_sources[0x2f]	7188	1			T1	163		T5	124		T6	278
valid_sources[0x30]	6916	1			T1	152		T5	121		T6	307
valid_sources[0x31]	7722	1			T1	129		T5	127		T6	293
valid_sources[0x32]	7227	1			T1	197		T5	144		T6	329
valid_sources[0x33]	7643	1			T1	310		T5	139		T6	292
valid_sources[0x34]	7451	1			T1	244		T5	95		T6	309
valid_sources[0x35]	6841	1			T1	70		T5	117		T6	258
valid_sources[0x36]	7179	1			T1	168		T5	126		T6	293
valid_sources[0x37]	7837	1			T1	137		T5	114		T6	293
valid_sources[0x38]	6550	1			T1	151		T5	109		T6	314
valid_sources[0x39]	7502	1			T1	124		T3	2		T5	121
valid_sources[0x3a]	7285	1			T1	169		T5	109		T6	256
valid_sources[0x3b]	7234	1			T1	202		T3	1		T5	122
valid_sources[0x3c]	6910	1			T1	179		T3	1		T5	103
valid_sources[0x3d]	7396	1			T1	108		T5	119		T6	263
valid_sources[0x3e]	8058	1			T1	138		T3	1		T5	135
valid_sources[0x3f]	7507	1			T1	198		T5	141		T6	313
valid_sources[0x40]	7062	1			T1	92		T5	106		T6	324
valid_sources[0x41]	7120	1			T1	156		T5	116		T6	286
valid_sources[0x42]	7754	1			T1	181		T5	125		T6	273
valid_sources[0x43]	7388	1			T1	130		T5	110		T6	270
valid_sources[0x44]	7684	1			T1	331		T4	36		T5	108
valid_sources[0x45]	7675	1			T1	139		T5	122		T6	299
valid_sources[0x46]	6687	1			T1	76		T5	105		T6	260
valid_sources[0x47]	8097	1			T1	194		T5	98		T6	279
valid_sources[0x48]	7474	1			T1	206		T5	131		T6	269
valid_sources[0x49]	8100	1			T1	198		T5	130		T6	312
valid_sources[0x4a]	7147	1			T1	215		T5	110		T6	312
valid_sources[0x4b]	7562	1			T1	171		T5	120		T6	261
valid_sources[0x4c]	7624	1			T1	223		T3	1		T5	112
valid_sources[0x4d]	7252	1			T1	140		T5	141		T6	309
valid_sources[0x4e]	7817	1			T1	250		T5	114		T6	279
valid_sources[0x4f]	7686	1			T1	141		T5	123		T6	296
valid_sources[0x50]	6950	1			T1	154		T5	104		T6	321
valid_sources[0x51]	7335	1			T1	252		T5	131		T6	295
valid_sources[0x52]	7349	1			T1	248		T5	102		T6	305
valid_sources[0x53]	6877	1			T1	148		T5	104		T6	250
valid_sources[0x54]	7918	1			T1	245		T5	112		T6	277
valid_sources[0x55]	7300	1			T1	168		T5	117		T6	295
valid_sources[0x56]	8274	1			T1	184		T5	118		T6	282
valid_sources[0x57]	7815	1			T1	238		T5	130		T6	290
valid_sources[0x58]	7358	1			T1	191		T5	126		T6	318
valid_sources[0x59]	7716	1			T1	249		T5	122		T6	295
valid_sources[0x5a]	8096	1			T1	326		T5	140		T6	302
valid_sources[0x5b]	7494	1			T1	311		T3	2		T5	140
valid_sources[0x5c]	6319	1			T1	144		T5	119		T6	311
valid_sources[0x5d]	7065	1			T1	172		T5	129		T6	286
valid_sources[0x5e]	8204	1			T1	225		T5	102		T6	291
valid_sources[0x5f]	7015	1			T1	206		T5	120		T6	312
valid_sources[0x60]	7612	1			T1	194		T5	121		T6	245
valid_sources[0x61]	7768	1			T1	291		T5	135		T6	295
valid_sources[0x62]	7498	1			T1	137		T5	131		T6	336
valid_sources[0x63]	7433	1			T1	159		T5	111		T6	274
valid_sources[0x64]	7657	1			T1	209		T5	141		T6	264
valid_sources[0x65]	7769	1			T1	179		T5	120		T6	278
valid_sources[0x66]	8078	1			T1	312		T5	133		T6	336
valid_sources[0x67]	8235	1			T1	245		T5	120		T6	296
valid_sources[0x68]	7595	1			T1	199		T5	133		T6	308
valid_sources[0x69]	7793	1			T1	261		T5	122		T6	249
valid_sources[0x6a]	6511	1			T1	107		T5	113		T6	291
valid_sources[0x6b]	8293	1			T1	142		T5	116		T6	272
valid_sources[0x6c]	7401	1			T1	149		T5	113		T6	290
valid_sources[0x6d]	7552	1			T1	162		T5	125		T6	293
valid_sources[0x6e]	7323	1			T1	218		T5	125		T6	318
valid_sources[0x6f]	7834	1			T1	366		T5	129		T6	312
valid_sources[0x70]	7186	1			T1	120		T5	97		T6	311
valid_sources[0x71]	7296	1			T1	286		T3	1		T5	117
valid_sources[0x72]	8026	1			T1	411		T5	115		T6	311
valid_sources[0x73]	7268	1			T1	240		T5	122		T6	266
valid_sources[0x74]	6756	1			T1	197		T5	129		T6	280
valid_sources[0x75]	7108	1			T1	136		T5	105		T6	261
valid_sources[0x76]	7547	1			T1	156		T5	110		T6	289
valid_sources[0x77]	8720	1			T1	245		T5	129		T6	306
valid_sources[0x78]	7098	1			T1	164		T5	116		T6	264
valid_sources[0x79]	8412	1			T1	264		T5	133		T6	267
valid_sources[0x7a]	7631	1			T1	289		T5	124		T6	295
valid_sources[0x7b]	7371	1			T1	210		T5	118		T6	298
valid_sources[0x7c]	6779	1			T1	172		T5	129		T6	296
valid_sources[0x7d]	7724	1			T1	288		T5	112		T6	290
valid_sources[0x7e]	7155	1			T1	189		T5	126		T6	265
valid_sources[0x7f]	7677	1			T1	160		T5	124		T6	305
valid_sources[0x80]	7769	1			T1	285		T5	121		T6	275

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

439348

1

T1

12263

T3

16

T4

17

values[0x0]

all_enables

biggest_size

647880

1

T1

18043

T5

10465

T6

25158

values[0x1]

all_enables

biggest_size

649021

1

T1

18150

T5

10663

T6

25059