Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4201390

1

T1

119605

T2

112

T3

83

full_word

2671119

1

T1

74399

T2

9

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6872219	1			T1	194004		T2	121		T3	89
auto[TlIntgErrCmd]	84	1			T57	4		T58	6		T59	3
auto[TlIntgErrData]	105	1			T57	5		T58	6		T59	3
auto[TlIntgErrBoth]	101	1			T57	11		T58	8		T59	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084060

1

T1

30830

T2

121

T3

89

auto[1]

5788449

1

T1

163174

T5

97716

T6

233060

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	453671	1			T1	13069		T2	112		T3	83
auto[TlIntgErrNone]	partial	auto[1]	3747448	1			T1	106536		T5	63217		T6	147367
auto[TlIntgErrNone]	full_word	auto[0]	630274	1			T1	17761		T2	9		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	2040826	1			T1	56638		T5	34499		T6	85693
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T57	2		T58	2		T59	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T57	1		T58	4		T59	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T57	1		T123	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T57	3		T58	2		T125	1
auto[TlIntgErrData]	partial	auto[1]	54	1			T57	2		T58	4		T59	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T126	2		T127	2		T128	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T129	1		T130	1		T128	2
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T57	2		T58	4		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T57	9		T58	4		T59	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T130	1		T127	1		T131	2
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T132	1		-	-		-	-