Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_rom_ctrl_cov_if::rom_ctrl_tlul_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
87.50 87.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rom_ctrl_cov_0/rom_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
rom_ctrl_tlul_cg 87.50 1 100 1 64 64




Group Instance : rom_ctrl_tlul_cg
Comment: TLUL interface behaviors
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64




Summary for Group Instance rom_ctrl_tlul_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group Instance rom_ctrl_tlul_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regs_req_check 3 0 3 100.00 100 1 1 0
cp_rom_invalid_condition 2 1 1 50.00 100 1 1 0
cp_rom_req_check 3 0 3 100.00 100 1 1 0


Summary for Variable cp_regs_req_check

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_regs_req_check

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
req_after_done 5283378 1 T2 32 T3 32 T6 4
req_and_done 10 1 T15 1 T86 2 T87 2
req_before_done 21 1 T48 1 T104 1 T105 1



Summary for Variable cp_rom_invalid_condition

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_rom_invalid_condition

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
check_invalid 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
check_valid 155541298 1 T1 12700 T2 18357 T3 17779



Summary for Variable cp_rom_req_check

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rom_req_check

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
req_after_done 6116040 1 T2 89 T3 1 T6 6
req_and_done 84 1 T8 1 T11 1 T20 1
req_before_done 343 1 T2 2 T3 1 T9 1

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