Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6548639

1

T2

87

T3

53

T8

187

full_word

4188179

1

T2

10

T3

4

T6

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	10736518	1			T2	97		T3	57		T6	4
auto[TlIntgErrCmd]	101	1			T62	7		T63	5		T64	4
auto[TlIntgErrData]	105	1			T62	9		T63	8		T64	12
auto[TlIntgErrBoth]	94	1			T62	4		T63	7		T64	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1680638

1

T2

97

T3

57

T6

4

auto[1]

9056180

1

T13

160322

T14

721998

T15

251725

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	693211	1			T2	87		T3	53		T8	187
auto[TlIntgErrNone]	partial	auto[1]	5855154	1			T13	103482		T14	469781		T15	161100
auto[TlIntgErrNone]	full_word	auto[0]	987292	1			T2	10		T3	4		T6	4
auto[TlIntgErrNone]	full_word	auto[1]	3200861	1			T13	56840		T14	252217		T15	90625
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T62	2		T63	2		T64	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T62	3		T63	3		T64	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T62	1		T112	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T62	1		T112	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T62	2		T63	3		T64	2
auto[TlIntgErrData]	partial	auto[1]	52	1			T62	5		T63	5		T64	10
auto[TlIntgErrData]	full_word	auto[0]	7	1			T62	1		T112	1		T106	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T62	1		T109	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T62	2		T63	3		T111	4
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T62	2		T63	4		T64	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T116	1		T106	2		T117	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T112	1		T118	1		T113	1