Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	49083	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1428938

1

T1

6

T4

13

T6

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	379221	1			T1	6		T4	93		T6	179
values[0x0]	539141	1			T10	27483		T12	16740		T13	34063
values[0x1]	559659	1			T10	28794		T12	17564		T13	35862

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1452039

1

T1

6

T4

57

T6

112

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6939	1			T10	293		T12	184		T17	2
valid_sources[0x01]	5420	1			T6	1		T10	260		T12	210
valid_sources[0x02]	5157	1			T6	1		T10	255		T16	1
valid_sources[0x03]	5715	1			T4	1		T10	240		T12	169
valid_sources[0x04]	6010	1			T4	1		T6	1		T10	295
valid_sources[0x05]	7006	1			T6	1		T10	285		T12	190
valid_sources[0x06]	5196	1			T10	232		T12	153		T17	2
valid_sources[0x07]	5350	1			T10	419		T12	179		T17	2
valid_sources[0x08]	6433	1			T4	3		T6	2		T10	326
valid_sources[0x09]	6898	1			T10	229		T12	200		T17	4
valid_sources[0x0a]	4677	1			T6	1		T10	267		T16	2
valid_sources[0x0b]	4675	1			T10	219		T12	191		T17	2
valid_sources[0x0c]	5339	1			T6	1		T10	286		T12	213
valid_sources[0x0d]	5979	1			T10	283		T12	172		T17	1
valid_sources[0x0e]	7218	1			T10	294		T12	161		T17	2
valid_sources[0x0f]	5532	1			T6	1		T10	220		T12	178
valid_sources[0x10]	5895	1			T6	1		T10	238		T12	189
valid_sources[0x11]	5248	1			T10	288		T12	176		T17	1
valid_sources[0x12]	6776	1			T4	1		T6	1		T10	254
valid_sources[0x13]	5318	1			T6	1		T10	247		T12	171
valid_sources[0x14]	7102	1			T10	311		T12	184		T17	2
valid_sources[0x15]	6093	1			T10	211		T12	193		T17	2
valid_sources[0x16]	5672	1			T6	2		T10	304		T12	210
valid_sources[0x17]	5268	1			T6	4		T10	338		T16	7
valid_sources[0x18]	5520	1			T10	267		T12	199		T13	317
valid_sources[0x19]	5820	1			T10	304		T12	183		T17	2
valid_sources[0x1a]	4772	1			T4	7		T6	1		T10	281
valid_sources[0x1b]	5605	1			T6	2		T10	332		T12	184
valid_sources[0x1c]	6969	1			T4	2		T10	359		T12	156
valid_sources[0x1d]	4627	1			T6	1		T10	281		T12	170
valid_sources[0x1e]	5156	1			T6	1		T10	334		T12	204
valid_sources[0x1f]	5076	1			T10	255		T12	195		T17	3
valid_sources[0x20]	6410	1			T10	276		T16	7		T12	189
valid_sources[0x21]	5440	1			T4	1		T9	1		T10	223
valid_sources[0x22]	6901	1			T6	2		T10	371		T12	155
valid_sources[0x23]	4788	1			T10	312		T12	211		T17	2
valid_sources[0x24]	6207	1			T10	275		T12	158		T17	1
valid_sources[0x25]	5536	1			T6	1		T10	282		T12	164
valid_sources[0x26]	5101	1			T6	1		T10	281		T16	7
valid_sources[0x27]	5689	1			T6	2		T10	234		T12	178
valid_sources[0x28]	5559	1			T10	313		T12	164		T17	1
valid_sources[0x29]	6830	1			T6	3		T10	265		T12	186
valid_sources[0x2a]	4674	1			T6	2		T10	261		T12	177
valid_sources[0x2b]	4794	1			T10	191		T12	185		T14	5
valid_sources[0x2c]	5305	1			T6	2		T10	412		T12	206
valid_sources[0x2d]	5440	1			T10	294		T12	173		T18	1
valid_sources[0x2e]	5447	1			T10	360		T12	186		T105	1
valid_sources[0x2f]	5259	1			T6	2		T10	275		T12	175
valid_sources[0x30]	6620	1			T4	2		T6	1		T10	214
valid_sources[0x31]	6203	1			T10	267		T12	194		T108	1
valid_sources[0x32]	4801	1			T6	3		T10	320		T12	166
valid_sources[0x33]	6722	1			T6	1		T10	311		T12	180
valid_sources[0x34]	5619	1			T6	1		T10	267		T12	168
valid_sources[0x35]	6644	1			T4	7		T10	250		T12	145
valid_sources[0x36]	6015	1			T10	370		T12	144		T13	364
valid_sources[0x37]	5206	1			T10	220		T12	175		T40	1
valid_sources[0x38]	6872	1			T6	2		T10	239		T12	171
valid_sources[0x39]	4816	1			T6	1		T10	340		T12	168
valid_sources[0x3a]	5229	1			T10	233		T12	180		T17	1
valid_sources[0x3b]	5438	1			T6	1		T10	221		T16	21
valid_sources[0x3c]	5049	1			T10	329		T12	218		T17	1
valid_sources[0x3d]	5622	1			T10	243		T12	171		T17	2
valid_sources[0x3e]	5513	1			T6	3		T10	348		T12	201
valid_sources[0x3f]	4861	1			T10	169		T12	182		T108	5
valid_sources[0x40]	6507	1			T6	1		T10	299		T12	191
valid_sources[0x41]	5243	1			T10	239		T12	197		T17	2
valid_sources[0x42]	5978	1			T10	320		T12	189		T17	1
valid_sources[0x43]	4817	1			T10	288		T12	157		T17	2
valid_sources[0x44]	6765	1			T6	1		T10	302		T12	198
valid_sources[0x45]	6587	1			T6	2		T10	332		T12	170
valid_sources[0x46]	7237	1			T6	2		T10	280		T16	4
valid_sources[0x47]	4943	1			T6	1		T10	306		T12	184
valid_sources[0x48]	5154	1			T1	2		T10	266		T12	156
valid_sources[0x49]	5767	1			T10	334		T12	158		T17	1
valid_sources[0x4a]	9034	1			T4	1		T6	2		T10	220
valid_sources[0x4b]	5619	1			T6	1		T10	184		T12	189
valid_sources[0x4c]	7312	1			T6	1		T10	300		T12	187
valid_sources[0x4d]	7542	1			T10	325		T12	198		T17	1
valid_sources[0x4e]	4537	1			T6	1		T10	373		T12	200
valid_sources[0x4f]	5494	1			T6	1		T10	317		T12	173
valid_sources[0x50]	5638	1			T6	1		T10	277		T12	201
valid_sources[0x51]	5233	1			T4	2		T6	1		T10	230
valid_sources[0x52]	5729	1			T4	1		T6	2		T10	248
valid_sources[0x53]	6655	1			T4	3		T6	1		T10	390
valid_sources[0x54]	4521	1			T10	297		T12	201		T17	1
valid_sources[0x55]	5186	1			T10	252		T12	152		T18	3
valid_sources[0x56]	6052	1			T4	1		T10	372		T12	165
valid_sources[0x57]	6489	1			T10	257		T12	174		T17	1
valid_sources[0x58]	5607	1			T4	1		T6	4		T10	263
valid_sources[0x59]	5503	1			T10	253		T16	5		T12	170
valid_sources[0x5a]	5521	1			T10	267		T16	1		T12	172
valid_sources[0x5b]	5745	1			T10	389		T12	179		T105	2
valid_sources[0x5c]	5711	1			T10	265		T12	188		T17	1
valid_sources[0x5d]	5283	1			T4	1		T10	330		T12	149
valid_sources[0x5e]	5901	1			T6	1		T10	437		T12	189
valid_sources[0x5f]	7251	1			T10	330		T12	191		T103	2
valid_sources[0x60]	5031	1			T6	1		T10	288		T12	149
valid_sources[0x61]	4830	1			T6	1		T10	281		T12	190
valid_sources[0x62]	5451	1			T10	280		T12	184		T103	3
valid_sources[0x63]	5378	1			T10	245		T12	186		T17	1
valid_sources[0x64]	6792	1			T4	1		T6	1		T10	275
valid_sources[0x65]	5228	1			T6	3		T10	209		T12	147
valid_sources[0x66]	5586	1			T6	3		T10	310		T12	225
valid_sources[0x67]	6194	1			T4	2		T6	2		T10	282
valid_sources[0x68]	5167	1			T9	1		T10	364		T12	179
valid_sources[0x69]	5632	1			T6	1		T10	279		T12	179
valid_sources[0x6a]	6077	1			T10	263		T12	158		T17	1
valid_sources[0x6b]	5466	1			T10	344		T12	171		T17	3
valid_sources[0x6c]	6354	1			T9	4		T10	320		T12	168
valid_sources[0x6d]	4877	1			T10	408		T12	173		T17	2
valid_sources[0x6e]	5280	1			T10	221		T12	160		T17	1
valid_sources[0x6f]	4978	1			T10	287		T12	200		T17	1
valid_sources[0x70]	6567	1			T6	1		T10	285		T12	192
valid_sources[0x71]	5850	1			T10	346		T12	183		T103	1
valid_sources[0x72]	4941	1			T6	1		T10	269		T12	157
valid_sources[0x73]	6063	1			T10	284		T12	162		T17	1
valid_sources[0x74]	5481	1			T10	228		T12	175		T17	1
valid_sources[0x75]	7053	1			T10	328		T12	188		T17	2
valid_sources[0x76]	5622	1			T10	251		T12	187		T17	1
valid_sources[0x77]	6729	1			T10	349		T16	5		T12	166
valid_sources[0x78]	6971	1			T10	241		T12	169		T108	4
valid_sources[0x79]	5156	1			T10	253		T12	186		T18	1
valid_sources[0x7a]	5488	1			T4	1		T10	270		T12	198
valid_sources[0x7b]	7217	1			T4	5		T6	1		T10	254
valid_sources[0x7c]	5997	1			T4	4		T6	1		T10	223
valid_sources[0x7d]	5255	1			T4	1		T10	220		T12	165
valid_sources[0x7e]	5167	1			T4	2		T6	1		T10	348
valid_sources[0x7f]	4696	1			T10	219		T12	156		T17	1
valid_sources[0x80]	5334	1			T10	297		T12	186		T17	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

359167

1

T1

6

T4

13

T6

18

values[0x0]

all_enables

biggest_size

534467

1

T10

27265

T12

16615

T13

33743

values[0x1]

all_enables

biggest_size

535304

1

T10

27584

T12

16783

T13

34305

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	104555	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1108078

1

T1

25

T4

27

T5

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	299662	1			T1	43		T3	1		T4	48
values[0x0]	423320	1			T2	1		T7	2		T10	20502
values[0x1]	489651	1			T7	2		T10	23708		T11	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45986	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1166647

1

T1

28

T4

33

T5

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4257	1			T4	1		T10	226		T12	131
valid_sources[0x01]	4370	1			T10	201		T12	133		T18	1
valid_sources[0x02]	5369	1			T10	237		T12	197		T13	694
valid_sources[0x03]	4893	1			T1	1		T4	1		T10	247
valid_sources[0x04]	4767	1			T10	241		T12	141		T104	1
valid_sources[0x05]	4663	1			T10	251		T12	139		T13	142
valid_sources[0x06]	4164	1			T10	230		T12	126		T13	56
valid_sources[0x07]	5353	1			T1	1		T10	212		T12	105
valid_sources[0x08]	5926	1			T10	223		T12	166		T13	745
valid_sources[0x09]	5129	1			T4	1		T10	254		T12	144
valid_sources[0x0a]	4727	1			T10	229		T12	168		T13	459
valid_sources[0x0b]	4754	1			T10	232		T12	127		T18	1
valid_sources[0x0c]	3787	1			T10	274		T12	134		T13	156
valid_sources[0x0d]	4793	1			T10	218		T12	148		T13	233
valid_sources[0x0e]	4752	1			T10	221		T12	134		T19	2
valid_sources[0x0f]	4584	1			T1	1		T10	226		T12	147
valid_sources[0x10]	4327	1			T1	1		T10	216		T12	141
valid_sources[0x11]	4149	1			T10	214		T12	177		T13	291
valid_sources[0x12]	4787	1			T9	5		T10	243		T12	137
valid_sources[0x13]	4555	1			T10	207		T12	136		T104	1
valid_sources[0x14]	4560	1			T10	242		T12	171		T24	1
valid_sources[0x15]	4642	1			T10	225		T12	158		T104	1
valid_sources[0x16]	4790	1			T4	1		T10	226		T12	154
valid_sources[0x17]	4781	1			T1	1		T10	208		T12	180
valid_sources[0x18]	4665	1			T10	250		T12	193		T18	1
valid_sources[0x19]	5359	1			T1	1		T10	212		T12	126
valid_sources[0x1a]	4554	1			T10	245		T12	130		T37	2
valid_sources[0x1b]	4723	1			T10	240		T12	169		T13	99
valid_sources[0x1c]	4997	1			T10	247		T12	135		T13	597
valid_sources[0x1d]	4441	1			T4	1		T10	238		T12	169
valid_sources[0x1e]	4442	1			T10	256		T12	91		T13	7
valid_sources[0x1f]	4217	1			T4	2		T10	228		T11	1
valid_sources[0x20]	4574	1			T1	2		T10	227		T12	138
valid_sources[0x21]	4951	1			T10	202		T12	160		T14	7
valid_sources[0x22]	4297	1			T10	268		T12	134		T18	1
valid_sources[0x23]	5491	1			T10	213		T12	143		T18	1
valid_sources[0x24]	4874	1			T10	219		T12	150		T19	2
valid_sources[0x25]	4925	1			T10	227		T12	157		T13	2
valid_sources[0x26]	4597	1			T10	226		T12	142		T45	411
valid_sources[0x27]	5276	1			T10	224		T12	147		T13	134
valid_sources[0x28]	4940	1			T10	199		T12	130		T13	88
valid_sources[0x29]	4669	1			T10	211		T12	164		T37	3
valid_sources[0x2a]	4307	1			T10	249		T12	141		T13	250
valid_sources[0x2b]	4995	1			T10	223		T12	170		T13	616
valid_sources[0x2c]	4851	1			T4	1		T10	217		T12	137
valid_sources[0x2d]	4797	1			T10	213		T12	168		T123	4
valid_sources[0x2e]	4482	1			T1	1		T10	242		T12	175
valid_sources[0x2f]	4795	1			T10	267		T12	135		T13	101
valid_sources[0x30]	5032	1			T10	211		T12	168		T13	472
valid_sources[0x31]	4417	1			T10	220		T12	141		T60	1
valid_sources[0x32]	4217	1			T10	239		T12	130		T13	94
valid_sources[0x33]	4552	1			T10	240		T11	3		T12	163
valid_sources[0x34]	4847	1			T10	223		T12	139		T13	474
valid_sources[0x35]	4286	1			T6	80		T10	224		T12	156
valid_sources[0x36]	4512	1			T1	1		T4	1		T10	229
valid_sources[0x37]	4649	1			T10	216		T12	113		T13	415
valid_sources[0x38]	4183	1			T10	238		T12	97		T14	8
valid_sources[0x39]	5031	1			T1	1		T10	219		T12	155
valid_sources[0x3a]	4360	1			T10	208		T12	158		T104	2
valid_sources[0x3b]	4157	1			T10	234		T12	181		T58	2
valid_sources[0x3c]	5219	1			T4	1		T10	223		T11	2
valid_sources[0x3d]	4100	1			T10	232		T12	170		T13	5
valid_sources[0x3e]	4088	1			T4	1		T9	2		T10	239
valid_sources[0x3f]	4431	1			T10	233		T12	199		T13	4
valid_sources[0x40]	5537	1			T10	240		T12	147		T13	348
valid_sources[0x41]	4642	1			T3	1		T4	1		T10	225
valid_sources[0x42]	3743	1			T10	215		T12	127		T13	145
valid_sources[0x43]	3845	1			T10	242		T12	106		T45	419
valid_sources[0x44]	4371	1			T10	225		T12	159		T13	44
valid_sources[0x45]	4966	1			T1	1		T10	179		T12	141
valid_sources[0x46]	5143	1			T1	1		T10	226		T12	157
valid_sources[0x47]	5051	1			T1	1		T10	203		T12	182
valid_sources[0x48]	5195	1			T10	236		T12	161		T19	2
valid_sources[0x49]	4985	1			T10	270		T12	172		T59	1
valid_sources[0x4a]	4546	1			T10	236		T12	124		T18	1
valid_sources[0x4b]	4283	1			T4	1		T10	230		T12	131
valid_sources[0x4c]	5562	1			T10	224		T12	133		T13	743
valid_sources[0x4d]	4893	1			T4	1		T10	216		T12	164
valid_sources[0x4e]	4389	1			T10	266		T12	139		T18	1
valid_sources[0x4f]	4562	1			T10	218		T12	109		T18	1
valid_sources[0x50]	5337	1			T10	227		T12	151		T18	1
valid_sources[0x51]	4868	1			T10	246		T12	139		T18	1
valid_sources[0x52]	4375	1			T1	1		T10	242		T12	114
valid_sources[0x53]	4877	1			T10	220		T12	152		T23	3
valid_sources[0x54]	4252	1			T10	230		T12	156		T13	3
valid_sources[0x55]	4741	1			T10	220		T12	166		T104	1
valid_sources[0x56]	5318	1			T10	222		T12	148		T13	447
valid_sources[0x57]	4708	1			T10	225		T12	114		T13	277
valid_sources[0x58]	4074	1			T10	241		T12	151		T104	1
valid_sources[0x59]	5026	1			T10	219		T12	150		T18	1
valid_sources[0x5a]	4925	1			T10	235		T12	145		T124	1
valid_sources[0x5b]	4591	1			T10	211		T12	116		T13	240
valid_sources[0x5c]	5196	1			T10	231		T12	153		T13	559
valid_sources[0x5d]	4313	1			T1	1		T9	3		T10	231
valid_sources[0x5e]	5152	1			T8	1		T10	231		T12	143
valid_sources[0x5f]	4877	1			T10	237		T12	149		T18	1
valid_sources[0x60]	5409	1			T1	1		T4	1		T10	242
valid_sources[0x61]	5637	1			T10	213		T12	131		T13	656
valid_sources[0x62]	5201	1			T4	1		T10	251		T12	148
valid_sources[0x63]	4376	1			T10	210		T12	142		T13	362
valid_sources[0x64]	4507	1			T1	1		T10	251		T36	2
valid_sources[0x65]	5156	1			T10	195		T12	146		T104	1
valid_sources[0x66]	5004	1			T10	225		T11	3		T12	135
valid_sources[0x67]	4633	1			T10	234		T12	155		T104	1
valid_sources[0x68]	5465	1			T10	222		T12	151		T13	197
valid_sources[0x69]	5225	1			T10	241		T12	138		T13	799
valid_sources[0x6a]	5097	1			T1	1		T10	251		T12	118
valid_sources[0x6b]	5256	1			T4	1		T10	235		T12	142
valid_sources[0x6c]	4468	1			T10	240		T12	143		T18	1
valid_sources[0x6d]	4927	1			T10	235		T12	109		T13	340
valid_sources[0x6e]	4249	1			T10	243		T12	152		T18	1
valid_sources[0x6f]	4099	1			T10	231		T12	149		T13	100
valid_sources[0x70]	5393	1			T10	230		T12	165		T13	932
valid_sources[0x71]	5099	1			T4	1		T10	265		T12	135
valid_sources[0x72]	4947	1			T10	246		T12	160		T13	693
valid_sources[0x73]	4601	1			T4	1		T10	245		T12	157
valid_sources[0x74]	4565	1			T4	1		T10	214		T12	126
valid_sources[0x75]	5348	1			T10	240		T12	144		T13	282
valid_sources[0x76]	4753	1			T1	2		T10	246		T12	163
valid_sources[0x77]	4355	1			T10	198		T11	2		T12	170
valid_sources[0x78]	4348	1			T10	212		T12	115		T104	2
valid_sources[0x79]	5117	1			T10	249		T12	136		T18	1
valid_sources[0x7a]	4965	1			T1	1		T10	264		T12	173
valid_sources[0x7b]	4761	1			T10	235		T12	152		T45	436
valid_sources[0x7c]	5405	1			T10	220		T12	156		T13	457
valid_sources[0x7d]	4713	1			T4	1		T10	183		T12	117
valid_sources[0x7e]	3824	1			T10	220		T12	149		T13	156
valid_sources[0x7f]	5104	1			T4	1		T10	228		T12	144
valid_sources[0x80]	4033	1			T10	247		T12	116		T18	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

278180

1

T1

25

T4

27

T5

16

values[0x0]

all_enables

biggest_size

414750

1

T10

20105

T11

1

T12

12744

values[0x1]

all_enables

biggest_size

415148

1

T10

20081

T11

1

T12

12815