Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2594030

1

T4

80

T6

161

T10

131322

full_word

1667563

1

T1

4

T4

13

T6

18

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4261303	1			T1	4		T4	93		T6	179
auto[TlIntgErrCmd]	84	1			T52	4		T53	6		T54	4
auto[TlIntgErrData]	103	1			T52	3		T53	12		T54	3
auto[TlIntgErrBoth]	103	1			T52	3		T53	2		T54	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668890

1

T1

4

T4

93

T6

179

auto[1]

3592703

1

T10

183352

T12

110377

T13

231027

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	274933	1			T4	80		T6	161		T10	13258
auto[TlIntgErrNone]	partial	auto[1]	2318827	1			T10	118064		T12	70886		T13	149660
auto[TlIntgErrNone]	full_word	auto[0]	393818	1			T1	4		T4	13		T6	18
auto[TlIntgErrNone]	full_word	auto[1]	1273725	1			T10	65288		T12	39491		T13	81367
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T52	3		T53	2		T54	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T52	1		T53	4		T54	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T111	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T118	1		T119	2		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T52	2		T53	6		T54	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T52	1		T53	5		T54	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T53	1		T117	2		T118	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T115	1		T120	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T52	1		T53	1		T54	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T52	2		T53	1		T54	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T112	1		T113	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T118	1		T116	1		-	-