Unified Coverage Report :: Module :: rom_ctrl

Module : rom_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.05	100.00	98.28	97.26		100.00	69.70

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	93.05	100.00	98.28	97.26		100.00	69.70

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.05	100.00	98.28	97.26		100.00	69.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.10	96.89	91.99	97.67	100.00	98.62	97.45

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_alert_sender	100.00			100.00
gen_fsm_scramble_enabled.u_checker_fsm	96.36	100.00	97.22	90.00	100.00	100.00	90.91
gen_rom_scramble_enabled.u_rom	97.06	88.24		100.00		100.00	100.00
regs_tlul_assert_device	100.00	100.00				100.00	100.00
rom_ctrl_regs_csr_assert	100.00						100.00
rom_tlul_assert_device	99.30	100.00				100.00	97.90
u_mux	95.24	100.00	85.71			100.00
u_reg_regs	99.72	99.41	99.21	100.00		100.00	100.00
u_tl_adapter_rom	93.03	90.70	82.58	97.66		94.20	100.00
u_tl_rom_h2d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	442	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
125	1	1
126	1	1
127	1	1
128	1	1
131	1	1
212	1	1
258	1	1
313	1	1
414	8	8
415	8	8
417	8	8
418	8	8
420	8	8
421	8	8
425	1	1
427	1	1
430	1	1
431	1	1
432	1	1
433	1	1
438	1	1
442	1	1

---

Cond Coverage for Module : rom_ctrl

	Total	Covered	Percent
Conditions	58	57	98.28
Logical	58	57	98.28
Non-Logical	0	0
Event	0	0

 LINE       212
 EXPRESSION (rom_tl_i.a_valid ? rom_tl_i.a_address[2+:RomIndexWidth] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       258
 EXPRESSION (bus_rom_rvalid_raw & ((!internal_alert)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T9
1	1	Covered	T1,T4,T6

 LINE       418
 EXPRESSION (exp_digest_de && (0 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (0 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (1 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (1 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (2 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (2 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (3 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (3 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (4 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (4 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (5 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (5 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (6 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (6 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       418
 EXPRESSION (exp_digest_de && (7 == exp_digest_idx))
             ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       418
 SUB-EXPRESSION (7 == exp_digest_idx)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       425
 EXPRESSION (rom_integrity_error | reg_integrity_error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21,T22
1	0	Not Covered

 LINE       427
 EXPRESSION (checker_alert | mux_alert)
             ------1------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T3,T5

 LINE       438
 EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
             ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T11,T23

 LINE       442
 EXPRESSION (bus_integrity_error | checker_alert | mux_alert)
             ---------1---------   ------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T5,T9
0	1	0	Covered	T1,T3,T5
1	0	0	Covered	T20,T21,T22

---

Toggle Coverage for Module : rom_ctrl

	Total	Covered	Percent
Totals	62	56	90.32
Total Bits	2884	2805	97.26
Total Bits 0->1	1442	1402	97.23
Total Bits 1->0	1442	1403	97.30

Ports	62	56	90.32
Port Bits	2884	2805	97.26
Port Bits 0->1	1442	1402	97.23
Port Bits 1->0	1442	1403	97.30

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
rom_cfg_i.test	No	No		No		INPUT
rom_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T8	Yes	T4,T6,T10	INPUT
rom_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T10,T12	Yes	T4,T10,T12	INPUT
rom_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_data[31:0]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T8	INPUT
rom_tl_i.a_mask[3:0]	Yes	Yes	T4,T6,T8	Yes	T4,T6,T8	INPUT
rom_tl_i.a_address[31:0]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T8	INPUT
rom_tl_i.a_source[7:0]	Yes	Yes	T4,T6,T9	Yes	T4,T6,T8	INPUT
rom_tl_i.a_size[1:0]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	INPUT
rom_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
rom_tl_i.a_opcode[2:0]	Yes	Yes	T4,T8,T10	Yes	T4,T10,T12	INPUT
rom_tl_i.a_valid	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
rom_tl_o.a_ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
rom_tl_o.d_error	Yes	Yes	T10,T12,T13	Yes	T10,T12,T13	OUTPUT
rom_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	OUTPUT
rom_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T4,*T6	Yes	T1,T4,T6	OUTPUT
rom_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_data[31:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	OUTPUT
rom_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_source[7:0]	Yes	Yes	T4,T6,T9	Yes	T4,T6,T9	OUTPUT
rom_tl_o.d_size[1:0]	Yes	Yes	T4,T6,T10	Yes	T4,T6,T10	OUTPUT
rom_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_opcode[0]	Yes	Yes	*T10,*T12,*T13	Yes	T10,T12,T13	OUTPUT
rom_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
rom_tl_o.d_valid	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T4	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T10,T12,T18	Yes	T10,T12,T18	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T4	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
regs_tl_i.a_address[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
regs_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T2,T7,T10	Yes	T2,T10,T11	INPUT
regs_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_error	Yes	Yes	T10,T12,T13	Yes	T10,T12,T13	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
regs_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
pwrmgr_data_o.good[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwrmgr_data_o.done[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T5	OUTPUT
keymgr_data_o.valid	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
keymgr_data_o.data[255:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
kmac_data_i.error	No	Yes	T3,T8,T24	No		INPUT
kmac_data_i.digest_share1[383:0]	Yes	Yes	T1,T3,T4	Yes	T1,T5,T6	INPUT
kmac_data_i.digest_share0[383:0]	Yes	Yes	T1,T5,T6	Yes	T1,T3,T5	INPUT
kmac_data_i.done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_i.ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
kmac_data_o.last	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[38:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
kmac_data_o.data[63:39]	No	No		No		OUTPUT
kmac_data_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rom_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	212	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv' or '../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	(rom_tl_i.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rom_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	23	69.70
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	23	69.70

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxOKnown_A	72018284	71847031	0	0
BusRomIndicesMatch_A	72006193	71841292	0	0
FpvSecCmRegWeOnehotCheck_A	72018284	80	0	0
FpvSecCmReqFifoRptrCheck_A	72018284	0	0	0
FpvSecCmReqFifoWptrCheck_A	72018284	0	0	0
FpvSecCmRspFifoRptrCheck_A	72018284	0	0	0
FpvSecCmRspFifoWptrCheck_A	72018284	0	0	0
FpvSecCmSramReqFifoRptrCheck_A	72018284	0	0	0
FpvSecCmSramReqFifoWptrCheck_A	72018284	0	0	0
KeymgrDataODataKnown_A	72018284	55570305	0	0
KeymgrDataODataKnown_AKnownEnable	72018284	71847031	0	0
KeymgrDataOValidKnown_A	72018284	71847031	0	0
KeymgrValidChk_A	72018284	0	0	280
KmacDataODataKnown_A	72018284	16140554	0	0
KmacDataODataKnown_AKnownEnable	72018284	71847031	0	0
KmacDataOValidKnown_A	72018284	71847031	0	0
PwrmgrDataChk_A	72018284	0	0	280
PwrmgrDataOKnown_A	72018284	71847031	0	0
RegsTlOAReadyKnown_A	72018284	71847031	0	0
RegsTlODDataKnown_A	72018284	9205630	0	0
RegsTlODDataKnown_AKnownEnable	72018284	71847031	0	0
RegsTlODValidKnown_A	72018284	71847031	0	0
RomTlOAReadyKnown_A	72018284	71847031	0	0
RomTlODDataKnown_A	72018284	11355709	0	0
RomTlODDataKnown_AKnownEnable	72018284	71847031	0	0
RomTlODValidKnown_A	72018284	71847031	0	0
StabilityChkKmac_A	72018284	16138217	0	0
StabilityChkkeymgr_A	72018284	55569279	0	0
TlAccessChk_A	72018284	16276726	0	0
gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A	72018284	80	0	0
gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A	72018284	0	0	0
gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A	72018284	518	0	0
gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A	72018284	0	0	0

AlertTxOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

BusRomIndicesMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72006193	71841292	0	0
T1	412022	408353	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	189813	188003	0	0
T10	208920	208903	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	80	0	0
T20	28129	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T25	0	20	0	0
T26	0	10	0	0
T27	9196	0	0	0
T28	50280	0	0	0
T29	8572	0	0	0
T30	25068	0	0	0
T31	9077	0	0	0
T32	25051	0	0	0
T33	271896	0	0	0
T34	246911	0	0	0
T35	12526	0	0	0

FpvSecCmReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	0	0	0

FpvSecCmReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	0	0	0

FpvSecCmRspFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	0	0	0

FpvSecCmRspFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	0	0	0

FpvSecCmSramReqFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	0	0	0

FpvSecCmSramReqFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	0	0	0

KeymgrDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	55570305	0	0
T1	412495	5590	0	0
T2	12630	289	0	0
T3	16864	281	0	0
T4	28458	3587	0	0
T5	317345	4325	0	0
T6	55066	5279	0	0
T7	12699	284	0	0
T8	16705	13	0	0
T9	190117	684	0	0
T10	208920	205516	0	0

KeymgrDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

KeymgrDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

KeymgrValidChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	0	0	280

KmacDataODataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	16140554	0	0
T1	412495	400182	0	0
T2	12630	12245	0	0
T3	16864	16368	0	0
T4	28458	24552	0	0
T5	317345	308271	0	0
T6	55066	49217	0	0
T7	12699	12290	0	0
T8	16705	16368	0	0
T9	190117	186074	0	0
T10	208920	33651	0	0

KmacDataODataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

KmacDataOValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

PwrmgrDataChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	0	0	280

PwrmgrDataOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

RegsTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

RegsTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	9205630	0	0
T1	412495	156	0	0
T2	12630	1	0	0
T3	16864	1	0	0
T4	28458	48	0	0
T5	317345	31	0	0
T6	55066	354	0	0
T7	12699	4	0	0
T8	16705	1	0	0
T9	190117	23	0	0
T10	208920	169273	0	0

RegsTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

RegsTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

RomTlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

RomTlODDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	11355709	0	0
T1	412495	37	0	0
T2	12630	0	0	0
T3	16864	0	0	0
T4	28458	93	0	0
T5	317345	0	0	0
T6	55066	179	0	0
T7	12699	0	0	0
T8	16705	0	0	0
T9	190117	62	0	0
T10	208920	216823	0	0
T12	0	727200	0	0
T16	0	139	0	0
T17	0	280	0	0
T18	0	92	0	0
T19	0	6	0	0

RomTlODDataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

RomTlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	71847031	0	0
T1	412495	408686	0	0
T2	12630	12556	0	0
T3	16864	16709	0	0
T4	28458	28202	0	0
T5	317345	314604	0	0
T6	55066	54711	0	0
T7	12699	12628	0	0
T8	16705	16530	0	0
T9	190117	188082	0	0
T10	208920	208903	0	0

StabilityChkKmac_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	16138217	0	0
T1	412495	400131	0	0
T2	12630	12244	0	0
T3	16864	16366	0	0
T4	28458	24549	0	0
T5	317345	308235	0	0
T6	55066	49212	0	0
T7	12699	12289	0	0
T8	16705	16366	0	0
T9	190117	186046	0	0
T10	208920	33646	0	0

StabilityChkkeymgr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	55569279	0	0
T1	412495	5574	0	0
T2	12630	288	0	0
T3	16864	280	0	0
T4	28458	3584	0	0
T5	317345	4311	0	0
T6	55066	5275	0	0
T7	12699	283	0	0
T8	16705	12	0	0
T9	190117	673	0	0
T10	208920	205516	0	0

TlAccessChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	16276726	0	0
T1	412495	403096	0	0
T2	12630	12267	0	0
T3	16864	16428	0	0
T4	28458	24615	0	0
T5	317345	310279	0	0
T6	55066	49432	0	0
T7	12699	12344	0	0
T8	16705	16517	0	0
T9	190117	187398	0	0
T10	208920	33864	0	0

gen_asserts_with_scrambling.FpvSecCmCheckerFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	80	0	0
T20	28129	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T25	0	20	0	0
T26	0	10	0	0
T27	9196	0	0	0
T28	50280	0	0	0
T29	8572	0	0	0
T30	25068	0	0	0
T31	9077	0	0	0
T32	25051	0	0	0
T33	271896	0	0	0
T34	246911	0	0	0
T35	12526	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareAddrCtrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	0	0	0

gen_asserts_with_scrambling.FpvSecCmCompareFsmAlert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	518	0	0
T1	412495	25	0	0
T2	12630	0	0	0
T3	16864	0	0	0
T4	28458	0	0	0
T5	317345	15	0	0
T6	55066	0	0	0
T7	12699	0	0	0
T8	16705	0	0	0
T9	190117	5	0	0
T10	208920	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T36	0	5	0	0
T37	0	10	0	0
T38	0	15	0	0
T39	0	5	0	0
T40	0	11	0	0

gen_fsm_scramble_enabled_asserts.BusLocalEscChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72018284	0	0	0