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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 96.89 92.13 97.67 100.00 98.62 97.30 98.37


Total test records in report: 413
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T297 /workspace/coverage/default/29.rom_ctrl_alert_test.615890885 Jul 30 06:19:16 PM PDT 24 Jul 30 06:19:22 PM PDT 24 131544357 ps
T298 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1419269810 Jul 30 06:19:00 PM PDT 24 Jul 30 06:19:06 PM PDT 24 97855212 ps
T299 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2091022160 Jul 30 06:19:40 PM PDT 24 Jul 30 06:21:52 PM PDT 24 18595125137 ps
T300 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1112756681 Jul 30 06:19:13 PM PDT 24 Jul 30 06:19:19 PM PDT 24 1654883286 ps
T301 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4230531140 Jul 30 06:19:26 PM PDT 24 Jul 30 06:20:33 PM PDT 24 10990453490 ps
T302 /workspace/coverage/default/2.rom_ctrl_stress_all.447035580 Jul 30 06:18:25 PM PDT 24 Jul 30 06:18:45 PM PDT 24 1689663395 ps
T303 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.219012115 Jul 30 06:19:34 PM PDT 24 Jul 30 06:19:41 PM PDT 24 142785104 ps
T304 /workspace/coverage/default/15.rom_ctrl_alert_test.600243440 Jul 30 06:19:00 PM PDT 24 Jul 30 06:19:04 PM PDT 24 175726392 ps
T305 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.981963112 Jul 30 06:19:11 PM PDT 24 Jul 30 06:19:22 PM PDT 24 251152641 ps
T306 /workspace/coverage/default/35.rom_ctrl_alert_test.2794398978 Jul 30 06:19:21 PM PDT 24 Jul 30 06:19:25 PM PDT 24 169333305 ps
T307 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4235740106 Jul 30 06:19:35 PM PDT 24 Jul 30 06:22:27 PM PDT 24 5229019833 ps
T28 /workspace/coverage/default/4.rom_ctrl_sec_cm.1581919849 Jul 30 06:18:32 PM PDT 24 Jul 30 06:19:26 PM PDT 24 188450786 ps
T308 /workspace/coverage/default/43.rom_ctrl_alert_test.3723378929 Jul 30 06:19:30 PM PDT 24 Jul 30 06:19:35 PM PDT 24 86527589 ps
T309 /workspace/coverage/default/31.rom_ctrl_alert_test.1254523531 Jul 30 06:19:18 PM PDT 24 Jul 30 06:19:23 PM PDT 24 350424440 ps
T310 /workspace/coverage/default/2.rom_ctrl_alert_test.532148317 Jul 30 06:18:28 PM PDT 24 Jul 30 06:18:33 PM PDT 24 1563007833 ps
T311 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.569253278 Jul 30 06:18:57 PM PDT 24 Jul 30 06:19:05 PM PDT 24 281242196 ps
T312 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2355753989 Jul 30 06:19:09 PM PDT 24 Jul 30 06:21:22 PM PDT 24 2268140278 ps
T313 /workspace/coverage/default/1.rom_ctrl_smoke.271914073 Jul 30 06:18:23 PM PDT 24 Jul 30 06:18:29 PM PDT 24 193369329 ps
T314 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3311922906 Jul 30 06:19:16 PM PDT 24 Jul 30 06:19:25 PM PDT 24 1005546215 ps
T315 /workspace/coverage/default/13.rom_ctrl_stress_all.1356810702 Jul 30 06:18:47 PM PDT 24 Jul 30 06:19:01 PM PDT 24 2030832399 ps
T316 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2205725191 Jul 30 06:19:08 PM PDT 24 Jul 30 06:19:17 PM PDT 24 724332836 ps
T317 /workspace/coverage/default/5.rom_ctrl_smoke.260524471 Jul 30 06:18:37 PM PDT 24 Jul 30 06:18:42 PM PDT 24 370187755 ps
T318 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3525613949 Jul 30 06:19:32 PM PDT 24 Jul 30 06:21:08 PM PDT 24 3335136628 ps
T319 /workspace/coverage/default/7.rom_ctrl_smoke.1421866735 Jul 30 06:18:39 PM PDT 24 Jul 30 06:18:45 PM PDT 24 101500368 ps
T320 /workspace/coverage/default/32.rom_ctrl_stress_all.1147717097 Jul 30 06:19:15 PM PDT 24 Jul 30 06:19:30 PM PDT 24 1577852509 ps
T321 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1016385400 Jul 30 06:19:27 PM PDT 24 Jul 30 06:20:53 PM PDT 24 2109168332 ps
T322 /workspace/coverage/default/48.rom_ctrl_stress_all.4051105114 Jul 30 06:19:45 PM PDT 24 Jul 30 06:19:54 PM PDT 24 164020371 ps
T323 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1488014570 Jul 30 06:18:24 PM PDT 24 Jul 30 06:18:30 PM PDT 24 379975689 ps
T324 /workspace/coverage/default/6.rom_ctrl_stress_all.3530839730 Jul 30 06:18:39 PM PDT 24 Jul 30 06:18:52 PM PDT 24 215719683 ps
T325 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.881792286 Jul 30 06:19:32 PM PDT 24 Jul 30 06:19:38 PM PDT 24 99204981 ps
T326 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2359666209 Jul 30 06:46:12 PM PDT 24 Jul 30 06:46:16 PM PDT 24 168526177 ps
T327 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3858989505 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:14 PM PDT 24 1554006932 ps
T60 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4168351742 Jul 30 06:46:19 PM PDT 24 Jul 30 06:46:25 PM PDT 24 263409520 ps
T328 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3723067823 Jul 30 06:46:30 PM PDT 24 Jul 30 06:46:38 PM PDT 24 1034912624 ps
T61 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3182611241 Jul 30 06:46:17 PM PDT 24 Jul 30 06:46:21 PM PDT 24 88367818 ps
T329 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3306654702 Jul 30 06:46:17 PM PDT 24 Jul 30 06:46:30 PM PDT 24 1827236841 ps
T62 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3634455294 Jul 30 06:46:08 PM PDT 24 Jul 30 06:46:14 PM PDT 24 87304627 ps
T63 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2436497802 Jul 30 06:46:44 PM PDT 24 Jul 30 06:47:03 PM PDT 24 376538992 ps
T56 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3268001370 Jul 30 06:46:36 PM PDT 24 Jul 30 06:47:47 PM PDT 24 844430470 ps
T330 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3739306156 Jul 30 06:46:08 PM PDT 24 Jul 30 06:46:13 PM PDT 24 517067698 ps
T93 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4092890071 Jul 30 06:46:08 PM PDT 24 Jul 30 06:46:17 PM PDT 24 268266193 ps
T331 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.146174763 Jul 30 06:46:20 PM PDT 24 Jul 30 06:46:26 PM PDT 24 89629041 ps
T332 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1589202013 Jul 30 06:46:13 PM PDT 24 Jul 30 06:46:23 PM PDT 24 246372318 ps
T89 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1696802289 Jul 30 06:46:19 PM PDT 24 Jul 30 06:46:25 PM PDT 24 733337957 ps
T333 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2346086362 Jul 30 06:46:28 PM PDT 24 Jul 30 06:46:34 PM PDT 24 554740093 ps
T57 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2164527411 Jul 30 06:46:11 PM PDT 24 Jul 30 06:47:17 PM PDT 24 795637879 ps
T58 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3645104005 Jul 30 06:46:24 PM PDT 24 Jul 30 06:47:01 PM PDT 24 216562376 ps
T99 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1264621355 Jul 30 06:46:31 PM PDT 24 Jul 30 06:47:39 PM PDT 24 576766079 ps
T105 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1600286859 Jul 30 06:46:06 PM PDT 24 Jul 30 06:46:46 PM PDT 24 687550008 ps
T94 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2536909679 Jul 30 06:46:07 PM PDT 24 Jul 30 06:46:12 PM PDT 24 594741024 ps
T90 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3199427281 Jul 30 06:46:23 PM PDT 24 Jul 30 06:46:28 PM PDT 24 85463792 ps
T64 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3221177884 Jul 30 06:46:14 PM PDT 24 Jul 30 06:46:19 PM PDT 24 131640013 ps
T95 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2102417921 Jul 30 06:46:18 PM PDT 24 Jul 30 06:46:23 PM PDT 24 480757831 ps
T65 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1848382150 Jul 30 06:46:14 PM PDT 24 Jul 30 06:46:21 PM PDT 24 288260064 ps
T334 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3816523770 Jul 30 06:46:29 PM PDT 24 Jul 30 06:46:35 PM PDT 24 143878624 ps
T66 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2221171178 Jul 30 06:46:22 PM PDT 24 Jul 30 06:46:30 PM PDT 24 2066253013 ps
T335 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1230123581 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:15 PM PDT 24 126180756 ps
T336 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2713836360 Jul 30 06:46:07 PM PDT 24 Jul 30 06:46:13 PM PDT 24 140225618 ps
T337 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.712219265 Jul 30 06:46:28 PM PDT 24 Jul 30 06:46:33 PM PDT 24 820680437 ps
T338 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1772543244 Jul 30 06:46:22 PM PDT 24 Jul 30 06:46:59 PM PDT 24 169634369 ps
T339 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3300109693 Jul 30 06:47:01 PM PDT 24 Jul 30 06:47:08 PM PDT 24 154727146 ps
T340 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.750757513 Jul 30 06:46:37 PM PDT 24 Jul 30 06:46:42 PM PDT 24 467699396 ps
T110 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1036095145 Jul 30 06:46:08 PM PDT 24 Jul 30 06:46:45 PM PDT 24 829197404 ps
T100 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3094092636 Jul 30 06:46:19 PM PDT 24 Jul 30 06:47:30 PM PDT 24 2404314694 ps
T91 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1806052911 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:17 PM PDT 24 598915807 ps
T341 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2902194978 Jul 30 06:46:07 PM PDT 24 Jul 30 06:46:12 PM PDT 24 380772165 ps
T101 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1161899516 Jul 30 06:46:14 PM PDT 24 Jul 30 06:46:52 PM PDT 24 445984125 ps
T342 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2227889306 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:16 PM PDT 24 128250979 ps
T92 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4132543430 Jul 30 06:46:45 PM PDT 24 Jul 30 06:46:51 PM PDT 24 250651992 ps
T67 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.645559284 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:15 PM PDT 24 246042272 ps
T343 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3273924798 Jul 30 06:46:11 PM PDT 24 Jul 30 06:46:15 PM PDT 24 640043486 ps
T68 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2261180587 Jul 30 06:46:12 PM PDT 24 Jul 30 06:46:17 PM PDT 24 948452427 ps
T344 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2608936767 Jul 30 06:46:07 PM PDT 24 Jul 30 06:46:13 PM PDT 24 249961244 ps
T345 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.884553964 Jul 30 06:46:13 PM PDT 24 Jul 30 06:46:18 PM PDT 24 403782045 ps
T69 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1115735343 Jul 30 06:46:11 PM PDT 24 Jul 30 06:46:16 PM PDT 24 132843678 ps
T346 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.884075634 Jul 30 06:46:51 PM PDT 24 Jul 30 06:46:55 PM PDT 24 177428730 ps
T70 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.377148230 Jul 30 06:46:27 PM PDT 24 Jul 30 06:46:34 PM PDT 24 268841833 ps
T71 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2211072956 Jul 30 06:46:11 PM PDT 24 Jul 30 06:46:15 PM PDT 24 90410850 ps
T347 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4172297505 Jul 30 06:46:15 PM PDT 24 Jul 30 06:46:23 PM PDT 24 85806326 ps
T348 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3006411840 Jul 30 06:46:11 PM PDT 24 Jul 30 06:46:16 PM PDT 24 128651000 ps
T349 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2442569585 Jul 30 06:46:12 PM PDT 24 Jul 30 06:46:19 PM PDT 24 249570173 ps
T72 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3948504562 Jul 30 06:46:12 PM PDT 24 Jul 30 06:46:17 PM PDT 24 499167014 ps
T350 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3420114233 Jul 30 06:46:17 PM PDT 24 Jul 30 06:46:24 PM PDT 24 86961964 ps
T351 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.571921535 Jul 30 06:46:13 PM PDT 24 Jul 30 06:46:18 PM PDT 24 272333243 ps
T352 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1231768804 Jul 30 06:46:32 PM PDT 24 Jul 30 06:46:38 PM PDT 24 144618134 ps
T353 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2597512803 Jul 30 06:46:10 PM PDT 24 Jul 30 06:46:15 PM PDT 24 333477634 ps
T354 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2728145996 Jul 30 06:46:19 PM PDT 24 Jul 30 06:47:26 PM PDT 24 1175242225 ps
T355 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3352591982 Jul 30 06:46:11 PM PDT 24 Jul 30 06:46:17 PM PDT 24 131640605 ps
T356 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2851539863 Jul 30 06:46:14 PM PDT 24 Jul 30 06:46:19 PM PDT 24 88912613 ps
T357 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2520513000 Jul 30 06:46:21 PM PDT 24 Jul 30 06:46:27 PM PDT 24 137335328 ps
T103 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.496520627 Jul 30 06:46:27 PM PDT 24 Jul 30 06:47:37 PM PDT 24 215937942 ps
T358 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3721947298 Jul 30 06:46:20 PM PDT 24 Jul 30 06:46:26 PM PDT 24 332760060 ps
T359 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1830879592 Jul 30 06:46:10 PM PDT 24 Jul 30 06:46:15 PM PDT 24 182843638 ps
T360 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2617127941 Jul 30 06:46:38 PM PDT 24 Jul 30 06:46:46 PM PDT 24 501127736 ps
T104 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4083819559 Jul 30 06:46:46 PM PDT 24 Jul 30 06:47:55 PM PDT 24 227067081 ps
T80 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2903781217 Jul 30 06:46:25 PM PDT 24 Jul 30 06:46:44 PM PDT 24 1486641892 ps
T361 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1764016011 Jul 30 06:46:10 PM PDT 24 Jul 30 06:46:18 PM PDT 24 1612563641 ps
T362 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3289034193 Jul 30 06:46:10 PM PDT 24 Jul 30 06:46:15 PM PDT 24 512434824 ps
T106 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2738222694 Jul 30 06:46:11 PM PDT 24 Jul 30 06:47:20 PM PDT 24 477413468 ps
T363 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4226364601 Jul 30 06:46:26 PM PDT 24 Jul 30 06:46:30 PM PDT 24 175254989 ps
T364 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2840490263 Jul 30 06:46:23 PM PDT 24 Jul 30 06:46:33 PM PDT 24 365457403 ps
T365 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2629684343 Jul 30 06:46:18 PM PDT 24 Jul 30 06:46:24 PM PDT 24 261688336 ps
T81 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1612249122 Jul 30 06:46:21 PM PDT 24 Jul 30 06:46:26 PM PDT 24 131827353 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3802383340 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:15 PM PDT 24 517859622 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.934937818 Jul 30 06:46:12 PM PDT 24 Jul 30 06:46:17 PM PDT 24 136713852 ps
T82 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1897890628 Jul 30 06:46:10 PM PDT 24 Jul 30 06:46:38 PM PDT 24 567264801 ps
T83 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4266093135 Jul 30 06:46:18 PM PDT 24 Jul 30 06:46:24 PM PDT 24 519358868 ps
T368 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.825601297 Jul 30 06:46:20 PM PDT 24 Jul 30 06:46:25 PM PDT 24 1031964487 ps
T369 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2010051675 Jul 30 06:46:05 PM PDT 24 Jul 30 06:46:10 PM PDT 24 1664899924 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1991243274 Jul 30 06:46:10 PM PDT 24 Jul 30 06:46:16 PM PDT 24 132697210 ps
T371 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3022593978 Jul 30 06:46:12 PM PDT 24 Jul 30 06:46:17 PM PDT 24 568231447 ps
T84 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4164802995 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:37 PM PDT 24 541518120 ps
T372 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2890866291 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:21 PM PDT 24 496385565 ps
T85 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2495690506 Jul 30 06:46:21 PM PDT 24 Jul 30 06:46:40 PM PDT 24 2990011912 ps
T373 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2222802559 Jul 30 06:46:28 PM PDT 24 Jul 30 06:46:35 PM PDT 24 1401828984 ps
T107 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2784023263 Jul 30 06:46:21 PM PDT 24 Jul 30 06:47:30 PM PDT 24 626793850 ps
T374 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2930962120 Jul 30 06:46:23 PM PDT 24 Jul 30 06:46:27 PM PDT 24 1452000461 ps
T375 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2170773375 Jul 30 06:46:08 PM PDT 24 Jul 30 06:46:18 PM PDT 24 292087916 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1278444768 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:15 PM PDT 24 272652639 ps
T377 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4072106731 Jul 30 06:46:33 PM PDT 24 Jul 30 06:46:39 PM PDT 24 137116484 ps
T378 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1670940305 Jul 30 06:46:08 PM PDT 24 Jul 30 06:46:13 PM PDT 24 128995988 ps
T379 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4049601357 Jul 30 06:46:13 PM PDT 24 Jul 30 06:46:21 PM PDT 24 2169510610 ps
T86 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.506250740 Jul 30 06:46:32 PM PDT 24 Jul 30 06:46:37 PM PDT 24 88900224 ps
T380 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2304530603 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:46 PM PDT 24 640603531 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3097426469 Jul 30 06:46:15 PM PDT 24 Jul 30 06:46:19 PM PDT 24 321542473 ps
T382 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1966887411 Jul 30 06:46:07 PM PDT 24 Jul 30 06:46:13 PM PDT 24 105759726 ps
T102 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2555884291 Jul 30 06:46:20 PM PDT 24 Jul 30 06:47:29 PM PDT 24 1125094571 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2136320135 Jul 30 06:46:21 PM PDT 24 Jul 30 06:46:25 PM PDT 24 89275938 ps
T384 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3055515204 Jul 30 06:46:12 PM PDT 24 Jul 30 06:46:40 PM PDT 24 548066002 ps
T385 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3382520985 Jul 30 06:46:11 PM PDT 24 Jul 30 06:46:19 PM PDT 24 493880686 ps
T386 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.709996781 Jul 30 06:46:07 PM PDT 24 Jul 30 06:46:12 PM PDT 24 154550945 ps
T387 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1910612919 Jul 30 06:46:12 PM PDT 24 Jul 30 06:46:19 PM PDT 24 551321401 ps
T388 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1148142119 Jul 30 06:46:01 PM PDT 24 Jul 30 06:46:05 PM PDT 24 348219843 ps
T108 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.705299668 Jul 30 06:46:33 PM PDT 24 Jul 30 06:47:43 PM PDT 24 950573454 ps
T389 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3723700526 Jul 30 06:46:50 PM PDT 24 Jul 30 06:46:55 PM PDT 24 131278650 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3808284205 Jul 30 06:46:05 PM PDT 24 Jul 30 06:46:24 PM PDT 24 720501081 ps
T391 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.267707428 Jul 30 06:46:30 PM PDT 24 Jul 30 06:46:35 PM PDT 24 128001937 ps
T392 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2949989185 Jul 30 06:46:03 PM PDT 24 Jul 30 06:46:40 PM PDT 24 740327868 ps
T87 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3036916265 Jul 30 06:46:27 PM PDT 24 Jul 30 06:46:32 PM PDT 24 127614113 ps
T393 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3721452339 Jul 30 06:45:58 PM PDT 24 Jul 30 06:46:04 PM PDT 24 332822090 ps
T394 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.345727234 Jul 30 06:46:19 PM PDT 24 Jul 30 06:46:26 PM PDT 24 139526772 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4165436235 Jul 30 06:46:08 PM PDT 24 Jul 30 06:46:18 PM PDT 24 574319012 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2505103825 Jul 30 06:46:00 PM PDT 24 Jul 30 06:46:07 PM PDT 24 145498511 ps
T111 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1164672781 Jul 30 06:46:21 PM PDT 24 Jul 30 06:47:32 PM PDT 24 591103729 ps
T397 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1282367752 Jul 30 06:46:14 PM PDT 24 Jul 30 06:46:21 PM PDT 24 104304120 ps
T398 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.503897419 Jul 30 06:46:11 PM PDT 24 Jul 30 06:46:17 PM PDT 24 1795018538 ps
T399 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2274742845 Jul 30 06:46:17 PM PDT 24 Jul 30 06:46:22 PM PDT 24 862213222 ps
T400 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3900444981 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:16 PM PDT 24 98653939 ps
T401 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3207044401 Jul 30 06:46:09 PM PDT 24 Jul 30 06:46:14 PM PDT 24 499685648 ps
T402 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3642054453 Jul 30 06:46:17 PM PDT 24 Jul 30 06:46:21 PM PDT 24 347562775 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2620207941 Jul 30 06:46:08 PM PDT 24 Jul 30 06:46:13 PM PDT 24 542351715 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3318706009 Jul 30 06:46:01 PM PDT 24 Jul 30 06:46:09 PM PDT 24 556427115 ps
T405 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4173804058 Jul 30 06:46:11 PM PDT 24 Jul 30 06:46:20 PM PDT 24 521578983 ps
T406 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.428602127 Jul 30 06:46:22 PM PDT 24 Jul 30 06:46:27 PM PDT 24 195737838 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2300501720 Jul 30 06:46:12 PM PDT 24 Jul 30 06:46:35 PM PDT 24 2349293099 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2650054023 Jul 30 06:46:10 PM PDT 24 Jul 30 06:46:20 PM PDT 24 417382106 ps
T408 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.847993393 Jul 30 06:46:11 PM PDT 24 Jul 30 06:46:16 PM PDT 24 173054157 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3527181591 Jul 30 06:46:07 PM PDT 24 Jul 30 06:46:12 PM PDT 24 281958116 ps
T410 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1454985719 Jul 30 06:46:18 PM PDT 24 Jul 30 06:46:29 PM PDT 24 4117614967 ps
T411 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3079076483 Jul 30 06:46:14 PM PDT 24 Jul 30 06:46:18 PM PDT 24 99366909 ps
T109 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1165879215 Jul 30 06:46:24 PM PDT 24 Jul 30 06:47:34 PM PDT 24 525211921 ps
T412 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.471701825 Jul 30 06:46:10 PM PDT 24 Jul 30 06:46:18 PM PDT 24 137046710 ps
T413 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.366324856 Jul 30 06:46:12 PM PDT 24 Jul 30 06:46:16 PM PDT 24 168365458 ps

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.2295226154
Short name T2
Test name
Test status
Simulation time 117790848561 ps
CPU time 1796.35 seconds
Started Jul 30 06:18:53 PM PDT 24
Finished Jul 30 06:48:49 PM PDT 24
Peak memory 239184 kb
Host smart-058ee644-34f7-4e52-896a-f4a4de0cae4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295226154 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.2295226154
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3158773885
Short name T21
Test name
Test status
Simulation time 35827790745 ps
CPU time 177.13 seconds
Started Jul 30 06:19:04 PM PDT 24
Finished Jul 30 06:22:01 PM PDT 24
Peak memory 228964 kb
Host smart-f4f6053d-0874-4f30-8641-087451e8ccd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158773885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3158773885
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2164527411
Short name T57
Test name
Test status
Simulation time 795637879 ps
CPU time 65.7 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:47:17 PM PDT 24
Peak memory 219460 kb
Host smart-aa486bde-8749-45a0-9980-a472c8491784
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164527411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2164527411
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3927992982
Short name T14
Test name
Test status
Simulation time 4943753335 ps
CPU time 126.57 seconds
Started Jul 30 06:19:20 PM PDT 24
Finished Jul 30 06:21:27 PM PDT 24
Peak memory 226296 kb
Host smart-388dcbae-2cbf-49df-b48a-a90389c8a676
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927992982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3927992982
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1497782606
Short name T13
Test name
Test status
Simulation time 120032120504 ps
CPU time 2320.51 seconds
Started Jul 30 06:19:32 PM PDT 24
Finished Jul 30 06:58:13 PM PDT 24
Peak memory 245380 kb
Host smart-119c866a-76ea-4e65-aceb-c26a9e8f227c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497782606 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1497782606
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1732271440
Short name T23
Test name
Test status
Simulation time 743964437 ps
CPU time 52.71 seconds
Started Jul 30 06:18:26 PM PDT 24
Finished Jul 30 06:19:19 PM PDT 24
Peak memory 237468 kb
Host smart-6106275e-b38f-4159-9514-d09274f11dba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732271440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1732271440
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.180279692
Short name T1
Test name
Test status
Simulation time 309904800 ps
CPU time 8.89 seconds
Started Jul 30 06:19:11 PM PDT 24
Finished Jul 30 06:19:20 PM PDT 24
Peak memory 212172 kb
Host smart-30d4369f-e58a-4c05-a4c3-523acde75fc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180279692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.180279692
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2436497802
Short name T63
Test name
Test status
Simulation time 376538992 ps
CPU time 18.82 seconds
Started Jul 30 06:46:44 PM PDT 24
Finished Jul 30 06:47:03 PM PDT 24
Peak memory 211440 kb
Host smart-324dd06e-f42d-4c31-8682-9b9ad8578262
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436497802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2436497802
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1161899516
Short name T101
Test name
Test status
Simulation time 445984125 ps
CPU time 37.31 seconds
Started Jul 30 06:46:14 PM PDT 24
Finished Jul 30 06:46:52 PM PDT 24
Peak memory 211584 kb
Host smart-5515a1f9-bb53-451f-b952-c07d772dffb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161899516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1161899516
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3360849963
Short name T41
Test name
Test status
Simulation time 986319585 ps
CPU time 15.74 seconds
Started Jul 30 06:19:06 PM PDT 24
Finished Jul 30 06:19:22 PM PDT 24
Peak memory 212976 kb
Host smart-964929e8-0f3d-4124-acaa-69259b89f0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360849963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3360849963
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4013652575
Short name T121
Test name
Test status
Simulation time 379006636 ps
CPU time 4.34 seconds
Started Jul 30 06:18:44 PM PDT 24
Finished Jul 30 06:18:48 PM PDT 24
Peak memory 212060 kb
Host smart-ef88f10f-aa66-4c21-b2cf-5c703b38d4c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013652575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4013652575
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2050053987
Short name T31
Test name
Test status
Simulation time 255434952 ps
CPU time 11.22 seconds
Started Jul 30 06:18:42 PM PDT 24
Finished Jul 30 06:18:54 PM PDT 24
Peak memory 212952 kb
Host smart-c1401e01-ee58-440b-a2a0-8c412120aa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050053987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2050053987
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1148911782
Short name T48
Test name
Test status
Simulation time 1905944855 ps
CPU time 11.4 seconds
Started Jul 30 06:19:33 PM PDT 24
Finished Jul 30 06:19:44 PM PDT 24
Peak memory 212972 kb
Host smart-62c5898a-9adf-494c-a58e-6bc068eb6387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148911782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1148911782
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.496520627
Short name T103
Test name
Test status
Simulation time 215937942 ps
CPU time 69.78 seconds
Started Jul 30 06:46:27 PM PDT 24
Finished Jul 30 06:47:37 PM PDT 24
Peak memory 219608 kb
Host smart-2a7c1473-e872-4b18-ab7a-7c98348ba53e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496520627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.496520627
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2300501720
Short name T88
Test name
Test status
Simulation time 2349293099 ps
CPU time 22.41 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:35 PM PDT 24
Peak memory 211520 kb
Host smart-423b76c4-e97e-46aa-9dcc-880b93706e65
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300501720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2300501720
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3093322099
Short name T30
Test name
Test status
Simulation time 2657616562 ps
CPU time 134.77 seconds
Started Jul 30 06:18:21 PM PDT 24
Finished Jul 30 06:20:36 PM PDT 24
Peak memory 234448 kb
Host smart-960824e1-fd97-416d-9479-279c64917658
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093322099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3093322099
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1164672781
Short name T111
Test name
Test status
Simulation time 591103729 ps
CPU time 70.85 seconds
Started Jul 30 06:46:21 PM PDT 24
Finished Jul 30 06:47:32 PM PDT 24
Peak memory 212216 kb
Host smart-3ece1db4-9606-4d02-a2d2-0199bfb2f77f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164672781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1164672781
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2555884291
Short name T102
Test name
Test status
Simulation time 1125094571 ps
CPU time 68.6 seconds
Started Jul 30 06:46:20 PM PDT 24
Finished Jul 30 06:47:29 PM PDT 24
Peak memory 213068 kb
Host smart-0647a1c8-bf9b-4073-99cf-c061407d46b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555884291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2555884291
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1786896054
Short name T12
Test name
Test status
Simulation time 222298723220 ps
CPU time 2295.77 seconds
Started Jul 30 06:18:49 PM PDT 24
Finished Jul 30 06:57:05 PM PDT 24
Peak memory 242924 kb
Host smart-726c715d-edb9-4c6f-b4c6-52820440685d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786896054 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1786896054
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2064173941
Short name T15
Test name
Test status
Simulation time 87362244498 ps
CPU time 1636.9 seconds
Started Jul 30 06:19:22 PM PDT 24
Finished Jul 30 06:46:39 PM PDT 24
Peak memory 235240 kb
Host smart-c6b3746e-692b-4932-8a92-1db9a371e7c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064173941 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2064173941
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2629684343
Short name T365
Test name
Test status
Simulation time 261688336 ps
CPU time 5.17 seconds
Started Jul 30 06:46:18 PM PDT 24
Finished Jul 30 06:46:24 PM PDT 24
Peak memory 218072 kb
Host smart-3dca1f35-b694-4c57-b31a-e6404c5026c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629684343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2629684343
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2136320135
Short name T383
Test name
Test status
Simulation time 89275938 ps
CPU time 4.18 seconds
Started Jul 30 06:46:21 PM PDT 24
Finished Jul 30 06:46:25 PM PDT 24
Peak memory 211120 kb
Host smart-06c65303-3d3f-4725-8fe1-59c8dd5f389a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136320135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2136320135
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3634455294
Short name T62
Test name
Test status
Simulation time 87304627 ps
CPU time 5.82 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:14 PM PDT 24
Peak memory 211340 kb
Host smart-3cfb4ea0-106e-42b9-afd5-4ee4c6434dfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634455294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3634455294
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.503897419
Short name T398
Test name
Test status
Simulation time 1795018538 ps
CPU time 5.97 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:17 PM PDT 24
Peak memory 219256 kb
Host smart-58dd0113-2076-46f1-8b14-4828cd39cb52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503897419 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.503897419
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3948504562
Short name T72
Test name
Test status
Simulation time 499167014 ps
CPU time 5.04 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:17 PM PDT 24
Peak memory 210952 kb
Host smart-0346dcde-e134-4994-aa1c-7942b1ef798b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948504562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3948504562
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2010051675
Short name T369
Test name
Test status
Simulation time 1664899924 ps
CPU time 4.2 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:10 PM PDT 24
Peak memory 211252 kb
Host smart-6dfae5f6-0282-4b11-9c8f-a61d9ccd220a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010051675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2010051675
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3858989505
Short name T327
Test name
Test status
Simulation time 1554006932 ps
CPU time 5.01 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:14 PM PDT 24
Peak memory 211244 kb
Host smart-06561a5a-d027-4655-a8c0-909c40218592
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858989505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3858989505
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1806052911
Short name T91
Test name
Test status
Simulation time 598915807 ps
CPU time 6.89 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:17 PM PDT 24
Peak memory 211372 kb
Host smart-1793602d-e253-4ba2-bffe-6814394092fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806052911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1806052911
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1282367752
Short name T397
Test name
Test status
Simulation time 104304120 ps
CPU time 7.57 seconds
Started Jul 30 06:46:14 PM PDT 24
Finished Jul 30 06:46:21 PM PDT 24
Peak memory 219680 kb
Host smart-51cd55d1-f716-4d25-87ef-683dbda61de7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282367752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1282367752
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1600286859
Short name T105
Test name
Test status
Simulation time 687550008 ps
CPU time 40.38 seconds
Started Jul 30 06:46:06 PM PDT 24
Finished Jul 30 06:46:46 PM PDT 24
Peak memory 211532 kb
Host smart-9329008a-29ba-43a9-9dc7-0db4edc017a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600286859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1600286859
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3221177884
Short name T64
Test name
Test status
Simulation time 131640013 ps
CPU time 5.02 seconds
Started Jul 30 06:46:14 PM PDT 24
Finished Jul 30 06:46:19 PM PDT 24
Peak memory 210988 kb
Host smart-78c0447a-7c08-4cc5-907e-e1773a6739a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221177884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3221177884
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3022593978
Short name T371
Test name
Test status
Simulation time 568231447 ps
CPU time 5.28 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:17 PM PDT 24
Peak memory 218308 kb
Host smart-af945586-a12e-4eeb-9a4f-1a9816ff4042
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022593978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3022593978
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.471701825
Short name T412
Test name
Test status
Simulation time 137046710 ps
CPU time 8.09 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:18 PM PDT 24
Peak memory 211152 kb
Host smart-3df456db-81db-4a3a-a20f-ab70d7751e29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471701825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.471701825
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3300109693
Short name T339
Test name
Test status
Simulation time 154727146 ps
CPU time 5.97 seconds
Started Jul 30 06:47:01 PM PDT 24
Finished Jul 30 06:47:08 PM PDT 24
Peak memory 214532 kb
Host smart-6a4bfb97-f7bb-4ea4-83bd-57e47a90dce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300109693 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3300109693
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1230123581
Short name T335
Test name
Test status
Simulation time 126180756 ps
CPU time 5.02 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 211284 kb
Host smart-13a20fa0-877a-45b3-a5c6-09e45cb5104a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230123581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1230123581
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2359666209
Short name T326
Test name
Test status
Simulation time 168526177 ps
CPU time 4.07 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 211252 kb
Host smart-41ef5572-a19b-4ef8-895b-9664b933f285
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359666209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2359666209
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.571921535
Short name T351
Test name
Test status
Simulation time 272333243 ps
CPU time 4.89 seconds
Started Jul 30 06:46:13 PM PDT 24
Finished Jul 30 06:46:18 PM PDT 24
Peak memory 211084 kb
Host smart-cede6139-837c-46fd-bc57-c2286fba699c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571921535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
571921535
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1897890628
Short name T82
Test name
Test status
Simulation time 567264801 ps
CPU time 27.68 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:38 PM PDT 24
Peak memory 211444 kb
Host smart-74177aec-6b64-4cbf-810d-1f0289e24a7b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897890628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1897890628
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2608936767
Short name T344
Test name
Test status
Simulation time 249961244 ps
CPU time 5.16 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 211336 kb
Host smart-f6ce09b1-6fea-4c9c-b95e-e154b9253737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608936767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2608936767
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2227889306
Short name T342
Test name
Test status
Simulation time 128250979 ps
CPU time 7.2 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 216124 kb
Host smart-40268964-d77f-459c-8c16-81ed3fa0f928
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227889306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2227889306
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3816523770
Short name T334
Test name
Test status
Simulation time 143878624 ps
CPU time 5.8 seconds
Started Jul 30 06:46:29 PM PDT 24
Finished Jul 30 06:46:35 PM PDT 24
Peak memory 213480 kb
Host smart-59e48b25-aa56-440f-b6b9-11214a0227cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816523770 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3816523770
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.1115735343
Short name T69
Test name
Test status
Simulation time 132843678 ps
CPU time 5.23 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 211372 kb
Host smart-4f85ec3c-9fed-4a7b-85ee-4fe4359466b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115735343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.1115735343
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3900444981
Short name T400
Test name
Test status
Simulation time 98653939 ps
CPU time 6.23 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 211336 kb
Host smart-98e90446-f6e8-441c-8157-7e7a2f5e8085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900444981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3900444981
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4165436235
Short name T395
Test name
Test status
Simulation time 574319012 ps
CPU time 8.76 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:18 PM PDT 24
Peak memory 216648 kb
Host smart-4bc81a2c-9ffc-450c-b33a-830bf9110b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165436235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4165436235
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1264621355
Short name T99
Test name
Test status
Simulation time 576766079 ps
CPU time 67.94 seconds
Started Jul 30 06:46:31 PM PDT 24
Finished Jul 30 06:47:39 PM PDT 24
Peak memory 219584 kb
Host smart-a6c94c9d-dda5-4d31-ae21-d043834124df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264621355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1264621355
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4049601357
Short name T379
Test name
Test status
Simulation time 2169510610 ps
CPU time 7.96 seconds
Started Jul 30 06:46:13 PM PDT 24
Finished Jul 30 06:46:21 PM PDT 24
Peak memory 219704 kb
Host smart-b6dde3f4-798a-4bf1-b2f0-fba0dda7b198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049601357 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4049601357
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4226364601
Short name T363
Test name
Test status
Simulation time 175254989 ps
CPU time 4.23 seconds
Started Jul 30 06:46:26 PM PDT 24
Finished Jul 30 06:46:30 PM PDT 24
Peak memory 218104 kb
Host smart-9419a902-99e3-45d1-bb03-2073aa27c4de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226364601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4226364601
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3055515204
Short name T384
Test name
Test status
Simulation time 548066002 ps
CPU time 27.8 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:40 PM PDT 24
Peak memory 211440 kb
Host smart-7e9303af-b5df-45fb-a2d3-097071669bad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055515204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3055515204
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1670940305
Short name T378
Test name
Test status
Simulation time 128995988 ps
CPU time 5.23 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 211468 kb
Host smart-81307e52-cf08-4a75-8ca5-b7bf90050330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670940305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1670940305
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4172297505
Short name T347
Test name
Test status
Simulation time 85806326 ps
CPU time 7.89 seconds
Started Jul 30 06:46:15 PM PDT 24
Finished Jul 30 06:46:23 PM PDT 24
Peak memory 219684 kb
Host smart-e73d1685-5e23-48d6-8632-f4db25b70917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172297505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4172297505
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1830879592
Short name T359
Test name
Test status
Simulation time 182843638 ps
CPU time 4.3 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 213872 kb
Host smart-4cc89f6e-885c-4bbd-acb4-91235713fa04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830879592 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1830879592
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.506250740
Short name T86
Test name
Test status
Simulation time 88900224 ps
CPU time 4.29 seconds
Started Jul 30 06:46:32 PM PDT 24
Finished Jul 30 06:46:37 PM PDT 24
Peak memory 211352 kb
Host smart-4b673a3b-a962-4da4-9371-a5608ccb0a5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506250740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.506250740
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1696802289
Short name T89
Test name
Test status
Simulation time 733337957 ps
CPU time 5.29 seconds
Started Jul 30 06:46:19 PM PDT 24
Finished Jul 30 06:46:25 PM PDT 24
Peak memory 211376 kb
Host smart-5a590828-6a46-4995-a1a3-aae553b90481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696802289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1696802289
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.146174763
Short name T331
Test name
Test status
Simulation time 89629041 ps
CPU time 6.01 seconds
Started Jul 30 06:46:20 PM PDT 24
Finished Jul 30 06:46:26 PM PDT 24
Peak memory 217268 kb
Host smart-9eac5f5b-8ccc-4164-97ea-15f17fb489af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146174763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.146174763
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3094092636
Short name T100
Test name
Test status
Simulation time 2404314694 ps
CPU time 70.62 seconds
Started Jul 30 06:46:19 PM PDT 24
Finished Jul 30 06:47:30 PM PDT 24
Peak memory 219644 kb
Host smart-9eb87beb-b0cc-4234-9786-a326990039ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094092636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3094092636
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2930962120
Short name T374
Test name
Test status
Simulation time 1452000461 ps
CPU time 4.38 seconds
Started Jul 30 06:46:23 PM PDT 24
Finished Jul 30 06:46:27 PM PDT 24
Peak memory 219624 kb
Host smart-0da320b2-17d5-41a2-a6b1-588c10dbdd5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930962120 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2930962120
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.712219265
Short name T337
Test name
Test status
Simulation time 820680437 ps
CPU time 5.08 seconds
Started Jul 30 06:46:28 PM PDT 24
Finished Jul 30 06:46:33 PM PDT 24
Peak memory 211372 kb
Host smart-2e94aa6b-52e8-4862-b120-9db9aff787e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712219265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.712219265
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3182611241
Short name T61
Test name
Test status
Simulation time 88367818 ps
CPU time 4.44 seconds
Started Jul 30 06:46:17 PM PDT 24
Finished Jul 30 06:46:21 PM PDT 24
Peak memory 211356 kb
Host smart-96f8ac4d-a162-44b7-ba5c-a27b074dfd5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182611241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3182611241
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.4173804058
Short name T405
Test name
Test status
Simulation time 521578983 ps
CPU time 8.96 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:20 PM PDT 24
Peak memory 216704 kb
Host smart-3a900727-9285-4bfa-b021-5faaaabffcfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173804058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.4173804058
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4072106731
Short name T377
Test name
Test status
Simulation time 137116484 ps
CPU time 5.87 seconds
Started Jul 30 06:46:33 PM PDT 24
Finished Jul 30 06:46:39 PM PDT 24
Peak memory 219636 kb
Host smart-fe93a535-461c-41c3-be6e-2303fb26903a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072106731 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4072106731
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3079076483
Short name T411
Test name
Test status
Simulation time 99366909 ps
CPU time 4.09 seconds
Started Jul 30 06:46:14 PM PDT 24
Finished Jul 30 06:46:18 PM PDT 24
Peak memory 211288 kb
Host smart-1cbec5ac-65df-4e26-9841-ba2540c6e5bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079076483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3079076483
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2851539863
Short name T356
Test name
Test status
Simulation time 88912613 ps
CPU time 4.36 seconds
Started Jul 30 06:46:14 PM PDT 24
Finished Jul 30 06:46:19 PM PDT 24
Peak memory 211376 kb
Host smart-5969f2ef-1408-48f2-b2da-dcb282ff1c64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851539863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2851539863
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1454985719
Short name T410
Test name
Test status
Simulation time 4117614967 ps
CPU time 10.64 seconds
Started Jul 30 06:46:18 PM PDT 24
Finished Jul 30 06:46:29 PM PDT 24
Peak memory 219740 kb
Host smart-166bb045-b054-4214-841e-d68b88cc563d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454985719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1454985719
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2728145996
Short name T354
Test name
Test status
Simulation time 1175242225 ps
CPU time 66.58 seconds
Started Jul 30 06:46:19 PM PDT 24
Finished Jul 30 06:47:26 PM PDT 24
Peak memory 213168 kb
Host smart-f3572c56-f86f-4d49-9fab-f7fa939b57c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728145996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2728145996
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2520513000
Short name T357
Test name
Test status
Simulation time 137335328 ps
CPU time 6.06 seconds
Started Jul 30 06:46:21 PM PDT 24
Finished Jul 30 06:46:27 PM PDT 24
Peak memory 219604 kb
Host smart-090b32e9-5283-4d1e-81b4-75194ad72fb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520513000 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2520513000
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3036916265
Short name T87
Test name
Test status
Simulation time 127614113 ps
CPU time 5.12 seconds
Started Jul 30 06:46:27 PM PDT 24
Finished Jul 30 06:46:32 PM PDT 24
Peak memory 211312 kb
Host smart-a840fb01-7470-4de9-b6bc-8324095de888
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036916265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3036916265
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.4168351742
Short name T60
Test name
Test status
Simulation time 263409520 ps
CPU time 6.82 seconds
Started Jul 30 06:46:19 PM PDT 24
Finished Jul 30 06:46:25 PM PDT 24
Peak memory 219540 kb
Host smart-a9910f99-58a4-4dc8-9a07-cc915f13f5a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168351742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.4168351742
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3721947298
Short name T358
Test name
Test status
Simulation time 332760060 ps
CPU time 6.65 seconds
Started Jul 30 06:46:20 PM PDT 24
Finished Jul 30 06:46:26 PM PDT 24
Peak memory 219640 kb
Host smart-ad01cb3b-58cc-4268-95aa-9e8ecfb4f93a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721947298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3721947298
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.428602127
Short name T406
Test name
Test status
Simulation time 195737838 ps
CPU time 5.09 seconds
Started Jul 30 06:46:22 PM PDT 24
Finished Jul 30 06:46:27 PM PDT 24
Peak memory 215784 kb
Host smart-7dd02dc8-0b09-4cae-b318-0e530ffbeb4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428602127 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.428602127
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4266093135
Short name T83
Test name
Test status
Simulation time 519358868 ps
CPU time 5.15 seconds
Started Jul 30 06:46:18 PM PDT 24
Finished Jul 30 06:46:24 PM PDT 24
Peak memory 218112 kb
Host smart-4186f1fd-4ad5-48e6-9b7e-951e7f0374f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266093135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4266093135
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.377148230
Short name T70
Test name
Test status
Simulation time 268841833 ps
CPU time 6.85 seconds
Started Jul 30 06:46:27 PM PDT 24
Finished Jul 30 06:46:34 PM PDT 24
Peak memory 211576 kb
Host smart-a5c29480-ac0d-48c6-bf10-4b21f0ef26da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377148230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.377148230
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3306654702
Short name T329
Test name
Test status
Simulation time 1827236841 ps
CPU time 12.58 seconds
Started Jul 30 06:46:17 PM PDT 24
Finished Jul 30 06:46:30 PM PDT 24
Peak memory 216776 kb
Host smart-3bac89ab-ea2c-4039-84ac-1b337fb6686d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306654702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3306654702
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.705299668
Short name T108
Test name
Test status
Simulation time 950573454 ps
CPU time 69.87 seconds
Started Jul 30 06:46:33 PM PDT 24
Finished Jul 30 06:47:43 PM PDT 24
Peak memory 212924 kb
Host smart-5d07c17d-53ee-4a73-ad28-faef3f482e87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705299668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.705299668
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1231768804
Short name T352
Test name
Test status
Simulation time 144618134 ps
CPU time 6.08 seconds
Started Jul 30 06:46:32 PM PDT 24
Finished Jul 30 06:46:38 PM PDT 24
Peak memory 219692 kb
Host smart-beb56c5d-add4-4fb6-9fc9-3da3ff1cbed5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231768804 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1231768804
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1612249122
Short name T81
Test name
Test status
Simulation time 131827353 ps
CPU time 5.13 seconds
Started Jul 30 06:46:21 PM PDT 24
Finished Jul 30 06:46:26 PM PDT 24
Peak memory 211352 kb
Host smart-830f3c0d-a426-4057-934d-6b60e580825e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612249122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1612249122
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.345727234
Short name T394
Test name
Test status
Simulation time 139526772 ps
CPU time 6.95 seconds
Started Jul 30 06:46:19 PM PDT 24
Finished Jul 30 06:46:26 PM PDT 24
Peak memory 211612 kb
Host smart-a865b759-2c07-4807-9ed4-0f5cfe71d5c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345727234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.345727234
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2222802559
Short name T373
Test name
Test status
Simulation time 1401828984 ps
CPU time 7.01 seconds
Started Jul 30 06:46:28 PM PDT 24
Finished Jul 30 06:46:35 PM PDT 24
Peak memory 219648 kb
Host smart-63cbd897-5b66-4ce3-a6af-c2b99ec6818d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222802559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2222802559
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3268001370
Short name T56
Test name
Test status
Simulation time 844430470 ps
CPU time 70.5 seconds
Started Jul 30 06:46:36 PM PDT 24
Finished Jul 30 06:47:47 PM PDT 24
Peak memory 212148 kb
Host smart-8fce53be-cd8f-4d00-96c3-26177170ac30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268001370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3268001370
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.750757513
Short name T340
Test name
Test status
Simulation time 467699396 ps
CPU time 4.55 seconds
Started Jul 30 06:46:37 PM PDT 24
Finished Jul 30 06:46:42 PM PDT 24
Peak memory 219512 kb
Host smart-d0590061-9173-4256-9219-4e44ea7a9d0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750757513 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.750757513
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.267707428
Short name T391
Test name
Test status
Simulation time 128001937 ps
CPU time 5.08 seconds
Started Jul 30 06:46:30 PM PDT 24
Finished Jul 30 06:46:35 PM PDT 24
Peak memory 218272 kb
Host smart-c3334922-671f-487e-b0c8-9d1c87c0ed06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267707428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.267707428
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2495690506
Short name T85
Test name
Test status
Simulation time 2990011912 ps
CPU time 18.79 seconds
Started Jul 30 06:46:21 PM PDT 24
Finished Jul 30 06:46:40 PM PDT 24
Peak memory 211568 kb
Host smart-97df2065-438c-431d-817c-6731b693323e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495690506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2495690506
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3723700526
Short name T389
Test name
Test status
Simulation time 131278650 ps
CPU time 5.12 seconds
Started Jul 30 06:46:50 PM PDT 24
Finished Jul 30 06:46:55 PM PDT 24
Peak memory 211428 kb
Host smart-8c5921b3-fbdd-4ba2-a589-af4872f230f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723700526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3723700526
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2617127941
Short name T360
Test name
Test status
Simulation time 501127736 ps
CPU time 7.43 seconds
Started Jul 30 06:46:38 PM PDT 24
Finished Jul 30 06:46:46 PM PDT 24
Peak memory 216492 kb
Host smart-13760d57-9726-41e0-9732-33eff0766593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617127941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2617127941
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2784023263
Short name T107
Test name
Test status
Simulation time 626793850 ps
CPU time 69.32 seconds
Started Jul 30 06:46:21 PM PDT 24
Finished Jul 30 06:47:30 PM PDT 24
Peak memory 213080 kb
Host smart-bfc293a5-7fc1-4f80-843f-4e6299456a77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784023263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2784023263
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2346086362
Short name T333
Test name
Test status
Simulation time 554740093 ps
CPU time 5.5 seconds
Started Jul 30 06:46:28 PM PDT 24
Finished Jul 30 06:46:34 PM PDT 24
Peak memory 219648 kb
Host smart-0b7d8d01-c0d2-42b7-a18c-83939ca47ac7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346086362 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2346086362
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.884075634
Short name T346
Test name
Test status
Simulation time 177428730 ps
CPU time 4.26 seconds
Started Jul 30 06:46:51 PM PDT 24
Finished Jul 30 06:46:55 PM PDT 24
Peak memory 211296 kb
Host smart-46b574fa-ca64-44f6-8adf-0ac590296b16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884075634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.884075634
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4132543430
Short name T92
Test name
Test status
Simulation time 250651992 ps
CPU time 5.16 seconds
Started Jul 30 06:46:45 PM PDT 24
Finished Jul 30 06:46:51 PM PDT 24
Peak memory 219008 kb
Host smart-90d22edb-e13a-46e2-93a8-b0e5c25ac58b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132543430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4132543430
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3723067823
Short name T328
Test name
Test status
Simulation time 1034912624 ps
CPU time 7.86 seconds
Started Jul 30 06:46:30 PM PDT 24
Finished Jul 30 06:46:38 PM PDT 24
Peak memory 219692 kb
Host smart-6f978caf-3fa5-4291-9eef-ffa94d35569b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723067823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3723067823
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4083819559
Short name T104
Test name
Test status
Simulation time 227067081 ps
CPU time 69.35 seconds
Started Jul 30 06:46:46 PM PDT 24
Finished Jul 30 06:47:55 PM PDT 24
Peak memory 219652 kb
Host smart-259fcf49-fba3-46bf-b539-b4db8b0a5833
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083819559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4083819559
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2620207941
Short name T403
Test name
Test status
Simulation time 542351715 ps
CPU time 5.16 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 211336 kb
Host smart-87f1be85-2ae2-4ed3-b637-4a3c428ca9ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620207941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2620207941
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1278444768
Short name T376
Test name
Test status
Simulation time 272652639 ps
CPU time 5.41 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 218140 kb
Host smart-3d7c8953-5f8a-4953-974f-a7212000e9ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278444768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1278444768
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.4092890071
Short name T93
Test name
Test status
Simulation time 268266193 ps
CPU time 8.01 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:17 PM PDT 24
Peak memory 211188 kb
Host smart-5b3cff12-1d03-4d36-985a-2e1576fc3b45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092890071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.4092890071
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3289034193
Short name T362
Test name
Test status
Simulation time 512434824 ps
CPU time 5.12 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 219624 kb
Host smart-2df89eff-bea9-4b42-ac9a-d238eed35886
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289034193 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3289034193
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2536909679
Short name T94
Test name
Test status
Simulation time 594741024 ps
CPU time 5.26 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 211380 kb
Host smart-485b81ac-2d30-4f30-8eca-07bec1ae1a2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536909679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2536909679
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3352591982
Short name T355
Test name
Test status
Simulation time 131640605 ps
CPU time 5.01 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:17 PM PDT 24
Peak memory 211252 kb
Host smart-1a76495b-d5bd-403e-9581-f691b26db842
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352591982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3352591982
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3097426469
Short name T381
Test name
Test status
Simulation time 321542473 ps
CPU time 4.13 seconds
Started Jul 30 06:46:15 PM PDT 24
Finished Jul 30 06:46:19 PM PDT 24
Peak memory 211220 kb
Host smart-5e4fe167-fa11-4c4e-b831-b6d7e1d0c0b2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097426469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3097426469
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4164802995
Short name T84
Test name
Test status
Simulation time 541518120 ps
CPU time 26.88 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:37 PM PDT 24
Peak memory 211404 kb
Host smart-3b3cb8fe-dbe4-42e3-94aa-2756d6405b0e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164802995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4164802995
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3802383340
Short name T366
Test name
Test status
Simulation time 517859622 ps
CPU time 5.11 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 211360 kb
Host smart-b00b8127-3295-4d27-a2cf-3df479e43fbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802383340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3802383340
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3721452339
Short name T393
Test name
Test status
Simulation time 332822090 ps
CPU time 6.14 seconds
Started Jul 30 06:45:58 PM PDT 24
Finished Jul 30 06:46:04 PM PDT 24
Peak memory 215332 kb
Host smart-f8bf323a-71c5-4117-b5f8-0021ffe5216f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721452339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3721452339
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2949989185
Short name T392
Test name
Test status
Simulation time 740327868 ps
CPU time 37.01 seconds
Started Jul 30 06:46:03 PM PDT 24
Finished Jul 30 06:46:40 PM PDT 24
Peak memory 219428 kb
Host smart-d9e1cd7e-277e-4cf4-8f15-96102889be50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949989185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2949989185
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.366324856
Short name T413
Test name
Test status
Simulation time 168365458 ps
CPU time 4.16 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 211316 kb
Host smart-0037efd5-b9eb-41f1-97c2-21da43fa4c84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366324856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.366324856
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3642054453
Short name T402
Test name
Test status
Simulation time 347562775 ps
CPU time 4.56 seconds
Started Jul 30 06:46:17 PM PDT 24
Finished Jul 30 06:46:21 PM PDT 24
Peak memory 211328 kb
Host smart-c0aa89ed-c27b-4bce-be9d-47e4bff8e6ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642054453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3642054453
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1764016011
Short name T361
Test name
Test status
Simulation time 1612563641 ps
CPU time 8.21 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:18 PM PDT 24
Peak memory 218328 kb
Host smart-ab734cbd-57a2-4622-972d-fdbe1f431c34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764016011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1764016011
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3527181591
Short name T409
Test name
Test status
Simulation time 281958116 ps
CPU time 4.97 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 216592 kb
Host smart-9f1ff20e-0dbf-43a7-a4f2-0dfdf6721823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527181591 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3527181591
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2261180587
Short name T68
Test name
Test status
Simulation time 948452427 ps
CPU time 5.03 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:17 PM PDT 24
Peak memory 218620 kb
Host smart-e4b3de2f-20ac-438a-9cd3-a76cc4d55671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261180587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2261180587
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3739306156
Short name T330
Test name
Test status
Simulation time 517067698 ps
CPU time 4.84 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 211128 kb
Host smart-09b55484-b15a-4cb2-a61b-73946a6f137a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739306156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3739306156
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3273924798
Short name T343
Test name
Test status
Simulation time 640043486 ps
CPU time 4.1 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 211340 kb
Host smart-343b38b9-36b2-4cbe-b259-0a54cf76181d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273924798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3273924798
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2505103825
Short name T396
Test name
Test status
Simulation time 145498511 ps
CPU time 7.01 seconds
Started Jul 30 06:46:00 PM PDT 24
Finished Jul 30 06:46:07 PM PDT 24
Peak memory 211584 kb
Host smart-c13b819f-4a25-4e68-8e2c-dd95e027124f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505103825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2505103825
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3318706009
Short name T404
Test name
Test status
Simulation time 556427115 ps
CPU time 8.06 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:09 PM PDT 24
Peak memory 219684 kb
Host smart-5178af30-2ba1-41c7-a38e-396e951224a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318706009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3318706009
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2650054023
Short name T407
Test name
Test status
Simulation time 417382106 ps
CPU time 4.21 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:20 PM PDT 24
Peak memory 219456 kb
Host smart-7419ff2a-c352-4482-a26a-97166db00885
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650054023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2650054023
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2221171178
Short name T66
Test name
Test status
Simulation time 2066253013 ps
CPU time 7.82 seconds
Started Jul 30 06:46:22 PM PDT 24
Finished Jul 30 06:46:30 PM PDT 24
Peak memory 211304 kb
Host smart-e70ce6e4-32c0-4af5-a8fb-beae5e7020ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221171178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2221171178
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1910612919
Short name T387
Test name
Test status
Simulation time 551321401 ps
CPU time 6.83 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:19 PM PDT 24
Peak memory 219468 kb
Host smart-603dc044-0949-496a-b14e-91b3ef9209a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910612919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1910612919
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.934937818
Short name T367
Test name
Test status
Simulation time 136713852 ps
CPU time 5.49 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:17 PM PDT 24
Peak memory 213844 kb
Host smart-be018369-30b1-469c-bc09-f38768a4ac1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934937818 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.934937818
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3207044401
Short name T401
Test name
Test status
Simulation time 499685648 ps
CPU time 4.96 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:14 PM PDT 24
Peak memory 218104 kb
Host smart-e2f3e06a-2c52-45a9-bf23-8cb1f5e5b458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207044401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3207044401
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2597512803
Short name T353
Test name
Test status
Simulation time 333477634 ps
CPU time 4.12 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 211228 kb
Host smart-effa0360-0683-40e8-af69-4432d9901f97
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597512803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2597512803
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1148142119
Short name T388
Test name
Test status
Simulation time 348219843 ps
CPU time 4.19 seconds
Started Jul 30 06:46:01 PM PDT 24
Finished Jul 30 06:46:05 PM PDT 24
Peak memory 211424 kb
Host smart-b1de241c-2a78-4c36-843f-9c003497d1c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148142119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1148142119
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2903781217
Short name T80
Test name
Test status
Simulation time 1486641892 ps
CPU time 19.14 seconds
Started Jul 30 06:46:25 PM PDT 24
Finished Jul 30 06:46:44 PM PDT 24
Peak memory 211428 kb
Host smart-f3cd01dc-203f-41e9-86a0-882c9628a125
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903781217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2903781217
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1991243274
Short name T370
Test name
Test status
Simulation time 132697210 ps
CPU time 5.41 seconds
Started Jul 30 06:46:10 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 219008 kb
Host smart-5f5eb040-6d89-4843-90b7-17672cf06d1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991243274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1991243274
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1589202013
Short name T332
Test name
Test status
Simulation time 246372318 ps
CPU time 9.44 seconds
Started Jul 30 06:46:13 PM PDT 24
Finished Jul 30 06:46:23 PM PDT 24
Peak memory 216468 kb
Host smart-df2f0e8f-f500-4ab7-affb-aac65a89afcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589202013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1589202013
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1036095145
Short name T110
Test name
Test status
Simulation time 829197404 ps
CPU time 36.68 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:45 PM PDT 24
Peak memory 219440 kb
Host smart-6b61337d-e306-465c-9d51-4282e4168b48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036095145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1036095145
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1966887411
Short name T382
Test name
Test status
Simulation time 105759726 ps
CPU time 5.23 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 219512 kb
Host smart-4aaaad82-c8c7-4c4c-98d5-4e3e87b0209b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966887411 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1966887411
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2211072956
Short name T71
Test name
Test status
Simulation time 90410850 ps
CPU time 4.11 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 219476 kb
Host smart-eced7c59-b263-4d32-8467-24de9863a3fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211072956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2211072956
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3006411840
Short name T348
Test name
Test status
Simulation time 128651000 ps
CPU time 5.12 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 218792 kb
Host smart-465a96f0-b01f-4750-a304-7e8099564906
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006411840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3006411840
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2170773375
Short name T375
Test name
Test status
Simulation time 292087916 ps
CPU time 9.66 seconds
Started Jul 30 06:46:08 PM PDT 24
Finished Jul 30 06:46:18 PM PDT 24
Peak memory 219568 kb
Host smart-d7d06871-d72e-404e-9dbf-0fef921e900b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170773375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2170773375
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1165879215
Short name T109
Test name
Test status
Simulation time 525211921 ps
CPU time 70.75 seconds
Started Jul 30 06:46:24 PM PDT 24
Finished Jul 30 06:47:34 PM PDT 24
Peak memory 214176 kb
Host smart-5a25b788-6644-43bd-9964-212794a7da3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165879215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1165879215
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.884553964
Short name T345
Test name
Test status
Simulation time 403782045 ps
CPU time 4.68 seconds
Started Jul 30 06:46:13 PM PDT 24
Finished Jul 30 06:46:18 PM PDT 24
Peak memory 214964 kb
Host smart-1ef95268-0696-4f30-9b4f-5d3358e304ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884553964 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.884553964
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.645559284
Short name T67
Test name
Test status
Simulation time 246042272 ps
CPU time 5.21 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:15 PM PDT 24
Peak memory 218252 kb
Host smart-44384bbd-bf61-4284-91c0-a43a8b6c949c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645559284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.645559284
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1848382150
Short name T65
Test name
Test status
Simulation time 288260064 ps
CPU time 6.83 seconds
Started Jul 30 06:46:14 PM PDT 24
Finished Jul 30 06:46:21 PM PDT 24
Peak memory 219516 kb
Host smart-85a59dee-ebc3-42b3-8dd9-06d171675edb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848382150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1848382150
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2890866291
Short name T372
Test name
Test status
Simulation time 496385565 ps
CPU time 11.09 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:21 PM PDT 24
Peak memory 219700 kb
Host smart-f1f313f8-2ac1-4932-bf01-0a4142e9a2d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890866291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2890866291
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2304530603
Short name T380
Test name
Test status
Simulation time 640603531 ps
CPU time 36.17 seconds
Started Jul 30 06:46:09 PM PDT 24
Finished Jul 30 06:46:46 PM PDT 24
Peak memory 219508 kb
Host smart-fbdb8291-31ff-44a2-8e66-787ef7de0f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304530603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2304530603
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2713836360
Short name T336
Test name
Test status
Simulation time 140225618 ps
CPU time 6.1 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:13 PM PDT 24
Peak memory 216184 kb
Host smart-c238e139-3504-4fb5-b4f5-ef8f118a62b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713836360 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2713836360
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3382520985
Short name T385
Test name
Test status
Simulation time 493880686 ps
CPU time 7.99 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:19 PM PDT 24
Peak memory 211352 kb
Host smart-875237e6-3f8f-4c76-9a15-54afc2802a88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382520985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3382520985
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3199427281
Short name T90
Test name
Test status
Simulation time 85463792 ps
CPU time 4.47 seconds
Started Jul 30 06:46:23 PM PDT 24
Finished Jul 30 06:46:28 PM PDT 24
Peak memory 211376 kb
Host smart-e963f28e-58c1-4966-ae5a-181839ae735e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199427281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3199427281
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2840490263
Short name T364
Test name
Test status
Simulation time 365457403 ps
CPU time 9.6 seconds
Started Jul 30 06:46:23 PM PDT 24
Finished Jul 30 06:46:33 PM PDT 24
Peak memory 219684 kb
Host smart-20c9fbc2-16e8-4191-a66a-b5741e98cfe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840490263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2840490263
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3645104005
Short name T58
Test name
Test status
Simulation time 216562376 ps
CPU time 36.55 seconds
Started Jul 30 06:46:24 PM PDT 24
Finished Jul 30 06:47:01 PM PDT 24
Peak memory 211532 kb
Host smart-630a680f-c953-432f-b6e6-b1ba81875ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645104005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3645104005
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2902194978
Short name T341
Test name
Test status
Simulation time 380772165 ps
CPU time 4.28 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 219616 kb
Host smart-a835b9a4-6b80-4bbe-9046-7849e44b470b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902194978 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2902194978
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.709996781
Short name T386
Test name
Test status
Simulation time 154550945 ps
CPU time 5.04 seconds
Started Jul 30 06:46:07 PM PDT 24
Finished Jul 30 06:46:12 PM PDT 24
Peak memory 211308 kb
Host smart-9878c4a2-b2e3-41c7-b848-97b5dfc4e87a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709996781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.709996781
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.825601297
Short name T368
Test name
Test status
Simulation time 1031964487 ps
CPU time 5.23 seconds
Started Jul 30 06:46:20 PM PDT 24
Finished Jul 30 06:46:25 PM PDT 24
Peak memory 211420 kb
Host smart-9432ef4c-1ff0-4bb3-9f21-b736c70e63c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825601297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.825601297
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2442569585
Short name T349
Test name
Test status
Simulation time 249570173 ps
CPU time 7.18 seconds
Started Jul 30 06:46:12 PM PDT 24
Finished Jul 30 06:46:19 PM PDT 24
Peak memory 217372 kb
Host smart-1ece8c7e-5637-480b-913e-e480d7fe49a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442569585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2442569585
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2738222694
Short name T106
Test name
Test status
Simulation time 477413468 ps
CPU time 68.95 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:47:20 PM PDT 24
Peak memory 213260 kb
Host smart-a446b363-88ee-46ae-933b-d9c0b23e292b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738222694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2738222694
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2274742845
Short name T399
Test name
Test status
Simulation time 862213222 ps
CPU time 5.43 seconds
Started Jul 30 06:46:17 PM PDT 24
Finished Jul 30 06:46:22 PM PDT 24
Peak memory 219616 kb
Host smart-2c783dcd-6f9c-4551-b6ee-7243fe450cb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274742845 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2274742845
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2102417921
Short name T95
Test name
Test status
Simulation time 480757831 ps
CPU time 5.11 seconds
Started Jul 30 06:46:18 PM PDT 24
Finished Jul 30 06:46:23 PM PDT 24
Peak memory 218128 kb
Host smart-12835f9b-ec60-4411-9239-5388b2b17cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102417921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2102417921
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3808284205
Short name T390
Test name
Test status
Simulation time 720501081 ps
CPU time 18.45 seconds
Started Jul 30 06:46:05 PM PDT 24
Finished Jul 30 06:46:24 PM PDT 24
Peak memory 211436 kb
Host smart-b3d7cc1c-ce8d-4831-8f74-44d334030062
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808284205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3808284205
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.847993393
Short name T408
Test name
Test status
Simulation time 173054157 ps
CPU time 4.34 seconds
Started Jul 30 06:46:11 PM PDT 24
Finished Jul 30 06:46:16 PM PDT 24
Peak memory 219424 kb
Host smart-e8b8f856-95df-4ddb-98ff-9a8b446d5155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847993393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.847993393
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3420114233
Short name T350
Test name
Test status
Simulation time 86961964 ps
CPU time 7.01 seconds
Started Jul 30 06:46:17 PM PDT 24
Finished Jul 30 06:46:24 PM PDT 24
Peak memory 216428 kb
Host smart-9548c237-c3ff-4388-94d4-462e0761abe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420114233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3420114233
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1772543244
Short name T338
Test name
Test status
Simulation time 169634369 ps
CPU time 36.95 seconds
Started Jul 30 06:46:22 PM PDT 24
Finished Jul 30 06:46:59 PM PDT 24
Peak memory 219516 kb
Host smart-72775581-3559-4152-96e7-a98f0671e1cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772543244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1772543244
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.213549758
Short name T197
Test name
Test status
Simulation time 591464204 ps
CPU time 5.14 seconds
Started Jul 30 06:18:22 PM PDT 24
Finished Jul 30 06:18:27 PM PDT 24
Peak memory 212044 kb
Host smart-6d5322d9-de0c-4139-829c-3b799ca33d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213549758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.213549758
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2099192933
Short name T114
Test name
Test status
Simulation time 251725105 ps
CPU time 11.04 seconds
Started Jul 30 06:18:21 PM PDT 24
Finished Jul 30 06:18:33 PM PDT 24
Peak memory 213196 kb
Host smart-ee05fa10-5808-4069-b523-c13eb3344cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099192933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2099192933
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1430319988
Short name T160
Test name
Test status
Simulation time 604290429 ps
CPU time 6.63 seconds
Started Jul 30 06:18:23 PM PDT 24
Finished Jul 30 06:18:30 PM PDT 24
Peak memory 212168 kb
Host smart-68926b81-2afa-449d-b340-b76ebcd4a091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1430319988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1430319988
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3996558706
Short name T24
Test name
Test status
Simulation time 250674751 ps
CPU time 54.42 seconds
Started Jul 30 06:18:24 PM PDT 24
Finished Jul 30 06:19:19 PM PDT 24
Peak memory 237372 kb
Host smart-69c4c86d-fff1-4165-b6b7-053e50c3ac1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996558706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3996558706
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4273871655
Short name T204
Test name
Test status
Simulation time 147857422 ps
CPU time 6.82 seconds
Started Jul 30 06:18:21 PM PDT 24
Finished Jul 30 06:18:28 PM PDT 24
Peak memory 212072 kb
Host smart-5fec61ce-d98d-42ca-a1a0-3bf1cfbc89c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273871655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4273871655
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2770103823
Short name T225
Test name
Test status
Simulation time 783660703 ps
CPU time 9.41 seconds
Started Jul 30 06:18:21 PM PDT 24
Finished Jul 30 06:18:30 PM PDT 24
Peak memory 212160 kb
Host smart-f0a892b2-c572-4d72-ab1f-c32c94c5a840
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770103823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2770103823
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2083325633
Short name T259
Test name
Test status
Simulation time 397140483 ps
CPU time 4.48 seconds
Started Jul 30 06:18:26 PM PDT 24
Finished Jul 30 06:18:31 PM PDT 24
Peak memory 212032 kb
Host smart-8e7460c6-4ef0-4e05-b0dc-36988d0e943a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083325633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2083325633
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1207910179
Short name T253
Test name
Test status
Simulation time 2852273707 ps
CPU time 107.28 seconds
Started Jul 30 06:18:24 PM PDT 24
Finished Jul 30 06:20:11 PM PDT 24
Peak memory 229208 kb
Host smart-bd304dda-e1e7-4754-904c-e924dfc0105e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207910179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1207910179
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1488014570
Short name T323
Test name
Test status
Simulation time 379975689 ps
CPU time 5.6 seconds
Started Jul 30 06:18:24 PM PDT 24
Finished Jul 30 06:18:30 PM PDT 24
Peak memory 212204 kb
Host smart-bd6c0f56-b0c9-45b5-b707-419393220fde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488014570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1488014570
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.271914073
Short name T313
Test name
Test status
Simulation time 193369329 ps
CPU time 5.66 seconds
Started Jul 30 06:18:23 PM PDT 24
Finished Jul 30 06:18:29 PM PDT 24
Peak memory 212156 kb
Host smart-6e7183e9-09fb-427a-b39b-4c0158820993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271914073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.271914073
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2769514622
Short name T200
Test name
Test status
Simulation time 178325056 ps
CPU time 8.73 seconds
Started Jul 30 06:18:23 PM PDT 24
Finished Jul 30 06:18:31 PM PDT 24
Peak memory 212084 kb
Host smart-75abf5c1-7600-4a3f-9094-96d17e0e0688
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769514622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2769514622
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4057669820
Short name T38
Test name
Test status
Simulation time 17589547334 ps
CPU time 150.19 seconds
Started Jul 30 06:18:46 PM PDT 24
Finished Jul 30 06:21:16 PM PDT 24
Peak memory 238868 kb
Host smart-e7b1d5ca-936e-463e-819b-189e085efb8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057669820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4057669820
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.376097963
Short name T134
Test name
Test status
Simulation time 144677844 ps
CPU time 6.84 seconds
Started Jul 30 06:18:45 PM PDT 24
Finished Jul 30 06:18:52 PM PDT 24
Peak memory 212216 kb
Host smart-1ede97dc-2b0b-40c6-b1a1-0e8266bac6bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=376097963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.376097963
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4099576551
Short name T264
Test name
Test status
Simulation time 295809608 ps
CPU time 16.14 seconds
Started Jul 30 06:18:49 PM PDT 24
Finished Jul 30 06:19:06 PM PDT 24
Peak memory 216000 kb
Host smart-acb65f0e-806b-4b98-8175-55cf02494e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099576551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4099576551
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1617227588
Short name T122
Test name
Test status
Simulation time 335078928 ps
CPU time 4.31 seconds
Started Jul 30 06:18:51 PM PDT 24
Finished Jul 30 06:18:55 PM PDT 24
Peak memory 212012 kb
Host smart-e11d7254-9453-4c39-9025-a730003ad95e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617227588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1617227588
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3819774561
Short name T228
Test name
Test status
Simulation time 4792556976 ps
CPU time 80.72 seconds
Started Jul 30 06:18:48 PM PDT 24
Finished Jul 30 06:20:09 PM PDT 24
Peak memory 213468 kb
Host smart-b0754d21-661d-4684-b8bc-b1a921a6a1d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819774561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3819774561
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2897678952
Short name T8
Test name
Test status
Simulation time 639749306 ps
CPU time 9.48 seconds
Started Jul 30 06:18:53 PM PDT 24
Finished Jul 30 06:19:02 PM PDT 24
Peak memory 212940 kb
Host smart-3eab2534-dffc-468f-acc0-7e7a11008911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897678952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2897678952
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1679866784
Short name T150
Test name
Test status
Simulation time 169075331 ps
CPU time 5.93 seconds
Started Jul 30 06:18:47 PM PDT 24
Finished Jul 30 06:18:53 PM PDT 24
Peak memory 212192 kb
Host smart-0e2ece4b-a353-44fd-989d-075d9120d1ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679866784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1679866784
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2078392003
Short name T16
Test name
Test status
Simulation time 932370504 ps
CPU time 14.23 seconds
Started Jul 30 06:18:43 PM PDT 24
Finished Jul 30 06:18:58 PM PDT 24
Peak memory 215072 kb
Host smart-311aabe2-a45a-45d0-9751-6450e59acef6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078392003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2078392003
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4131177265
Short name T42
Test name
Test status
Simulation time 168479086 ps
CPU time 4.36 seconds
Started Jul 30 06:18:52 PM PDT 24
Finished Jul 30 06:18:57 PM PDT 24
Peak memory 212032 kb
Host smart-e5fba8b0-49c0-4055-8a95-120edb9e2588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131177265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4131177265
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1827565467
Short name T47
Test name
Test status
Simulation time 5840074951 ps
CPU time 156.13 seconds
Started Jul 30 06:18:47 PM PDT 24
Finished Jul 30 06:21:23 PM PDT 24
Peak memory 238972 kb
Host smart-5f91ba1f-1cca-4843-965b-5ffda2d8f5f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827565467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1827565467
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2776852865
Short name T129
Test name
Test status
Simulation time 692017623 ps
CPU time 9.53 seconds
Started Jul 30 06:18:47 PM PDT 24
Finished Jul 30 06:18:57 PM PDT 24
Peak memory 212912 kb
Host smart-2c1371fd-4de5-424d-baab-42efa0ecbc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776852865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2776852865
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1381458233
Short name T208
Test name
Test status
Simulation time 610184225 ps
CPU time 6.48 seconds
Started Jul 30 06:18:49 PM PDT 24
Finished Jul 30 06:18:56 PM PDT 24
Peak memory 212160 kb
Host smart-04d6b4b9-98a3-4550-a407-dd7a3fd382c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381458233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1381458233
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.660434475
Short name T272
Test name
Test status
Simulation time 1076130597 ps
CPU time 13.61 seconds
Started Jul 30 06:18:53 PM PDT 24
Finished Jul 30 06:19:06 PM PDT 24
Peak memory 215944 kb
Host smart-2438a404-fded-48e6-87d6-385fd25e0631
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660434475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.660434475
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1395962156
Short name T151
Test name
Test status
Simulation time 348532940 ps
CPU time 4.39 seconds
Started Jul 30 06:18:52 PM PDT 24
Finished Jul 30 06:18:56 PM PDT 24
Peak memory 212028 kb
Host smart-e87920e8-a809-4c91-a042-7bf74c085c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395962156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1395962156
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2643066429
Short name T153
Test name
Test status
Simulation time 1056192410 ps
CPU time 52.69 seconds
Started Jul 30 06:18:49 PM PDT 24
Finished Jul 30 06:19:42 PM PDT 24
Peak memory 227696 kb
Host smart-2213ad14-d446-40c2-bd23-fdd7cb2583cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643066429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2643066429
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.243822085
Short name T206
Test name
Test status
Simulation time 526032692 ps
CPU time 11.26 seconds
Started Jul 30 06:18:48 PM PDT 24
Finished Jul 30 06:18:59 PM PDT 24
Peak memory 212964 kb
Host smart-1a3c146a-390b-47c8-bd22-a1f67c85d298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243822085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.243822085
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.758503858
Short name T120
Test name
Test status
Simulation time 102219589 ps
CPU time 6.03 seconds
Started Jul 30 06:18:53 PM PDT 24
Finished Jul 30 06:18:59 PM PDT 24
Peak memory 212208 kb
Host smart-ce4e97cc-4aa5-42d5-8cee-d8da054ddebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758503858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.758503858
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1356810702
Short name T315
Test name
Test status
Simulation time 2030832399 ps
CPU time 13.86 seconds
Started Jul 30 06:18:47 PM PDT 24
Finished Jul 30 06:19:01 PM PDT 24
Peak memory 214792 kb
Host smart-7a4e4f77-d3b5-497f-97fc-f79bedaa0d51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356810702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1356810702
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.192331853
Short name T283
Test name
Test status
Simulation time 130946980 ps
CPU time 5.21 seconds
Started Jul 30 06:18:56 PM PDT 24
Finished Jul 30 06:19:02 PM PDT 24
Peak memory 212040 kb
Host smart-f29c9c7b-01b3-46ee-9a4f-c92dc808e31c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192331853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.192331853
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2620559388
Short name T233
Test name
Test status
Simulation time 1598977507 ps
CPU time 96.34 seconds
Started Jul 30 06:18:58 PM PDT 24
Finished Jul 30 06:20:34 PM PDT 24
Peak memory 237356 kb
Host smart-198b506a-f27c-40a4-a2cf-1f18dbe5ee7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620559388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2620559388
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1616012793
Short name T269
Test name
Test status
Simulation time 498464314 ps
CPU time 11.65 seconds
Started Jul 30 06:18:56 PM PDT 24
Finished Jul 30 06:19:08 PM PDT 24
Peak memory 212860 kb
Host smart-9247ec5c-e51a-4b79-8923-55cbb2d105d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616012793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1616012793
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.448370456
Short name T251
Test name
Test status
Simulation time 140207045 ps
CPU time 6.13 seconds
Started Jul 30 06:18:51 PM PDT 24
Finished Jul 30 06:18:57 PM PDT 24
Peak memory 212132 kb
Host smart-2fbc6f77-67dd-44a4-8b51-601bc267d398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448370456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.448370456
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.61630604
Short name T284
Test name
Test status
Simulation time 173867154 ps
CPU time 11.82 seconds
Started Jul 30 06:18:51 PM PDT 24
Finished Jul 30 06:19:03 PM PDT 24
Peak memory 212292 kb
Host smart-fe55e05d-3bc1-4e37-9ed1-86d07196ac94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61630604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.rom_ctrl_stress_all.61630604
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.600243440
Short name T304
Test name
Test status
Simulation time 175726392 ps
CPU time 4.36 seconds
Started Jul 30 06:19:00 PM PDT 24
Finished Jul 30 06:19:04 PM PDT 24
Peak memory 212052 kb
Host smart-a99f8b38-8017-4c5d-a0a1-b6a2ff4f1829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600243440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.600243440
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2923702569
Short name T274
Test name
Test status
Simulation time 10761277035 ps
CPU time 67.03 seconds
Started Jul 30 06:18:58 PM PDT 24
Finished Jul 30 06:20:06 PM PDT 24
Peak memory 238420 kb
Host smart-535c1e55-32b5-4c0a-8d83-51eebfec9455
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923702569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2923702569
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.516661671
Short name T252
Test name
Test status
Simulation time 928099289 ps
CPU time 11.29 seconds
Started Jul 30 06:18:57 PM PDT 24
Finished Jul 30 06:19:08 PM PDT 24
Peak memory 212924 kb
Host smart-fd24b295-fe81-4744-90da-2f445aa59deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516661671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.516661671
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.569253278
Short name T311
Test name
Test status
Simulation time 281242196 ps
CPU time 7.1 seconds
Started Jul 30 06:18:57 PM PDT 24
Finished Jul 30 06:19:05 PM PDT 24
Peak memory 212200 kb
Host smart-c76927f1-6aca-421e-95d6-620b90e64b06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=569253278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.569253278
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1738938309
Short name T3
Test name
Test status
Simulation time 200638989 ps
CPU time 5.7 seconds
Started Jul 30 06:18:57 PM PDT 24
Finished Jul 30 06:19:02 PM PDT 24
Peak memory 212100 kb
Host smart-a0f80302-0041-413c-9c72-41ee6abc57ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738938309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1738938309
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3920646891
Short name T139
Test name
Test status
Simulation time 564456176 ps
CPU time 5.22 seconds
Started Jul 30 06:19:03 PM PDT 24
Finished Jul 30 06:19:08 PM PDT 24
Peak memory 212044 kb
Host smart-833ab2fe-91c4-473b-9c67-998dceac47c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920646891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3920646891
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2592396723
Short name T258
Test name
Test status
Simulation time 14000071850 ps
CPU time 105.49 seconds
Started Jul 30 06:18:59 PM PDT 24
Finished Jul 30 06:20:45 PM PDT 24
Peak memory 213532 kb
Host smart-6f74ee76-359f-446f-8757-6b7fce7464d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592396723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2592396723
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3617711539
Short name T163
Test name
Test status
Simulation time 3545049943 ps
CPU time 11.57 seconds
Started Jul 30 06:19:00 PM PDT 24
Finished Jul 30 06:19:11 PM PDT 24
Peak memory 213476 kb
Host smart-4055139b-871f-4a0b-83d5-8993c3ba4a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617711539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3617711539
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1419269810
Short name T298
Test name
Test status
Simulation time 97855212 ps
CPU time 5.82 seconds
Started Jul 30 06:19:00 PM PDT 24
Finished Jul 30 06:19:06 PM PDT 24
Peak memory 212216 kb
Host smart-96d027b2-ed12-42f7-b06a-ccd14c2f4823
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1419269810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1419269810
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2039660547
Short name T97
Test name
Test status
Simulation time 298271049 ps
CPU time 14.38 seconds
Started Jul 30 06:18:59 PM PDT 24
Finished Jul 30 06:19:14 PM PDT 24
Peak memory 214584 kb
Host smart-baf6b6c2-13a5-4b2d-a80b-e3de17221742
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039660547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2039660547
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3286398230
Short name T52
Test name
Test status
Simulation time 92772199573 ps
CPU time 935.83 seconds
Started Jul 30 06:19:02 PM PDT 24
Finished Jul 30 06:34:38 PM PDT 24
Peak memory 236664 kb
Host smart-b63c64b9-d67b-4957-9544-8d4538a3ba9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286398230 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.3286398230
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3061702678
Short name T215
Test name
Test status
Simulation time 496392890 ps
CPU time 5.15 seconds
Started Jul 30 06:18:59 PM PDT 24
Finished Jul 30 06:19:05 PM PDT 24
Peak memory 211988 kb
Host smart-d4e23dc0-738c-4a5f-bca4-0d103adb4cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061702678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3061702678
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1763467686
Short name T40
Test name
Test status
Simulation time 2447146514 ps
CPU time 124.13 seconds
Started Jul 30 06:19:02 PM PDT 24
Finished Jul 30 06:21:07 PM PDT 24
Peak memory 213472 kb
Host smart-08dd599f-d4b3-4f60-835d-ca66190cf49f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763467686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1763467686
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4054872967
Short name T296
Test name
Test status
Simulation time 723531174 ps
CPU time 9.9 seconds
Started Jul 30 06:19:00 PM PDT 24
Finished Jul 30 06:19:10 PM PDT 24
Peak memory 212892 kb
Host smart-d030caa3-b6c9-4b50-ba80-29f9bd8be136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054872967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4054872967
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.939861910
Short name T218
Test name
Test status
Simulation time 660690593 ps
CPU time 6.07 seconds
Started Jul 30 06:19:01 PM PDT 24
Finished Jul 30 06:19:07 PM PDT 24
Peak memory 212156 kb
Host smart-ed487282-1955-4eeb-bc5f-38e5f555f1b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939861910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.939861910
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.246103778
Short name T277
Test name
Test status
Simulation time 279847267 ps
CPU time 13.62 seconds
Started Jul 30 06:19:01 PM PDT 24
Finished Jul 30 06:19:14 PM PDT 24
Peak memory 214604 kb
Host smart-e77e4fc9-aee8-48d9-b5d4-ce21d1e2c01e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246103778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.246103778
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1159476607
Short name T275
Test name
Test status
Simulation time 169272263 ps
CPU time 4.37 seconds
Started Jul 30 06:19:02 PM PDT 24
Finished Jul 30 06:19:07 PM PDT 24
Peak memory 212056 kb
Host smart-039b8d59-9d2f-462a-918b-ab0662236faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159476607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1159476607
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2935999061
Short name T279
Test name
Test status
Simulation time 1471587115 ps
CPU time 90.17 seconds
Started Jul 30 06:18:59 PM PDT 24
Finished Jul 30 06:20:29 PM PDT 24
Peak memory 237556 kb
Host smart-c0ee42ed-dd39-4eb2-98e9-c932f411a142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935999061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2935999061
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3679539861
Short name T45
Test name
Test status
Simulation time 168849126 ps
CPU time 9.52 seconds
Started Jul 30 06:19:01 PM PDT 24
Finished Jul 30 06:19:10 PM PDT 24
Peak memory 212924 kb
Host smart-ff4e47db-d9cb-4a5a-a796-ffa92b29795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679539861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3679539861
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2280893054
Short name T156
Test name
Test status
Simulation time 391825032 ps
CPU time 5.67 seconds
Started Jul 30 06:19:04 PM PDT 24
Finished Jul 30 06:19:09 PM PDT 24
Peak memory 212208 kb
Host smart-24620ad7-1d52-449f-8829-f70ae0c82993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280893054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2280893054
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2990867725
Short name T142
Test name
Test status
Simulation time 264687119 ps
CPU time 10.26 seconds
Started Jul 30 06:19:03 PM PDT 24
Finished Jul 30 06:19:13 PM PDT 24
Peak memory 212964 kb
Host smart-5b0c4736-73d0-4090-945f-9f1b8ae4e635
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990867725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2990867725
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.212555605
Short name T50
Test name
Test status
Simulation time 532074364253 ps
CPU time 2080 seconds
Started Jul 30 06:19:00 PM PDT 24
Finished Jul 30 06:53:40 PM PDT 24
Peak memory 239188 kb
Host smart-ed22adfd-4e67-44c3-a1ca-95c6184f41d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212555605 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.212555605
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2670709097
Short name T43
Test name
Test status
Simulation time 131820385 ps
CPU time 5.23 seconds
Started Jul 30 06:19:03 PM PDT 24
Finished Jul 30 06:19:08 PM PDT 24
Peak memory 212052 kb
Host smart-49c7fc74-b6ad-400b-9693-1d3270c81f52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670709097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2670709097
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3331162825
Short name T285
Test name
Test status
Simulation time 8517087627 ps
CPU time 110.41 seconds
Started Jul 30 06:19:08 PM PDT 24
Finished Jul 30 06:20:58 PM PDT 24
Peak memory 229332 kb
Host smart-858d9424-88ac-49ae-b38c-adcf6ac5dea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331162825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3331162825
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.633198805
Short name T260
Test name
Test status
Simulation time 258876425 ps
CPU time 11.03 seconds
Started Jul 30 06:19:02 PM PDT 24
Finished Jul 30 06:19:14 PM PDT 24
Peak memory 213032 kb
Host smart-6dc9c405-08fb-4e39-8ce2-18fc609ebde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633198805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.633198805
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3305435048
Short name T256
Test name
Test status
Simulation time 268691917 ps
CPU time 6.47 seconds
Started Jul 30 06:19:04 PM PDT 24
Finished Jul 30 06:19:11 PM PDT 24
Peak memory 212344 kb
Host smart-71055dfc-18d8-4259-b91f-e4d5a2cbf134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3305435048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3305435048
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3733770076
Short name T199
Test name
Test status
Simulation time 1156915146 ps
CPU time 7.33 seconds
Started Jul 30 06:19:05 PM PDT 24
Finished Jul 30 06:19:13 PM PDT 24
Peak memory 212168 kb
Host smart-38928710-ec58-4f32-a6c5-4a15df7f6b2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733770076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3733770076
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.532148317
Short name T310
Test name
Test status
Simulation time 1563007833 ps
CPU time 5.08 seconds
Started Jul 30 06:18:28 PM PDT 24
Finished Jul 30 06:18:33 PM PDT 24
Peak memory 212056 kb
Host smart-8921571d-8c4c-4957-9f88-891535ded9b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532148317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.532148317
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1308315754
Short name T205
Test name
Test status
Simulation time 20621278117 ps
CPU time 167.58 seconds
Started Jul 30 06:18:25 PM PDT 24
Finished Jul 30 06:21:13 PM PDT 24
Peak memory 214444 kb
Host smart-2f38290d-364a-4a0f-91ae-217324c7e277
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308315754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1308315754
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4110557425
Short name T119
Test name
Test status
Simulation time 619492809 ps
CPU time 9.46 seconds
Started Jul 30 06:18:28 PM PDT 24
Finished Jul 30 06:18:38 PM PDT 24
Peak memory 213244 kb
Host smart-275190b4-7e3c-4da8-84dd-55cc4c787f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110557425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4110557425
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.602762064
Short name T19
Test name
Test status
Simulation time 446528091 ps
CPU time 5.39 seconds
Started Jul 30 06:18:27 PM PDT 24
Finished Jul 30 06:18:32 PM PDT 24
Peak memory 212208 kb
Host smart-682d53f9-934c-4e49-9250-1f05a890bf69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=602762064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.602762064
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2688369939
Short name T27
Test name
Test status
Simulation time 256417438 ps
CPU time 100.22 seconds
Started Jul 30 06:18:28 PM PDT 24
Finished Jul 30 06:20:09 PM PDT 24
Peak memory 237300 kb
Host smart-21bd7495-bd24-4d05-a835-f26a7d59ed29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688369939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2688369939
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3989443010
Short name T219
Test name
Test status
Simulation time 287322681 ps
CPU time 6.46 seconds
Started Jul 30 06:18:27 PM PDT 24
Finished Jul 30 06:18:34 PM PDT 24
Peak memory 212108 kb
Host smart-712bcbbc-631b-43bf-9a17-81599ec17dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989443010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3989443010
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.447035580
Short name T302
Test name
Test status
Simulation time 1689663395 ps
CPU time 19.51 seconds
Started Jul 30 06:18:25 PM PDT 24
Finished Jul 30 06:18:45 PM PDT 24
Peak memory 214280 kb
Host smart-a377ea24-3f2b-41ab-8c18-f8ebfde679bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447035580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.447035580
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1574967423
Short name T54
Test name
Test status
Simulation time 85296773272 ps
CPU time 1815.54 seconds
Started Jul 30 06:18:25 PM PDT 24
Finished Jul 30 06:48:41 PM PDT 24
Peak memory 248520 kb
Host smart-3893d8ae-af79-40e2-b4f9-34dda45c6441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574967423 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1574967423
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.741649660
Short name T217
Test name
Test status
Simulation time 2067346948 ps
CPU time 5.15 seconds
Started Jul 30 06:19:04 PM PDT 24
Finished Jul 30 06:19:09 PM PDT 24
Peak memory 212004 kb
Host smart-649adbc9-ff1c-4dc0-a0c4-0e32ea203128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741649660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.741649660
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.884072151
Short name T261
Test name
Test status
Simulation time 735062103 ps
CPU time 6.24 seconds
Started Jul 30 06:19:04 PM PDT 24
Finished Jul 30 06:19:10 PM PDT 24
Peak memory 212192 kb
Host smart-2fb1df69-1d9d-4e69-ae27-0afc73c9ea6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884072151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.884072151
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.400021601
Short name T44
Test name
Test status
Simulation time 449825032 ps
CPU time 8.66 seconds
Started Jul 30 06:19:05 PM PDT 24
Finished Jul 30 06:19:14 PM PDT 24
Peak memory 213128 kb
Host smart-d7655039-9e93-4916-83c7-629881e752c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400021601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.400021601
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1960391117
Short name T51
Test name
Test status
Simulation time 244409801504 ps
CPU time 2187.29 seconds
Started Jul 30 06:19:02 PM PDT 24
Finished Jul 30 06:55:30 PM PDT 24
Peak memory 252240 kb
Host smart-b065a35e-578a-4eb6-9c64-f83626786ca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960391117 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1960391117
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3547230887
Short name T189
Test name
Test status
Simulation time 171263512 ps
CPU time 4.33 seconds
Started Jul 30 06:19:04 PM PDT 24
Finished Jul 30 06:19:08 PM PDT 24
Peak memory 212044 kb
Host smart-79240029-25bc-4c88-98e9-4a4a50165ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547230887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3547230887
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3372032675
Short name T292
Test name
Test status
Simulation time 2411444025 ps
CPU time 153.27 seconds
Started Jul 30 06:19:03 PM PDT 24
Finished Jul 30 06:21:36 PM PDT 24
Peak memory 234392 kb
Host smart-ee5cb409-0f94-40d1-89f5-b14ea1951513
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372032675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3372032675
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1452036410
Short name T127
Test name
Test status
Simulation time 257430522 ps
CPU time 11.73 seconds
Started Jul 30 06:19:05 PM PDT 24
Finished Jul 30 06:19:17 PM PDT 24
Peak memory 212208 kb
Host smart-5786cf92-ceab-4cd7-8b61-ca392121e809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452036410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1452036410
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1191459373
Short name T240
Test name
Test status
Simulation time 137122944 ps
CPU time 6.3 seconds
Started Jul 30 06:19:05 PM PDT 24
Finished Jul 30 06:19:11 PM PDT 24
Peak memory 212192 kb
Host smart-ef95f44e-e7f5-4f44-a960-4dbd328838e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191459373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1191459373
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.460122407
Short name T148
Test name
Test status
Simulation time 306504257 ps
CPU time 14.18 seconds
Started Jul 30 06:19:07 PM PDT 24
Finished Jul 30 06:19:22 PM PDT 24
Peak memory 214248 kb
Host smart-17ab5766-b245-4909-90cc-4583d5de8347
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460122407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.460122407
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2422113457
Short name T248
Test name
Test status
Simulation time 200619340 ps
CPU time 4.34 seconds
Started Jul 30 06:19:07 PM PDT 24
Finished Jul 30 06:19:11 PM PDT 24
Peak memory 212136 kb
Host smart-0fdbf453-2b2b-4aca-947c-488d300c40ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422113457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2422113457
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2355753989
Short name T312
Test name
Test status
Simulation time 2268140278 ps
CPU time 132.76 seconds
Started Jul 30 06:19:09 PM PDT 24
Finished Jul 30 06:21:22 PM PDT 24
Peak memory 235016 kb
Host smart-682af880-406f-40f7-a091-807ce9982000
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355753989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2355753989
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1820057236
Short name T179
Test name
Test status
Simulation time 758041309 ps
CPU time 9.49 seconds
Started Jul 30 06:19:07 PM PDT 24
Finished Jul 30 06:19:17 PM PDT 24
Peak memory 213108 kb
Host smart-f0512530-662d-43a4-81be-6f20050489da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820057236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1820057236
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3092117808
Short name T117
Test name
Test status
Simulation time 382767627 ps
CPU time 5.41 seconds
Started Jul 30 06:19:11 PM PDT 24
Finished Jul 30 06:19:16 PM PDT 24
Peak memory 212132 kb
Host smart-3154cfad-3be8-480f-8930-609ac9ea9450
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3092117808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3092117808
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.781323331
Short name T74
Test name
Test status
Simulation time 2553854403 ps
CPU time 14.4 seconds
Started Jul 30 06:19:05 PM PDT 24
Finished Jul 30 06:19:20 PM PDT 24
Peak memory 215304 kb
Host smart-56b4053d-7816-46fb-b7ce-9d5b18feec37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781323331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.781323331
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1286716291
Short name T34
Test name
Test status
Simulation time 87843870 ps
CPU time 4.34 seconds
Started Jul 30 06:19:10 PM PDT 24
Finished Jul 30 06:19:15 PM PDT 24
Peak memory 212056 kb
Host smart-383b8f27-6c83-4b9a-833d-11ba70fa295c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286716291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1286716291
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3737991233
Short name T195
Test name
Test status
Simulation time 17704013739 ps
CPU time 214.04 seconds
Started Jul 30 06:19:09 PM PDT 24
Finished Jul 30 06:22:43 PM PDT 24
Peak memory 235552 kb
Host smart-160bc9e5-35bb-4b86-8b4d-0d47c92bc4d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737991233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3737991233
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4088317658
Short name T194
Test name
Test status
Simulation time 976142587 ps
CPU time 9.6 seconds
Started Jul 30 06:19:08 PM PDT 24
Finished Jul 30 06:19:17 PM PDT 24
Peak memory 212920 kb
Host smart-5b78fe28-7c02-40fa-ad64-f0d71f872bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088317658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4088317658
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3752267297
Short name T294
Test name
Test status
Simulation time 142481629 ps
CPU time 6.25 seconds
Started Jul 30 06:19:09 PM PDT 24
Finished Jul 30 06:19:15 PM PDT 24
Peak memory 212188 kb
Host smart-aa42331d-19fe-4f5d-8997-847ebc6959e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752267297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3752267297
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3556767558
Short name T176
Test name
Test status
Simulation time 232787538 ps
CPU time 11.37 seconds
Started Jul 30 06:19:14 PM PDT 24
Finished Jul 30 06:19:26 PM PDT 24
Peak memory 214332 kb
Host smart-117f611b-4724-441d-b80a-0221e64d3926
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556767558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3556767558
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3855802549
Short name T159
Test name
Test status
Simulation time 262495263 ps
CPU time 5.05 seconds
Started Jul 30 06:19:07 PM PDT 24
Finished Jul 30 06:19:12 PM PDT 24
Peak memory 212096 kb
Host smart-6c99485c-d9f5-4a51-9bf4-6e682e5311d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855802549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3855802549
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3115735913
Short name T191
Test name
Test status
Simulation time 14822146163 ps
CPU time 152.49 seconds
Started Jul 30 06:19:09 PM PDT 24
Finished Jul 30 06:21:42 PM PDT 24
Peak memory 238524 kb
Host smart-93b579b7-90e9-4c79-a392-14afb0ea4593
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115735913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3115735913
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2205725191
Short name T316
Test name
Test status
Simulation time 724332836 ps
CPU time 9.44 seconds
Started Jul 30 06:19:08 PM PDT 24
Finished Jul 30 06:19:17 PM PDT 24
Peak memory 212836 kb
Host smart-208ccaad-e100-4b5a-8aa2-f53112ccd6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205725191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2205725191
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3156700317
Short name T209
Test name
Test status
Simulation time 398169923 ps
CPU time 5.86 seconds
Started Jul 30 06:19:08 PM PDT 24
Finished Jul 30 06:19:14 PM PDT 24
Peak memory 212344 kb
Host smart-254273db-9e37-400e-9bd6-4f4083873870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156700317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3156700317
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.693685819
Short name T162
Test name
Test status
Simulation time 545855555 ps
CPU time 13.71 seconds
Started Jul 30 06:19:14 PM PDT 24
Finished Jul 30 06:19:28 PM PDT 24
Peak memory 214008 kb
Host smart-a1f10c54-f95a-4082-8bf3-b953126c4931
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693685819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.693685819
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2787856643
Short name T221
Test name
Test status
Simulation time 254960363 ps
CPU time 5.12 seconds
Started Jul 30 06:19:14 PM PDT 24
Finished Jul 30 06:19:20 PM PDT 24
Peak memory 211988 kb
Host smart-99670ce3-bf11-4687-9dc1-6b2ff7574ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787856643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2787856643
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.453383295
Short name T18
Test name
Test status
Simulation time 3505484279 ps
CPU time 121.1 seconds
Started Jul 30 06:19:15 PM PDT 24
Finished Jul 30 06:21:16 PM PDT 24
Peak memory 229288 kb
Host smart-b92d3f34-2956-4494-bf10-3f9fbab25815
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453383295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.453383295
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4222620571
Short name T211
Test name
Test status
Simulation time 171932321 ps
CPU time 9.54 seconds
Started Jul 30 06:19:10 PM PDT 24
Finished Jul 30 06:19:20 PM PDT 24
Peak memory 212832 kb
Host smart-7571228c-fbeb-49be-9178-4678a85cbe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222620571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4222620571
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.456663605
Short name T140
Test name
Test status
Simulation time 535884995 ps
CPU time 6.3 seconds
Started Jul 30 06:19:09 PM PDT 24
Finished Jul 30 06:19:16 PM PDT 24
Peak memory 212160 kb
Host smart-671ca994-6c04-406a-88f6-7149163fc586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456663605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.456663605
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2049257619
Short name T17
Test name
Test status
Simulation time 401687612 ps
CPU time 17.24 seconds
Started Jul 30 06:19:08 PM PDT 24
Finished Jul 30 06:19:25 PM PDT 24
Peak memory 214952 kb
Host smart-4fc713e5-b27d-4ca8-8353-7cfa2ceb5ae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049257619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2049257619
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2555750281
Short name T222
Test name
Test status
Simulation time 295303070649 ps
CPU time 3170.78 seconds
Started Jul 30 06:19:09 PM PDT 24
Finished Jul 30 07:12:00 PM PDT 24
Peak memory 253056 kb
Host smart-359e56bf-8525-4156-8282-6852f3baad75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555750281 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2555750281
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1772860135
Short name T146
Test name
Test status
Simulation time 127480002 ps
CPU time 5.28 seconds
Started Jul 30 06:19:11 PM PDT 24
Finished Jul 30 06:19:16 PM PDT 24
Peak memory 212116 kb
Host smart-27c00361-9a21-43f6-8cb0-25896e41fa26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772860135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1772860135
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2307051051
Short name T263
Test name
Test status
Simulation time 2927874271 ps
CPU time 96.05 seconds
Started Jul 30 06:19:11 PM PDT 24
Finished Jul 30 06:20:47 PM PDT 24
Peak memory 234432 kb
Host smart-469fcfb4-d480-4ad0-91b8-10cd6b4e1f7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307051051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2307051051
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1708097364
Short name T152
Test name
Test status
Simulation time 615828416 ps
CPU time 9.38 seconds
Started Jul 30 06:19:15 PM PDT 24
Finished Jul 30 06:19:25 PM PDT 24
Peak memory 212932 kb
Host smart-659de68a-7b82-4e02-aa76-2fb303e78f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708097364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1708097364
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.4110663039
Short name T236
Test name
Test status
Simulation time 216420285 ps
CPU time 6.28 seconds
Started Jul 30 06:19:10 PM PDT 24
Finished Jul 30 06:19:16 PM PDT 24
Peak memory 212132 kb
Host smart-6837afa9-bfde-4951-8fe6-ec7a9c2d8c73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4110663039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.4110663039
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2513829737
Short name T286
Test name
Test status
Simulation time 313639647 ps
CPU time 17.02 seconds
Started Jul 30 06:19:14 PM PDT 24
Finished Jul 30 06:19:31 PM PDT 24
Peak memory 216828 kb
Host smart-b224a936-43a5-459e-9c7e-9ab3edb081ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513829737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2513829737
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1304907610
Short name T183
Test name
Test status
Simulation time 129494212 ps
CPU time 4.91 seconds
Started Jul 30 06:19:15 PM PDT 24
Finished Jul 30 06:19:20 PM PDT 24
Peak memory 211988 kb
Host smart-2f21d27b-6744-4c1a-af31-f8ab5c15577e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304907610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1304907610
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.192831308
Short name T22
Test name
Test status
Simulation time 3402677149 ps
CPU time 91.53 seconds
Started Jul 30 06:19:12 PM PDT 24
Finished Jul 30 06:20:43 PM PDT 24
Peak memory 239488 kb
Host smart-906e8414-c646-4884-aa10-515f58fa8f80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192831308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.192831308
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1956289612
Short name T169
Test name
Test status
Simulation time 730629050 ps
CPU time 9.43 seconds
Started Jul 30 06:19:12 PM PDT 24
Finished Jul 30 06:19:21 PM PDT 24
Peak memory 213420 kb
Host smart-a0bd6cab-5f3c-4407-8dd7-e643b150111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956289612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1956289612
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.759755017
Short name T270
Test name
Test status
Simulation time 97493409 ps
CPU time 5.56 seconds
Started Jul 30 06:19:14 PM PDT 24
Finished Jul 30 06:19:19 PM PDT 24
Peak memory 212156 kb
Host smart-0bcb546d-b759-4cab-a8af-559004736a40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759755017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.759755017
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3458126354
Short name T79
Test name
Test status
Simulation time 1362648671 ps
CPU time 30.08 seconds
Started Jul 30 06:19:13 PM PDT 24
Finished Jul 30 06:19:43 PM PDT 24
Peak memory 215720 kb
Host smart-1b1fe184-fc28-4c63-b68c-ff92759b42f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458126354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3458126354
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.349990680
Short name T247
Test name
Test status
Simulation time 255459794 ps
CPU time 5.1 seconds
Started Jul 30 06:19:11 PM PDT 24
Finished Jul 30 06:19:16 PM PDT 24
Peak memory 211992 kb
Host smart-5872a573-2e11-44fa-be0b-f80a81ec10ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349990680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.349990680
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3609609702
Short name T39
Test name
Test status
Simulation time 3063037478 ps
CPU time 122.34 seconds
Started Jul 30 06:19:12 PM PDT 24
Finished Jul 30 06:21:15 PM PDT 24
Peak memory 238368 kb
Host smart-5c8a608d-c20c-47a0-9ffe-f5817ab0c828
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609609702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3609609702
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.981963112
Short name T305
Test name
Test status
Simulation time 251152641 ps
CPU time 11.27 seconds
Started Jul 30 06:19:11 PM PDT 24
Finished Jul 30 06:19:22 PM PDT 24
Peak memory 212808 kb
Host smart-924dd79a-f162-4921-b373-d157323e3781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981963112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.981963112
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3466910526
Short name T230
Test name
Test status
Simulation time 170686835 ps
CPU time 5.87 seconds
Started Jul 30 06:19:12 PM PDT 24
Finished Jul 30 06:19:18 PM PDT 24
Peak memory 212204 kb
Host smart-d8078d4b-95ee-4a49-9bed-d0e41b6fdb86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466910526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3466910526
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4049172303
Short name T268
Test name
Test status
Simulation time 399287226 ps
CPU time 15.39 seconds
Started Jul 30 06:19:14 PM PDT 24
Finished Jul 30 06:19:30 PM PDT 24
Peak memory 214228 kb
Host smart-1a078b38-89e7-4ffc-98c1-993e08dabe5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049172303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4049172303
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.615890885
Short name T297
Test name
Test status
Simulation time 131544357 ps
CPU time 5.21 seconds
Started Jul 30 06:19:16 PM PDT 24
Finished Jul 30 06:19:22 PM PDT 24
Peak memory 212032 kb
Host smart-4531f30e-e0dd-4585-88f0-2f4093d94f67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615890885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.615890885
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1108229313
Short name T180
Test name
Test status
Simulation time 4923790873 ps
CPU time 77.89 seconds
Started Jul 30 06:19:14 PM PDT 24
Finished Jul 30 06:20:32 PM PDT 24
Peak memory 233752 kb
Host smart-3e1d6c1d-8a76-4037-aa67-e29d30e11860
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108229313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1108229313
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1938352986
Short name T116
Test name
Test status
Simulation time 511089568 ps
CPU time 11.07 seconds
Started Jul 30 06:19:10 PM PDT 24
Finished Jul 30 06:19:21 PM PDT 24
Peak memory 212936 kb
Host smart-9bb19a49-3907-411f-a902-fa625d5cd852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938352986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1938352986
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1112756681
Short name T300
Test name
Test status
Simulation time 1654883286 ps
CPU time 6.46 seconds
Started Jul 30 06:19:13 PM PDT 24
Finished Jul 30 06:19:19 PM PDT 24
Peak memory 212156 kb
Host smart-d654de24-e17b-472f-bced-fb3bcb41729d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112756681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1112756681
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3908694842
Short name T278
Test name
Test status
Simulation time 126529410 ps
CPU time 5.2 seconds
Started Jul 30 06:18:30 PM PDT 24
Finished Jul 30 06:18:35 PM PDT 24
Peak memory 212072 kb
Host smart-06461e18-1753-4b9e-964c-2ffaa7fd100d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908694842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3908694842
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1730870797
Short name T112
Test name
Test status
Simulation time 5183838390 ps
CPU time 76.3 seconds
Started Jul 30 06:18:29 PM PDT 24
Finished Jul 30 06:19:45 PM PDT 24
Peak memory 238416 kb
Host smart-e1c6ecd5-fa3d-468e-9ccf-53190df958b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730870797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1730870797
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3940077117
Short name T33
Test name
Test status
Simulation time 646620381 ps
CPU time 9.67 seconds
Started Jul 30 06:18:34 PM PDT 24
Finished Jul 30 06:18:44 PM PDT 24
Peak memory 212924 kb
Host smart-6f48ffb7-fdfe-4584-9128-3cfe1172ed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940077117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3940077117
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.628238750
Short name T118
Test name
Test status
Simulation time 2643380389 ps
CPU time 6.29 seconds
Started Jul 30 06:18:31 PM PDT 24
Finished Jul 30 06:18:37 PM PDT 24
Peak memory 212280 kb
Host smart-dffe7aeb-0368-42f3-90a8-809f99f79def
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628238750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.628238750
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.450523603
Short name T25
Test name
Test status
Simulation time 848563701 ps
CPU time 53.92 seconds
Started Jul 30 06:18:31 PM PDT 24
Finished Jul 30 06:19:25 PM PDT 24
Peak memory 237364 kb
Host smart-d53fbf4f-c815-4345-8ff6-bdc67c253ccc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450523603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.450523603
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1005261822
Short name T76
Test name
Test status
Simulation time 200690397 ps
CPU time 5.71 seconds
Started Jul 30 06:18:28 PM PDT 24
Finished Jul 30 06:18:34 PM PDT 24
Peak memory 212224 kb
Host smart-892a7596-589e-44ab-ba77-ac32eaf4cf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005261822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1005261822
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.494790306
Short name T234
Test name
Test status
Simulation time 312361264 ps
CPU time 8.34 seconds
Started Jul 30 06:18:31 PM PDT 24
Finished Jul 30 06:18:39 PM PDT 24
Peak memory 212080 kb
Host smart-05b53791-b463-4494-a39a-e495203f0898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494790306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.494790306
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1932518999
Short name T138
Test name
Test status
Simulation time 497368354 ps
CPU time 5.24 seconds
Started Jul 30 06:19:16 PM PDT 24
Finished Jul 30 06:19:22 PM PDT 24
Peak memory 212040 kb
Host smart-1984db18-51a0-4fbb-a8da-c621a844d35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932518999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1932518999
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.878649006
Short name T246
Test name
Test status
Simulation time 2719043723 ps
CPU time 85.28 seconds
Started Jul 30 06:19:15 PM PDT 24
Finished Jul 30 06:20:40 PM PDT 24
Peak memory 240792 kb
Host smart-857c5568-8e72-4fdb-ba51-b47be33d5fd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878649006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.878649006
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.734067836
Short name T201
Test name
Test status
Simulation time 260615951 ps
CPU time 11.53 seconds
Started Jul 30 06:19:14 PM PDT 24
Finished Jul 30 06:19:26 PM PDT 24
Peak memory 212880 kb
Host smart-f4a56b16-efdf-4c4f-8304-2e216b678b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734067836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.734067836
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1498566405
Short name T198
Test name
Test status
Simulation time 349111973 ps
CPU time 5.7 seconds
Started Jul 30 06:19:18 PM PDT 24
Finished Jul 30 06:19:24 PM PDT 24
Peak memory 212144 kb
Host smart-68bd389d-215b-4e34-95d1-46197452262e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498566405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1498566405
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3032941309
Short name T29
Test name
Test status
Simulation time 303080638 ps
CPU time 14.96 seconds
Started Jul 30 06:19:13 PM PDT 24
Finished Jul 30 06:19:28 PM PDT 24
Peak memory 215540 kb
Host smart-7910b1c0-6458-424b-ae34-03e1e9d92c54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032941309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3032941309
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3423506645
Short name T238
Test name
Test status
Simulation time 357163912438 ps
CPU time 1682.87 seconds
Started Jul 30 06:19:15 PM PDT 24
Finished Jul 30 06:47:19 PM PDT 24
Peak memory 236672 kb
Host smart-17fde324-60f0-4f44-ae79-3e4a9ce8ec23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423506645 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3423506645
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1254523531
Short name T309
Test name
Test status
Simulation time 350424440 ps
CPU time 4.18 seconds
Started Jul 30 06:19:18 PM PDT 24
Finished Jul 30 06:19:23 PM PDT 24
Peak memory 212100 kb
Host smart-44c235eb-0840-41a5-9599-82e08471679d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254523531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1254523531
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1735416434
Short name T226
Test name
Test status
Simulation time 4910295196 ps
CPU time 131.84 seconds
Started Jul 30 06:19:15 PM PDT 24
Finished Jul 30 06:21:26 PM PDT 24
Peak memory 229304 kb
Host smart-0a7c3289-206e-4067-9818-f0eca70ec319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735416434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1735416434
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2591961311
Short name T115
Test name
Test status
Simulation time 416349549 ps
CPU time 11.36 seconds
Started Jul 30 06:19:17 PM PDT 24
Finished Jul 30 06:19:28 PM PDT 24
Peak memory 213088 kb
Host smart-6cf2881d-31c9-4c69-ad90-c56dbb669ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591961311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2591961311
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3311922906
Short name T314
Test name
Test status
Simulation time 1005546215 ps
CPU time 9.09 seconds
Started Jul 30 06:19:16 PM PDT 24
Finished Jul 30 06:19:25 PM PDT 24
Peak memory 212160 kb
Host smart-aa163e29-2f27-4082-9fdd-9dd8035576e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311922906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3311922906
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1943848040
Short name T11
Test name
Test status
Simulation time 1682249970 ps
CPU time 14.06 seconds
Started Jul 30 06:19:15 PM PDT 24
Finished Jul 30 06:19:29 PM PDT 24
Peak memory 213876 kb
Host smart-43556f94-edc0-410b-8afb-e4eef3ced389
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943848040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1943848040
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.391350285
Short name T131
Test name
Test status
Simulation time 9792438359 ps
CPU time 7.46 seconds
Started Jul 30 06:19:16 PM PDT 24
Finished Jul 30 06:19:24 PM PDT 24
Peak memory 212156 kb
Host smart-15ad2b6d-0079-4f8d-910b-5038273ae454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391350285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.391350285
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3558791481
Short name T170
Test name
Test status
Simulation time 1263701068 ps
CPU time 104.39 seconds
Started Jul 30 06:19:20 PM PDT 24
Finished Jul 30 06:21:04 PM PDT 24
Peak memory 237604 kb
Host smart-703a068e-cae0-48e7-97a0-fae283ce8e8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558791481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3558791481
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2674708305
Short name T130
Test name
Test status
Simulation time 697404231 ps
CPU time 9.56 seconds
Started Jul 30 06:19:13 PM PDT 24
Finished Jul 30 06:19:23 PM PDT 24
Peak memory 212956 kb
Host smart-1b9dc8bb-0995-439a-93a2-ec5c41950d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674708305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2674708305
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2633253490
Short name T168
Test name
Test status
Simulation time 381075515 ps
CPU time 5.61 seconds
Started Jul 30 06:19:14 PM PDT 24
Finished Jul 30 06:19:20 PM PDT 24
Peak memory 212172 kb
Host smart-d7fa9c6b-e39f-40c9-9f09-9c813bae5727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633253490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2633253490
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1147717097
Short name T320
Test name
Test status
Simulation time 1577852509 ps
CPU time 14.93 seconds
Started Jul 30 06:19:15 PM PDT 24
Finished Jul 30 06:19:30 PM PDT 24
Peak memory 214188 kb
Host smart-21c6e026-8c6d-4135-acc8-9cfd46ceba4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147717097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1147717097
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2082478212
Short name T164
Test name
Test status
Simulation time 190941674 ps
CPU time 5.06 seconds
Started Jul 30 06:19:14 PM PDT 24
Finished Jul 30 06:19:20 PM PDT 24
Peak memory 212040 kb
Host smart-4865a853-6ef6-40cb-b294-34e9c99e5b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082478212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2082478212
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2634706817
Short name T37
Test name
Test status
Simulation time 3120142249 ps
CPU time 99.6 seconds
Started Jul 30 06:19:21 PM PDT 24
Finished Jul 30 06:21:01 PM PDT 24
Peak memory 225580 kb
Host smart-464e1f44-491e-4e09-bd9d-5129d0f2e738
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634706817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2634706817
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2222998715
Short name T26
Test name
Test status
Simulation time 2778966377 ps
CPU time 9.33 seconds
Started Jul 30 06:19:19 PM PDT 24
Finished Jul 30 06:19:28 PM PDT 24
Peak memory 213052 kb
Host smart-6b187f2b-c819-4196-b90c-0faa0e31bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222998715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2222998715
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3659174744
Short name T35
Test name
Test status
Simulation time 98948811 ps
CPU time 5.7 seconds
Started Jul 30 06:19:15 PM PDT 24
Finished Jul 30 06:19:21 PM PDT 24
Peak memory 212192 kb
Host smart-db5ba518-10c6-4a66-8dc6-5f76e7c6ef31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659174744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3659174744
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1765431836
Short name T242
Test name
Test status
Simulation time 266002319 ps
CPU time 9.36 seconds
Started Jul 30 06:19:15 PM PDT 24
Finished Jul 30 06:19:25 PM PDT 24
Peak memory 212136 kb
Host smart-3229b01d-8574-4b5c-9451-f2257a3f5288
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765431836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1765431836
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1559204397
Short name T273
Test name
Test status
Simulation time 99357879165 ps
CPU time 2109.72 seconds
Started Jul 30 06:19:21 PM PDT 24
Finished Jul 30 06:54:31 PM PDT 24
Peak memory 245312 kb
Host smart-67f5cd34-95c3-40af-a099-b80e7f460dc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559204397 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1559204397
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1708178284
Short name T9
Test name
Test status
Simulation time 519606440 ps
CPU time 5.02 seconds
Started Jul 30 06:19:20 PM PDT 24
Finished Jul 30 06:19:25 PM PDT 24
Peak memory 212036 kb
Host smart-4d770611-6ba1-44a6-8d4d-ce51729f6cf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708178284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1708178284
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1802250663
Short name T188
Test name
Test status
Simulation time 3071327142 ps
CPU time 145.09 seconds
Started Jul 30 06:19:20 PM PDT 24
Finished Jul 30 06:21:45 PM PDT 24
Peak memory 213404 kb
Host smart-8d379c5e-68c8-4368-a633-9c7efcaf4211
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802250663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1802250663
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.101521069
Short name T213
Test name
Test status
Simulation time 3929674411 ps
CPU time 16.14 seconds
Started Jul 30 06:19:19 PM PDT 24
Finished Jul 30 06:19:35 PM PDT 24
Peak memory 212980 kb
Host smart-ce5d4c80-094d-4c9a-aa3e-ea1745de9750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101521069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.101521069
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.483675785
Short name T20
Test name
Test status
Simulation time 1882915298 ps
CPU time 6.26 seconds
Started Jul 30 06:19:19 PM PDT 24
Finished Jul 30 06:19:25 PM PDT 24
Peak memory 212184 kb
Host smart-caf6cde0-b0e5-4c92-a358-a9686573495f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483675785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.483675785
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2261755933
Short name T59
Test name
Test status
Simulation time 1047932444 ps
CPU time 23.33 seconds
Started Jul 30 06:19:16 PM PDT 24
Finished Jul 30 06:19:40 PM PDT 24
Peak memory 214892 kb
Host smart-bf002bdc-56bc-4e7c-b378-432c37ed45de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261755933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2261755933
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2794398978
Short name T306
Test name
Test status
Simulation time 169333305 ps
CPU time 4.23 seconds
Started Jul 30 06:19:21 PM PDT 24
Finished Jul 30 06:19:25 PM PDT 24
Peak memory 212056 kb
Host smart-a10920fe-0abc-40d1-a4f2-852a90673502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794398978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2794398978
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4281037062
Short name T235
Test name
Test status
Simulation time 8529501669 ps
CPU time 150.61 seconds
Started Jul 30 06:19:20 PM PDT 24
Finished Jul 30 06:21:51 PM PDT 24
Peak memory 213468 kb
Host smart-ed3cdd12-3653-43c5-9ab8-086aee46244f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281037062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4281037062
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3032286289
Short name T254
Test name
Test status
Simulation time 172594225 ps
CPU time 9.29 seconds
Started Jul 30 06:19:18 PM PDT 24
Finished Jul 30 06:19:28 PM PDT 24
Peak memory 212952 kb
Host smart-94f0c39f-21a8-4d52-95de-0cf17741c0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032286289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3032286289
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2946564789
Short name T190
Test name
Test status
Simulation time 103494097 ps
CPU time 6.02 seconds
Started Jul 30 06:19:20 PM PDT 24
Finished Jul 30 06:19:26 PM PDT 24
Peak memory 212188 kb
Host smart-e7940647-689b-4fe6-8a34-7aee0f44328f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946564789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2946564789
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1877274555
Short name T175
Test name
Test status
Simulation time 452686810 ps
CPU time 20.4 seconds
Started Jul 30 06:19:21 PM PDT 24
Finished Jul 30 06:19:42 PM PDT 24
Peak memory 216240 kb
Host smart-dfb24d54-d5b1-4fd5-9740-a00633f90939
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877274555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1877274555
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1964534491
Short name T288
Test name
Test status
Simulation time 2260488697 ps
CPU time 7.58 seconds
Started Jul 30 06:19:22 PM PDT 24
Finished Jul 30 06:19:29 PM PDT 24
Peak memory 212216 kb
Host smart-0ef59e82-1606-4bee-a9e6-38466aa32dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964534491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1964534491
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4161116775
Short name T173
Test name
Test status
Simulation time 975981438 ps
CPU time 9.52 seconds
Started Jul 30 06:19:21 PM PDT 24
Finished Jul 30 06:19:30 PM PDT 24
Peak memory 213344 kb
Host smart-9d179f3e-3032-414a-bd72-8dde57057a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161116775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4161116775
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.674872754
Short name T224
Test name
Test status
Simulation time 94854295 ps
CPU time 5.45 seconds
Started Jul 30 06:19:22 PM PDT 24
Finished Jul 30 06:19:27 PM PDT 24
Peak memory 211856 kb
Host smart-5cdd3787-eecf-4acd-b2c0-840d0a7784ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674872754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.674872754
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1309053640
Short name T167
Test name
Test status
Simulation time 420174046 ps
CPU time 12.49 seconds
Started Jul 30 06:19:17 PM PDT 24
Finished Jul 30 06:19:30 PM PDT 24
Peak memory 214252 kb
Host smart-3a9e0b21-b5cf-42ef-840a-9e27f87bd8b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309053640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1309053640
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3949331676
Short name T155
Test name
Test status
Simulation time 989628487 ps
CPU time 7.65 seconds
Started Jul 30 06:19:22 PM PDT 24
Finished Jul 30 06:19:30 PM PDT 24
Peak memory 212028 kb
Host smart-4e455b91-7ce8-4182-afb3-950a563ea7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949331676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3949331676
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1339556858
Short name T203
Test name
Test status
Simulation time 6475563410 ps
CPU time 111.35 seconds
Started Jul 30 06:19:20 PM PDT 24
Finished Jul 30 06:21:11 PM PDT 24
Peak memory 226076 kb
Host smart-7ebcf4c6-2d81-450d-b56e-940f51a5f362
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339556858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1339556858
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3349114694
Short name T265
Test name
Test status
Simulation time 262533913 ps
CPU time 11.3 seconds
Started Jul 30 06:19:21 PM PDT 24
Finished Jul 30 06:19:32 PM PDT 24
Peak memory 211860 kb
Host smart-ff86b83e-15ea-41db-a5ab-793af11238ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349114694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3349114694
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3823735925
Short name T133
Test name
Test status
Simulation time 528232691 ps
CPU time 8.7 seconds
Started Jul 30 06:19:21 PM PDT 24
Finished Jul 30 06:19:30 PM PDT 24
Peak memory 212168 kb
Host smart-aefde5b0-aee5-42e4-8868-b1c12e54f55e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823735925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3823735925
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1884847973
Short name T147
Test name
Test status
Simulation time 651774766 ps
CPU time 7 seconds
Started Jul 30 06:19:21 PM PDT 24
Finished Jul 30 06:19:28 PM PDT 24
Peak memory 212104 kb
Host smart-59f21088-c1f3-4771-95e9-4956ff8036f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884847973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1884847973
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.498567775
Short name T262
Test name
Test status
Simulation time 175692994 ps
CPU time 4.39 seconds
Started Jul 30 06:19:21 PM PDT 24
Finished Jul 30 06:19:26 PM PDT 24
Peak memory 212028 kb
Host smart-96f59dc7-9ec9-4217-9325-16d8ec09a7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498567775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.498567775
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2467247356
Short name T255
Test name
Test status
Simulation time 3507142979 ps
CPU time 149.18 seconds
Started Jul 30 06:19:22 PM PDT 24
Finished Jul 30 06:21:51 PM PDT 24
Peak memory 225920 kb
Host smart-6d6fbfa1-189f-4e58-8411-e3d4f5c73bbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467247356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2467247356
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3071984509
Short name T141
Test name
Test status
Simulation time 251325534 ps
CPU time 11.49 seconds
Started Jul 30 06:19:25 PM PDT 24
Finished Jul 30 06:19:37 PM PDT 24
Peak memory 212836 kb
Host smart-f8882398-15f1-4588-9d63-1ac1e1bf0c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071984509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3071984509
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3540756611
Short name T135
Test name
Test status
Simulation time 98699157 ps
CPU time 5.54 seconds
Started Jul 30 06:19:22 PM PDT 24
Finished Jul 30 06:19:27 PM PDT 24
Peak memory 212228 kb
Host smart-fcf87a81-b29d-46e0-9a7f-f80763877571
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3540756611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3540756611
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.306945066
Short name T249
Test name
Test status
Simulation time 214532593 ps
CPU time 5.48 seconds
Started Jul 30 06:19:23 PM PDT 24
Finished Jul 30 06:19:29 PM PDT 24
Peak memory 212232 kb
Host smart-fd33f1b3-a710-4e7e-a35b-acf109a7a766
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306945066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.306945066
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3155377704
Short name T281
Test name
Test status
Simulation time 127166056 ps
CPU time 5.01 seconds
Started Jul 30 06:19:24 PM PDT 24
Finished Jul 30 06:19:29 PM PDT 24
Peak memory 212088 kb
Host smart-c56bf674-bac2-4cc6-b58b-0a3d8a5eb944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155377704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3155377704
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.4230531140
Short name T301
Test name
Test status
Simulation time 10990453490 ps
CPU time 67 seconds
Started Jul 30 06:19:26 PM PDT 24
Finished Jul 30 06:20:33 PM PDT 24
Peak memory 237596 kb
Host smart-5963e5ab-893b-4917-9165-ec0dbba184f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230531140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.4230531140
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4031790454
Short name T196
Test name
Test status
Simulation time 872702818 ps
CPU time 9.51 seconds
Started Jul 30 06:19:24 PM PDT 24
Finished Jul 30 06:19:34 PM PDT 24
Peak memory 212932 kb
Host smart-6272b15c-b6c1-45a4-afcb-d7b57a6d60a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031790454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.4031790454
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2020970587
Short name T185
Test name
Test status
Simulation time 142860445 ps
CPU time 6.77 seconds
Started Jul 30 06:19:23 PM PDT 24
Finished Jul 30 06:19:30 PM PDT 24
Peak memory 212140 kb
Host smart-f56aa7f7-6735-46e0-91ea-77bde0d52a11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020970587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2020970587
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2594892059
Short name T172
Test name
Test status
Simulation time 1243879322 ps
CPU time 13.37 seconds
Started Jul 30 06:19:25 PM PDT 24
Finished Jul 30 06:19:38 PM PDT 24
Peak memory 214376 kb
Host smart-b33950d4-3518-4903-8989-8358820c432c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594892059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2594892059
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1686400504
Short name T177
Test name
Test status
Simulation time 86328827 ps
CPU time 4.66 seconds
Started Jul 30 06:18:35 PM PDT 24
Finished Jul 30 06:18:40 PM PDT 24
Peak memory 212076 kb
Host smart-431bd9d5-9796-4c4b-839e-93fea05c8c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686400504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1686400504
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1410472996
Short name T212
Test name
Test status
Simulation time 11570710169 ps
CPU time 167.19 seconds
Started Jul 30 06:18:32 PM PDT 24
Finished Jul 30 06:21:19 PM PDT 24
Peak memory 238408 kb
Host smart-680816cc-4113-4cc2-b6dc-6fc4953c049d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410472996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.1410472996
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3127999620
Short name T243
Test name
Test status
Simulation time 556265535 ps
CPU time 9.45 seconds
Started Jul 30 06:18:34 PM PDT 24
Finished Jul 30 06:18:44 PM PDT 24
Peak memory 213104 kb
Host smart-1484cbad-34b1-4036-8c71-9670b0aa4f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127999620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3127999620
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.433467857
Short name T181
Test name
Test status
Simulation time 149204476 ps
CPU time 6.71 seconds
Started Jul 30 06:18:35 PM PDT 24
Finished Jul 30 06:18:42 PM PDT 24
Peak memory 212176 kb
Host smart-bf72c152-8cd5-436c-9764-e96007a73255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433467857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.433467857
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1581919849
Short name T28
Test name
Test status
Simulation time 188450786 ps
CPU time 53.39 seconds
Started Jul 30 06:18:32 PM PDT 24
Finished Jul 30 06:19:26 PM PDT 24
Peak memory 237436 kb
Host smart-9a80b41f-666b-4fe4-b9b8-d2ddcaf0da96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581919849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1581919849
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2548218448
Short name T232
Test name
Test status
Simulation time 285943612 ps
CPU time 6.3 seconds
Started Jul 30 06:18:30 PM PDT 24
Finished Jul 30 06:18:36 PM PDT 24
Peak memory 212200 kb
Host smart-2874230a-4dea-4fa9-8e33-0c6d37123f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548218448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2548218448
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.174173098
Short name T210
Test name
Test status
Simulation time 643038855 ps
CPU time 8.42 seconds
Started Jul 30 06:18:34 PM PDT 24
Finished Jul 30 06:18:43 PM PDT 24
Peak memory 212440 kb
Host smart-5b2ebb8a-77f2-49eb-9ecf-a6e88844e42a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174173098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.174173098
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3760180274
Short name T32
Test name
Test status
Simulation time 588972477 ps
CPU time 5.11 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:19:32 PM PDT 24
Peak memory 212036 kb
Host smart-d0616dad-a226-4157-ae1e-5db9cc47d180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760180274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3760180274
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3168249877
Short name T289
Test name
Test status
Simulation time 7294494854 ps
CPU time 89.47 seconds
Started Jul 30 06:19:28 PM PDT 24
Finished Jul 30 06:20:57 PM PDT 24
Peak memory 238540 kb
Host smart-5b2ab735-2d5f-4d40-b3ec-1251bafef552
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168249877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3168249877
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1829247986
Short name T187
Test name
Test status
Simulation time 214914281 ps
CPU time 9.7 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:19:37 PM PDT 24
Peak memory 213104 kb
Host smart-3985bdc7-c46d-4da6-9827-89b3e6b95851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829247986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1829247986
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2792759433
Short name T231
Test name
Test status
Simulation time 1003491609 ps
CPU time 5.36 seconds
Started Jul 30 06:19:23 PM PDT 24
Finished Jul 30 06:19:29 PM PDT 24
Peak memory 212164 kb
Host smart-e0f0b9c1-4f6c-4c8f-88f6-8b2ccaffdc0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792759433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2792759433
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2888787956
Short name T75
Test name
Test status
Simulation time 388805501 ps
CPU time 22.91 seconds
Started Jul 30 06:19:23 PM PDT 24
Finished Jul 30 06:19:46 PM PDT 24
Peak memory 217708 kb
Host smart-8c8f22f1-dd6c-4026-8808-3715b5cbf561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888787956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2888787956
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2811916178
Short name T257
Test name
Test status
Simulation time 88572454 ps
CPU time 4.27 seconds
Started Jul 30 06:19:29 PM PDT 24
Finished Jul 30 06:19:33 PM PDT 24
Peak memory 212096 kb
Host smart-03cb49e1-34f9-4ec2-8a86-8e2eb0a6c919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811916178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2811916178
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1016385400
Short name T321
Test name
Test status
Simulation time 2109168332 ps
CPU time 85.94 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:20:53 PM PDT 24
Peak memory 228520 kb
Host smart-15ab0f19-a2e3-48f7-80df-2c35d098f7cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016385400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1016385400
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.4172343227
Short name T223
Test name
Test status
Simulation time 617415348 ps
CPU time 9.29 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:19:37 PM PDT 24
Peak memory 212892 kb
Host smart-ad49d7ed-a1ec-49e5-be6a-42d1268cfdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172343227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.4172343227
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1330244639
Short name T137
Test name
Test status
Simulation time 524734397 ps
CPU time 6.23 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:19:33 PM PDT 24
Peak memory 212132 kb
Host smart-13a25006-daf2-4fe9-bcb1-7e62ae750736
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330244639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1330244639
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2205969642
Short name T77
Test name
Test status
Simulation time 433915023 ps
CPU time 12.74 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:19:40 PM PDT 24
Peak memory 213452 kb
Host smart-51a5f381-d9f0-4a72-8aa8-f408f1d5b1bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205969642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2205969642
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3060584534
Short name T293
Test name
Test status
Simulation time 494805691 ps
CPU time 7.66 seconds
Started Jul 30 06:19:28 PM PDT 24
Finished Jul 30 06:19:35 PM PDT 24
Peak memory 212076 kb
Host smart-1c2787aa-febc-4b0c-b895-8ffb6f142399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060584534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3060584534
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2145791908
Short name T207
Test name
Test status
Simulation time 2759514568 ps
CPU time 139.65 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:21:46 PM PDT 24
Peak memory 238624 kb
Host smart-ef200a80-3655-444d-b919-a0b912cad311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145791908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2145791908
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.490393397
Short name T171
Test name
Test status
Simulation time 1521678723 ps
CPU time 9.53 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:19:37 PM PDT 24
Peak memory 213112 kb
Host smart-c6ff3ce0-5ffa-49b1-8522-0798211e2eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490393397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.490393397
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4139235273
Short name T7
Test name
Test status
Simulation time 273783545 ps
CPU time 6.42 seconds
Started Jul 30 06:19:29 PM PDT 24
Finished Jul 30 06:19:35 PM PDT 24
Peak memory 212160 kb
Host smart-667ddcd7-73b8-41d8-9e40-cc1b36c52db7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139235273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4139235273
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.463468147
Short name T244
Test name
Test status
Simulation time 1022006414 ps
CPU time 8.32 seconds
Started Jul 30 06:19:30 PM PDT 24
Finished Jul 30 06:19:39 PM PDT 24
Peak memory 212088 kb
Host smart-f7bef445-4db9-44f9-8138-92af90a9877a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463468147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.463468147
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3723378929
Short name T308
Test name
Test status
Simulation time 86527589 ps
CPU time 4.25 seconds
Started Jul 30 06:19:30 PM PDT 24
Finished Jul 30 06:19:35 PM PDT 24
Peak memory 212016 kb
Host smart-ff677212-9dda-4280-b80b-ed4ae775e681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723378929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3723378929
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.247344549
Short name T46
Test name
Test status
Simulation time 38668320314 ps
CPU time 104.7 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:21:12 PM PDT 24
Peak memory 238372 kb
Host smart-bca901cc-17d9-4ca2-b28d-f13cbfcf216e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247344549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.247344549
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3004436516
Short name T250
Test name
Test status
Simulation time 507578755 ps
CPU time 11.2 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:19:38 PM PDT 24
Peak memory 212984 kb
Host smart-61a2306a-508b-4853-8949-aa48dc49c4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004436516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3004436516
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.208729892
Short name T166
Test name
Test status
Simulation time 617936626 ps
CPU time 5.51 seconds
Started Jul 30 06:19:28 PM PDT 24
Finished Jul 30 06:19:33 PM PDT 24
Peak memory 212196 kb
Host smart-73d25cc4-9257-4e97-a33a-7927942e01d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208729892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.208729892
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.222512341
Short name T266
Test name
Test status
Simulation time 300684038 ps
CPU time 13.31 seconds
Started Jul 30 06:19:27 PM PDT 24
Finished Jul 30 06:19:41 PM PDT 24
Peak memory 214516 kb
Host smart-589c86b4-8a0b-417a-9c9d-440d1bf22d0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222512341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.222512341
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.288129617
Short name T10
Test name
Test status
Simulation time 131688334 ps
CPU time 5.11 seconds
Started Jul 30 06:19:30 PM PDT 24
Finished Jul 30 06:19:35 PM PDT 24
Peak memory 212100 kb
Host smart-9d30eca2-90c2-41aa-adb2-f88925be59ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288129617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.288129617
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3525613949
Short name T318
Test name
Test status
Simulation time 3335136628 ps
CPU time 95.85 seconds
Started Jul 30 06:19:32 PM PDT 24
Finished Jul 30 06:21:08 PM PDT 24
Peak memory 238508 kb
Host smart-86e9920d-c477-457d-9cde-9a443f757743
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525613949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3525613949
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1057706998
Short name T165
Test name
Test status
Simulation time 688155023 ps
CPU time 11.06 seconds
Started Jul 30 06:19:30 PM PDT 24
Finished Jul 30 06:19:41 PM PDT 24
Peak memory 212880 kb
Host smart-0e2f3715-f834-4729-b9ef-3a4136c5e073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057706998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1057706998
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1797512965
Short name T143
Test name
Test status
Simulation time 175913964 ps
CPU time 5.37 seconds
Started Jul 30 06:19:30 PM PDT 24
Finished Jul 30 06:19:35 PM PDT 24
Peak memory 212192 kb
Host smart-238d87c1-d253-49ba-b0aa-33ca75528494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797512965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1797512965
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3080886554
Short name T125
Test name
Test status
Simulation time 180238103 ps
CPU time 8.16 seconds
Started Jul 30 06:19:30 PM PDT 24
Finished Jul 30 06:19:38 PM PDT 24
Peak memory 212136 kb
Host smart-eec3e49e-1bdf-4156-b8b3-09f289454024
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080886554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3080886554
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2788220263
Short name T123
Test name
Test status
Simulation time 335290494 ps
CPU time 4.25 seconds
Started Jul 30 06:19:34 PM PDT 24
Finished Jul 30 06:19:38 PM PDT 24
Peak memory 212048 kb
Host smart-505fa324-cb11-4855-bfbb-f6c6b5c8805e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788220263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2788220263
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.718090608
Short name T49
Test name
Test status
Simulation time 5646611308 ps
CPU time 107.91 seconds
Started Jul 30 06:19:32 PM PDT 24
Finished Jul 30 06:21:20 PM PDT 24
Peak memory 238524 kb
Host smart-65893cf1-a116-467f-8e2d-969a83045ae9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718090608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.718090608
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.881792286
Short name T325
Test name
Test status
Simulation time 99204981 ps
CPU time 5.58 seconds
Started Jul 30 06:19:32 PM PDT 24
Finished Jul 30 06:19:38 PM PDT 24
Peak memory 212344 kb
Host smart-697aa560-b794-4e14-9d82-19ae3d0cd0bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881792286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.881792286
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2132127194
Short name T78
Test name
Test status
Simulation time 587619117 ps
CPU time 16.45 seconds
Started Jul 30 06:19:34 PM PDT 24
Finished Jul 30 06:19:50 PM PDT 24
Peak memory 215580 kb
Host smart-d77b61eb-ed5f-4651-83fe-01a9a04a1378
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132127194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2132127194
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.807549712
Short name T136
Test name
Test status
Simulation time 591778431 ps
CPU time 4.45 seconds
Started Jul 30 06:19:35 PM PDT 24
Finished Jul 30 06:19:39 PM PDT 24
Peak memory 212028 kb
Host smart-b69307c4-0262-4936-958d-bcdddf240089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807549712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.807549712
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4235740106
Short name T307
Test name
Test status
Simulation time 5229019833 ps
CPU time 171.95 seconds
Started Jul 30 06:19:35 PM PDT 24
Finished Jul 30 06:22:27 PM PDT 24
Peak memory 214748 kb
Host smart-b303ac51-d48e-494f-850c-9d1880a6a6fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235740106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4235740106
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3420151060
Short name T174
Test name
Test status
Simulation time 259291644 ps
CPU time 11.69 seconds
Started Jul 30 06:19:35 PM PDT 24
Finished Jul 30 06:19:47 PM PDT 24
Peak memory 212940 kb
Host smart-7cbd789e-107d-4e67-8122-cd3a1457f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420151060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3420151060
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.104773060
Short name T4
Test name
Test status
Simulation time 268017759 ps
CPU time 6.38 seconds
Started Jul 30 06:19:38 PM PDT 24
Finished Jul 30 06:19:44 PM PDT 24
Peak memory 212144 kb
Host smart-103c25a3-66fe-42a4-b1e5-51df3bc8a887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104773060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.104773060
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1486110512
Short name T154
Test name
Test status
Simulation time 466338375 ps
CPU time 7.71 seconds
Started Jul 30 06:19:37 PM PDT 24
Finished Jul 30 06:19:45 PM PDT 24
Peak memory 212100 kb
Host smart-89b3977d-5659-427c-aa97-c3bb5459c9dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486110512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1486110512
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2905696051
Short name T276
Test name
Test status
Simulation time 41991049050 ps
CPU time 1779.57 seconds
Started Jul 30 06:19:38 PM PDT 24
Finished Jul 30 06:49:18 PM PDT 24
Peak memory 237356 kb
Host smart-db3a4079-a8ba-4925-8178-9e2eba41845e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905696051 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2905696051
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2046480673
Short name T291
Test name
Test status
Simulation time 337714871 ps
CPU time 4.48 seconds
Started Jul 30 06:19:34 PM PDT 24
Finished Jul 30 06:19:38 PM PDT 24
Peak memory 212040 kb
Host smart-13e0156a-4c7c-4e53-adff-5db7ca2bf788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046480673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2046480673
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3311088314
Short name T202
Test name
Test status
Simulation time 30242665657 ps
CPU time 124.79 seconds
Started Jul 30 06:19:36 PM PDT 24
Finished Jul 30 06:21:41 PM PDT 24
Peak memory 214432 kb
Host smart-227955ee-ada3-4428-b142-997ad77112ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311088314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3311088314
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2134000722
Short name T245
Test name
Test status
Simulation time 610419898 ps
CPU time 11.35 seconds
Started Jul 30 06:19:35 PM PDT 24
Finished Jul 30 06:19:47 PM PDT 24
Peak memory 212980 kb
Host smart-f965d4c9-1374-406e-a652-53915d3d6a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134000722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2134000722
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.219012115
Short name T303
Test name
Test status
Simulation time 142785104 ps
CPU time 6.31 seconds
Started Jul 30 06:19:34 PM PDT 24
Finished Jul 30 06:19:41 PM PDT 24
Peak memory 212132 kb
Host smart-d9472bc3-71f5-43b3-951c-5c4d7f819378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219012115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.219012115
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.168828523
Short name T73
Test name
Test status
Simulation time 2626994145 ps
CPU time 12.34 seconds
Started Jul 30 06:19:35 PM PDT 24
Finished Jul 30 06:19:48 PM PDT 24
Peak memory 213576 kb
Host smart-f7f8aa68-f2d5-4c91-abc4-9d2eb6a6114d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168828523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.168828523
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.658208577
Short name T98
Test name
Test status
Simulation time 40996034061 ps
CPU time 831.9 seconds
Started Jul 30 06:19:45 PM PDT 24
Finished Jul 30 06:33:38 PM PDT 24
Peak memory 236624 kb
Host smart-37703e0e-6926-429d-8a87-07611994e6c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658208577 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.658208577
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1550332241
Short name T36
Test name
Test status
Simulation time 334841948 ps
CPU time 4.27 seconds
Started Jul 30 06:19:41 PM PDT 24
Finished Jul 30 06:19:45 PM PDT 24
Peak memory 212108 kb
Host smart-f86aa6de-1a62-456a-87d6-72a7e5962bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550332241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1550332241
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1336135493
Short name T192
Test name
Test status
Simulation time 3077227362 ps
CPU time 79.25 seconds
Started Jul 30 06:19:37 PM PDT 24
Finished Jul 30 06:20:56 PM PDT 24
Peak memory 238508 kb
Host smart-af889f76-6f7f-4372-9ff0-3368257cc111
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336135493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1336135493
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1017268930
Short name T6
Test name
Test status
Simulation time 677147331 ps
CPU time 9.97 seconds
Started Jul 30 06:19:36 PM PDT 24
Finished Jul 30 06:19:46 PM PDT 24
Peak memory 215408 kb
Host smart-045a6b64-64f0-4e81-87cb-fc2a729347fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017268930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1017268930
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2909916101
Short name T290
Test name
Test status
Simulation time 136662118 ps
CPU time 6.56 seconds
Started Jul 30 06:19:37 PM PDT 24
Finished Jul 30 06:19:43 PM PDT 24
Peak memory 212108 kb
Host smart-cb1b6670-57c3-4541-8a40-c034874adb2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2909916101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2909916101
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4051105114
Short name T322
Test name
Test status
Simulation time 164020371 ps
CPU time 8.24 seconds
Started Jul 30 06:19:45 PM PDT 24
Finished Jul 30 06:19:54 PM PDT 24
Peak memory 212036 kb
Host smart-839b651e-0fed-4c14-b3ee-4730e94b278f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051105114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4051105114
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.887266915
Short name T282
Test name
Test status
Simulation time 27707971987 ps
CPU time 446.63 seconds
Started Jul 30 06:19:45 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 234852 kb
Host smart-7a384e42-47d8-4542-9540-2eb4b5bf1d51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887266915 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.887266915
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1222270160
Short name T182
Test name
Test status
Simulation time 2080991671 ps
CPU time 5.19 seconds
Started Jul 30 06:19:44 PM PDT 24
Finished Jul 30 06:19:49 PM PDT 24
Peak memory 212020 kb
Host smart-6bcf40dc-ceb0-4ae0-95bd-623a0436823a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222270160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1222270160
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2091022160
Short name T299
Test name
Test status
Simulation time 18595125137 ps
CPU time 131.32 seconds
Started Jul 30 06:19:40 PM PDT 24
Finished Jul 30 06:21:52 PM PDT 24
Peak memory 229044 kb
Host smart-fda0e867-2b8f-42c9-b8bc-93417a9d582f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091022160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2091022160
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4038646129
Short name T193
Test name
Test status
Simulation time 176260748 ps
CPU time 9.54 seconds
Started Jul 30 06:19:40 PM PDT 24
Finished Jul 30 06:19:49 PM PDT 24
Peak memory 212916 kb
Host smart-a0482283-b4ee-4ea6-966a-5c313ca9f428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038646129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4038646129
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1142861794
Short name T96
Test name
Test status
Simulation time 141768132 ps
CPU time 6.4 seconds
Started Jul 30 06:19:38 PM PDT 24
Finished Jul 30 06:19:44 PM PDT 24
Peak memory 212224 kb
Host smart-0044deff-7892-4155-b1df-10c3f30eea77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1142861794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1142861794
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3571700225
Short name T145
Test name
Test status
Simulation time 299565629 ps
CPU time 15.55 seconds
Started Jul 30 06:19:41 PM PDT 24
Finished Jul 30 06:19:56 PM PDT 24
Peak memory 216348 kb
Host smart-c0e6e8b5-b6ca-4843-869b-b70756e33948
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571700225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3571700225
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.1939019100
Short name T280
Test name
Test status
Simulation time 87803692 ps
CPU time 4.23 seconds
Started Jul 30 06:18:34 PM PDT 24
Finished Jul 30 06:18:38 PM PDT 24
Peak memory 212028 kb
Host smart-931c1883-0ad2-4106-bc9f-ae6d39aeafef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939019100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.1939019100
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2685976195
Short name T157
Test name
Test status
Simulation time 3301040990 ps
CPU time 79.3 seconds
Started Jul 30 06:18:33 PM PDT 24
Finished Jul 30 06:19:52 PM PDT 24
Peak memory 213692 kb
Host smart-a08a6948-a647-4bf5-88f7-df976cb837ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685976195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2685976195
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1243517054
Short name T124
Test name
Test status
Simulation time 175011247 ps
CPU time 9.81 seconds
Started Jul 30 06:18:36 PM PDT 24
Finished Jul 30 06:18:46 PM PDT 24
Peak memory 213056 kb
Host smart-e5e0e004-9d3a-4fc0-a6ad-56623f099a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243517054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1243517054
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.211362845
Short name T220
Test name
Test status
Simulation time 136196982 ps
CPU time 6.12 seconds
Started Jul 30 06:18:35 PM PDT 24
Finished Jul 30 06:18:41 PM PDT 24
Peak memory 212160 kb
Host smart-7a89c0d1-9e1d-413f-8ca4-08c92cb76c63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211362845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.211362845
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.260524471
Short name T317
Test name
Test status
Simulation time 370187755 ps
CPU time 5.35 seconds
Started Jul 30 06:18:37 PM PDT 24
Finished Jul 30 06:18:42 PM PDT 24
Peak memory 212164 kb
Host smart-ba46b284-b8b9-4fd3-98b2-438e25f1fbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260524471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.260524471
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2013718903
Short name T237
Test name
Test status
Simulation time 2709598754 ps
CPU time 15.78 seconds
Started Jul 30 06:18:33 PM PDT 24
Finished Jul 30 06:18:48 PM PDT 24
Peak memory 213384 kb
Host smart-44437e03-60a2-473e-8eef-40bab9f18b97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013718903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2013718903
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1775568114
Short name T128
Test name
Test status
Simulation time 259961286 ps
CPU time 5 seconds
Started Jul 30 06:18:35 PM PDT 24
Finished Jul 30 06:18:41 PM PDT 24
Peak memory 212028 kb
Host smart-71314909-01eb-4c67-9214-88fd1f0082ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775568114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1775568114
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.552178820
Short name T239
Test name
Test status
Simulation time 2459594459 ps
CPU time 142.41 seconds
Started Jul 30 06:18:38 PM PDT 24
Finished Jul 30 06:21:00 PM PDT 24
Peak memory 237860 kb
Host smart-f3f366d1-bfb8-45d2-806b-43c92eac124a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552178820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.552178820
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.520073944
Short name T186
Test name
Test status
Simulation time 168753612 ps
CPU time 9.72 seconds
Started Jul 30 06:18:37 PM PDT 24
Finished Jul 30 06:18:47 PM PDT 24
Peak memory 212844 kb
Host smart-c9a26fb3-4a94-42d3-a733-eaa6517e7185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520073944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.520073944
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1572268037
Short name T214
Test name
Test status
Simulation time 200759607 ps
CPU time 5.45 seconds
Started Jul 30 06:18:36 PM PDT 24
Finished Jul 30 06:18:42 PM PDT 24
Peak memory 212216 kb
Host smart-f1d61dd7-9078-4706-a32b-67a2a9639f99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572268037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1572268037
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2462439242
Short name T229
Test name
Test status
Simulation time 784452102 ps
CPU time 6.24 seconds
Started Jul 30 06:18:36 PM PDT 24
Finished Jul 30 06:18:42 PM PDT 24
Peak memory 212280 kb
Host smart-aaf6caa9-a285-4c1c-bd48-a6c44e87b4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462439242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2462439242
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3530839730
Short name T324
Test name
Test status
Simulation time 215719683 ps
CPU time 12.13 seconds
Started Jul 30 06:18:39 PM PDT 24
Finished Jul 30 06:18:52 PM PDT 24
Peak memory 214312 kb
Host smart-afcaa529-e26f-4b3d-a42e-50b9d82c616e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530839730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3530839730
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4079124970
Short name T295
Test name
Test status
Simulation time 86334251 ps
CPU time 4.34 seconds
Started Jul 30 06:18:40 PM PDT 24
Finished Jul 30 06:18:44 PM PDT 24
Peak memory 212032 kb
Host smart-2048892e-f2dd-4185-a5b0-c3c43130d010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079124970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4079124970
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1294101578
Short name T113
Test name
Test status
Simulation time 1520785161 ps
CPU time 77.8 seconds
Started Jul 30 06:18:37 PM PDT 24
Finished Jul 30 06:19:55 PM PDT 24
Peak memory 238352 kb
Host smart-dd675884-362d-4d84-b54a-d01bca58233e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294101578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1294101578
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.19031732
Short name T126
Test name
Test status
Simulation time 252600952 ps
CPU time 11.33 seconds
Started Jul 30 06:18:38 PM PDT 24
Finished Jul 30 06:18:49 PM PDT 24
Peak memory 213464 kb
Host smart-80bd4d08-3f5a-4dc8-a28d-e45bd5016f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19031732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.19031732
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.266860685
Short name T267
Test name
Test status
Simulation time 604809857 ps
CPU time 6.49 seconds
Started Jul 30 06:18:39 PM PDT 24
Finished Jul 30 06:18:46 PM PDT 24
Peak memory 212160 kb
Host smart-8a5a677f-8e43-449e-9d16-d9ba2a59b62e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=266860685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.266860685
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1421866735
Short name T319
Test name
Test status
Simulation time 101500368 ps
CPU time 5.64 seconds
Started Jul 30 06:18:39 PM PDT 24
Finished Jul 30 06:18:45 PM PDT 24
Peak memory 212152 kb
Host smart-26b2d5c4-f431-4ab7-9418-de759d1f0ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421866735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1421866735
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.560149963
Short name T241
Test name
Test status
Simulation time 325042309 ps
CPU time 7.2 seconds
Started Jul 30 06:18:37 PM PDT 24
Finished Jul 30 06:18:45 PM PDT 24
Peak memory 212148 kb
Host smart-28254ee6-5c57-4fea-adc0-e307ba7f728d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560149963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.560149963
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3305694063
Short name T287
Test name
Test status
Simulation time 922812390 ps
CPU time 4.24 seconds
Started Jul 30 06:18:41 PM PDT 24
Finished Jul 30 06:18:45 PM PDT 24
Peak memory 212096 kb
Host smart-b82b194f-0638-4afe-9e51-2527e4312ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305694063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3305694063
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3189626004
Short name T271
Test name
Test status
Simulation time 1220076488 ps
CPU time 70.39 seconds
Started Jul 30 06:18:50 PM PDT 24
Finished Jul 30 06:20:00 PM PDT 24
Peak memory 233648 kb
Host smart-019e17a8-c492-4a40-87d4-4f045d4c411e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189626004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3189626004
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2122829649
Short name T184
Test name
Test status
Simulation time 2775833211 ps
CPU time 9.48 seconds
Started Jul 30 06:18:41 PM PDT 24
Finished Jul 30 06:18:50 PM PDT 24
Peak memory 212988 kb
Host smart-493cdd6f-6043-4121-957a-d3e22faf4fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122829649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2122829649
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3915049329
Short name T144
Test name
Test status
Simulation time 360997780 ps
CPU time 5.46 seconds
Started Jul 30 06:18:46 PM PDT 24
Finished Jul 30 06:18:51 PM PDT 24
Peak memory 212208 kb
Host smart-bcfbed56-aa99-48de-959d-77650df5173e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915049329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3915049329
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.71989118
Short name T227
Test name
Test status
Simulation time 330264925 ps
CPU time 5.65 seconds
Started Jul 30 06:18:40 PM PDT 24
Finished Jul 30 06:18:46 PM PDT 24
Peak memory 212228 kb
Host smart-beb82f8d-49bc-46ca-918b-a9129465926e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71989118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.71989118
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3540739540
Short name T158
Test name
Test status
Simulation time 328125243 ps
CPU time 12.45 seconds
Started Jul 30 06:18:42 PM PDT 24
Finished Jul 30 06:18:54 PM PDT 24
Peak memory 214328 kb
Host smart-5ffc22e7-de82-49f7-9922-a9b97ab4a51d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540739540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3540739540
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2124897246
Short name T53
Test name
Test status
Simulation time 149787365771 ps
CPU time 3127.67 seconds
Started Jul 30 06:18:49 PM PDT 24
Finished Jul 30 07:10:58 PM PDT 24
Peak memory 252936 kb
Host smart-416e4bbb-bd69-4894-9eea-e1081de08d54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124897246 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2124897246
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3234530450
Short name T5
Test name
Test status
Simulation time 480676855 ps
CPU time 5.14 seconds
Started Jul 30 06:18:49 PM PDT 24
Finished Jul 30 06:18:55 PM PDT 24
Peak memory 212000 kb
Host smart-5408f155-117d-4933-9ac2-7397f1f6478b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234530450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3234530450
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3885116501
Short name T216
Test name
Test status
Simulation time 5726963792 ps
CPU time 70.22 seconds
Started Jul 30 06:18:40 PM PDT 24
Finished Jul 30 06:19:51 PM PDT 24
Peak memory 214556 kb
Host smart-234ade50-b9b1-44ae-83de-dcee8c43d03d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885116501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3885116501
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1884204031
Short name T161
Test name
Test status
Simulation time 1474239850 ps
CPU time 10.96 seconds
Started Jul 30 06:18:50 PM PDT 24
Finished Jul 30 06:19:01 PM PDT 24
Peak memory 213136 kb
Host smart-35730dc7-114d-40cb-b8d2-25c7f690e253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884204031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1884204031
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2622717913
Short name T178
Test name
Test status
Simulation time 524074907 ps
CPU time 6.29 seconds
Started Jul 30 06:18:42 PM PDT 24
Finished Jul 30 06:18:49 PM PDT 24
Peak memory 212160 kb
Host smart-af5a32be-bc1b-4d67-87fa-06f78fd785c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622717913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2622717913
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2309358579
Short name T132
Test name
Test status
Simulation time 273843013 ps
CPU time 6.15 seconds
Started Jul 30 06:18:40 PM PDT 24
Finished Jul 30 06:18:46 PM PDT 24
Peak memory 212168 kb
Host smart-89c004c7-7ef1-4341-b2fc-9dfbe9857fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309358579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2309358579
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3266239191
Short name T149
Test name
Test status
Simulation time 276454585 ps
CPU time 15.22 seconds
Started Jul 30 06:18:40 PM PDT 24
Finished Jul 30 06:18:56 PM PDT 24
Peak memory 213972 kb
Host smart-a10f49d7-36ee-4fcf-bf24-c76302afd663
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266239191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3266239191
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1349579423
Short name T55
Test name
Test status
Simulation time 112602832007 ps
CPU time 1224.53 seconds
Started Jul 30 06:18:43 PM PDT 24
Finished Jul 30 06:39:07 PM PDT 24
Peak memory 236648 kb
Host smart-56a5e660-f222-4cad-8390-a57da3299909
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349579423 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1349579423
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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