SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
87.50 | 87.50 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
rom_ctrl_tlul_cg | 87.50 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
87.50 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 1 | 7 | 87.50 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_regs_req_check | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
cp_rom_invalid_condition | 2 | 1 | 1 | 50.00 | 100 | 1 | 1 | 0 | |
cp_rom_req_check | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
req_after_done | 1778543 | 1 | T3 | 88371 | T9 | 6212 | T10 | 3 | ||||
req_and_done | 1 | 1 | T100 | 1 | - | - | - | - | ||||
req_before_done | 3 | 1 | T27 | 1 | T101 | 2 | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
check_invalid | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
check_valid | 82128130 | 1 | T1 | 8388 | T2 | 25110 | T3 | 176168 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
req_after_done | 1794077 | 1 | T3 | 106771 | T5 | 1 | T7 | 6 | ||||
req_and_done | 69 | 1 | T5 | 1 | T7 | 1 | T17 | 1 | ||||
req_before_done | 164 | 1 | T3 | 3 | T9 | 3 | T12 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |