Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3419432

1

T3

69765

T5

53

T7

244

full_word

2172381

1

T3

44332

T5

7

T7

24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5591463	1			T3	114097		T5	60		T7	268
auto[TlIntgErrCmd]	107	1			T54	7		T55	5		T56	4
auto[TlIntgErrData]	120	1			T54	4		T55	6		T56	7
auto[TlIntgErrBoth]	123	1			T54	9		T55	9		T56	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

870290

1

T3

17899

T5

60

T7

268

auto[1]

4721523

1

T3

96198

T9

126042

T11

146269

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	358951	1			T3	7528		T5	53		T7	244
auto[TlIntgErrNone]	partial	auto[1]	3060161	1			T3	62237		T9	80517		T11	96189
auto[TlIntgErrNone]	full_word	auto[0]	511167	1			T3	10371		T5	7		T7	24
auto[TlIntgErrNone]	full_word	auto[1]	1661184	1			T3	33961		T9	45525		T11	50080
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T54	2		T55	2		T56	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T54	4		T55	3		T56	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T109	1		T105	1		T107	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T54	1		T109	1		T103	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T54	3		T55	4		T56	6
auto[TlIntgErrData]	partial	auto[1]	42	1			T54	1		T55	1		T110	2
auto[TlIntgErrData]	full_word	auto[0]	10	1			T55	1		T110	1		T108	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T56	1		T111	1		T104	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T54	4		T55	4		T56	3
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T54	5		T55	5		T56	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T104	1		T106	1		T112	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T108	1		T113	1		T107	1