Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3056640

1

T2

284

T4

115

T7

84

full_word

1933411

1

T2

33

T4

9

T7

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4989731	1			T2	317		T4	124		T7	92
auto[TlIntgErrCmd]	104	1			T72	8		T73	4		T74	6
auto[TlIntgErrData]	113	1			T72	5		T73	2		T74	5
auto[TlIntgErrBoth]	103	1			T72	7		T73	4		T74	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

778290

1

T2

317

T4

124

T7

92

auto[1]

4211761

1

T15

511021

T18

202215

T19

151596

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	323472	1			T2	284		T4	115		T7	84
auto[TlIntgErrNone]	partial	auto[1]	2732877	1			T15	332934		T18	130995		T19	95708
auto[TlIntgErrNone]	full_word	auto[0]	454670	1			T2	33		T4	9		T7	8
auto[TlIntgErrNone]	full_word	auto[1]	1478712	1			T15	178087		T18	71220		T19	55888
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T72	3		T73	1		T74	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T72	4		T73	1		T74	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T73	1		T74	1		T112	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T72	1		T73	1		T109	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T72	4		T115	3		T110	3
auto[TlIntgErrData]	partial	auto[1]	56	1			T72	1		T73	1		T74	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T115	1		T114	1		T116	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T73	1		T74	1		T109	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T72	5		T74	3		T109	5
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T72	2		T73	3		T74	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T73	1		T117	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T74	1		T112	1		T116	1