Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	86157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2969983

1

T1

12

T4

61173

T5

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	767541	1			T1	12		T4	15770		T5	129
values[0x0]	1123316	1			T4	23162		T11	23419		T12	22544
values[0x1]	1165283	1			T4	23954		T11	24671		T12	23541

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47435	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3008705

1

T1

12

T4

61933

T5

83

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11172	1			T4	205		T11	263		T12	232
valid_sources[0x01]	12344	1			T4	174		T11	277		T12	287
valid_sources[0x02]	11706	1			T4	484		T11	237		T16	5
valid_sources[0x03]	12385	1			T4	326		T11	233		T12	225
valid_sources[0x04]	12277	1			T4	445		T7	1		T11	291
valid_sources[0x05]	11724	1			T4	258		T11	248		T16	2
valid_sources[0x06]	11454	1			T4	42		T7	1		T11	218
valid_sources[0x07]	13053	1			T4	653		T7	1		T11	251
valid_sources[0x08]	12303	1			T4	500		T5	16		T11	249
valid_sources[0x09]	11820	1			T4	113		T7	2		T11	251
valid_sources[0x0a]	12663	1			T7	1		T11	289		T16	10
valid_sources[0x0b]	11513	1			T4	112		T11	233		T12	257
valid_sources[0x0c]	10765	1			T4	3		T7	1		T11	252
valid_sources[0x0d]	11725	1			T4	167		T11	243		T12	239
valid_sources[0x0e]	11900	1			T7	1		T11	218		T16	8
valid_sources[0x0f]	12098	1			T11	254		T16	6		T12	219
valid_sources[0x10]	10673	1			T11	254		T16	2		T12	236
valid_sources[0x11]	12151	1			T4	204		T11	241		T12	266
valid_sources[0x12]	11023	1			T4	701		T11	248		T12	240
valid_sources[0x13]	12267	1			T7	1		T11	231		T16	6
valid_sources[0x14]	12373	1			T4	497		T11	250		T12	218
valid_sources[0x15]	11660	1			T4	375		T7	2		T11	231
valid_sources[0x16]	10404	1			T7	1		T11	262		T16	6
valid_sources[0x17]	12380	1			T4	1003		T11	265		T16	2
valid_sources[0x18]	11308	1			T4	9		T7	1		T11	253
valid_sources[0x19]	11322	1			T7	1		T11	222		T12	246
valid_sources[0x1a]	13934	1			T4	1104		T11	286		T12	249
valid_sources[0x1b]	12660	1			T7	1		T11	252		T12	263
valid_sources[0x1c]	11410	1			T4	64		T11	227		T12	215
valid_sources[0x1d]	12562	1			T4	859		T11	263		T12	256
valid_sources[0x1e]	11593	1			T11	248		T12	241		T18	669
valid_sources[0x1f]	10666	1			T4	30		T11	199		T16	6
valid_sources[0x20]	13978	1			T4	1		T7	2		T11	294
valid_sources[0x21]	11779	1			T4	286		T11	296		T16	1
valid_sources[0x22]	11474	1			T4	129		T11	269		T16	1
valid_sources[0x23]	11810	1			T4	112		T11	251		T12	246
valid_sources[0x24]	11039	1			T4	395		T7	1		T11	216
valid_sources[0x25]	11479	1			T4	167		T11	234		T12	238
valid_sources[0x26]	12263	1			T4	452		T11	233		T16	6
valid_sources[0x27]	11103	1			T11	270		T12	206		T18	633
valid_sources[0x28]	12879	1			T4	786		T11	271		T16	5
valid_sources[0x29]	12952	1			T7	1		T11	216		T16	1
valid_sources[0x2a]	10696	1			T11	314		T12	242		T18	636
valid_sources[0x2b]	12398	1			T4	390		T11	220		T12	232
valid_sources[0x2c]	12136	1			T4	47		T7	1		T11	266
valid_sources[0x2d]	12364	1			T11	274		T16	9		T12	228
valid_sources[0x2e]	12883	1			T4	651		T7	3		T11	227
valid_sources[0x2f]	10568	1			T4	152		T7	1		T11	224
valid_sources[0x30]	10573	1			T11	253		T12	254		T18	660
valid_sources[0x31]	12103	1			T4	928		T11	225		T12	245
valid_sources[0x32]	11626	1			T4	179		T11	234		T12	223
valid_sources[0x33]	10487	1			T4	110		T11	240		T16	2
valid_sources[0x34]	11099	1			T4	213		T11	314		T12	239
valid_sources[0x35]	12354	1			T11	256		T12	276		T18	675
valid_sources[0x36]	11414	1			T11	260		T12	242		T18	616
valid_sources[0x37]	11554	1			T7	1		T11	252		T12	317
valid_sources[0x38]	11598	1			T4	318		T7	2		T11	269
valid_sources[0x39]	11500	1			T4	5		T11	221		T12	252
valid_sources[0x3a]	12324	1			T4	545		T7	1		T11	296
valid_sources[0x3b]	11941	1			T4	509		T7	1		T10	14
valid_sources[0x3c]	13183	1			T4	1376		T11	301		T16	1
valid_sources[0x3d]	10838	1			T11	250		T12	222		T18	659
valid_sources[0x3e]	11095	1			T4	177		T7	1		T11	249
valid_sources[0x3f]	13886	1			T4	228		T7	1		T11	256
valid_sources[0x40]	11531	1			T4	340		T11	285		T12	251
valid_sources[0x41]	11491	1			T4	13		T11	227		T12	246
valid_sources[0x42]	11622	1			T4	2		T7	1		T11	243
valid_sources[0x43]	11242	1			T11	261		T16	9		T12	218
valid_sources[0x44]	11477	1			T11	233		T12	225		T18	641
valid_sources[0x45]	10736	1			T4	317		T11	253		T12	248
valid_sources[0x46]	10323	1			T4	3		T11	249		T12	232
valid_sources[0x47]	11940	1			T1	2		T4	9		T7	1
valid_sources[0x48]	12137	1			T4	129		T11	240		T12	244
valid_sources[0x49]	11961	1			T4	139		T11	262		T16	3
valid_sources[0x4a]	10961	1			T4	26		T11	236		T12	223
valid_sources[0x4b]	10563	1			T11	235		T12	232		T18	574
valid_sources[0x4c]	11958	1			T4	448		T11	259		T12	229
valid_sources[0x4d]	10437	1			T11	236		T12	251		T18	550
valid_sources[0x4e]	12761	1			T4	140		T7	1		T11	246
valid_sources[0x4f]	12114	1			T1	1		T4	428		T7	2
valid_sources[0x50]	12752	1			T4	230		T7	1		T11	228
valid_sources[0x51]	12095	1			T4	118		T7	1		T11	233
valid_sources[0x52]	11606	1			T4	650		T7	2		T11	242
valid_sources[0x53]	12424	1			T4	646		T7	1		T11	262
valid_sources[0x54]	13041	1			T4	624		T11	236		T12	223
valid_sources[0x55]	11436	1			T1	1		T11	239		T12	231
valid_sources[0x56]	13461	1			T4	112		T7	1		T11	246
valid_sources[0x57]	11929	1			T7	1		T11	263		T12	261
valid_sources[0x58]	11262	1			T11	274		T12	223		T18	658
valid_sources[0x59]	12067	1			T4	16		T11	268		T16	4
valid_sources[0x5a]	11490	1			T4	14		T7	2		T11	286
valid_sources[0x5b]	10819	1			T11	261		T12	252		T18	677
valid_sources[0x5c]	11039	1			T11	222		T12	224		T18	663
valid_sources[0x5d]	12388	1			T4	245		T11	256		T16	7
valid_sources[0x5e]	11335	1			T4	59		T7	1		T11	258
valid_sources[0x5f]	11861	1			T7	2		T11	205		T16	2
valid_sources[0x60]	11644	1			T4	395		T7	1		T11	261
valid_sources[0x61]	10567	1			T4	37		T11	234		T12	231
valid_sources[0x62]	10875	1			T4	564		T7	1		T11	236
valid_sources[0x63]	10872	1			T1	1		T4	77		T11	251
valid_sources[0x64]	11831	1			T4	94		T11	251		T12	234
valid_sources[0x65]	11303	1			T4	112		T11	266		T12	235
valid_sources[0x66]	11542	1			T1	1		T4	9		T11	260
valid_sources[0x67]	12005	1			T4	436		T11	245		T16	1
valid_sources[0x68]	13077	1			T4	472		T11	235		T12	227
valid_sources[0x69]	11539	1			T4	84		T11	291		T12	247
valid_sources[0x6a]	11965	1			T11	254		T16	2		T12	219
valid_sources[0x6b]	11589	1			T1	1		T4	164		T11	221
valid_sources[0x6c]	11809	1			T4	27		T11	242		T16	2
valid_sources[0x6d]	12920	1			T4	635		T7	1		T11	246
valid_sources[0x6e]	11893	1			T4	242		T11	256		T16	3
valid_sources[0x6f]	12228	1			T10	37		T11	237		T12	251
valid_sources[0x70]	11877	1			T4	729		T11	288		T16	2
valid_sources[0x71]	11563	1			T5	13		T7	2		T11	325
valid_sources[0x72]	12254	1			T4	605		T7	2		T11	214
valid_sources[0x73]	11797	1			T4	23		T11	257		T16	8
valid_sources[0x74]	11652	1			T4	205		T11	276		T12	245
valid_sources[0x75]	13820	1			T4	253		T11	259		T12	221
valid_sources[0x76]	12367	1			T4	55		T5	10		T11	238
valid_sources[0x77]	13866	1			T4	595		T11	246		T12	226
valid_sources[0x78]	12017	1			T4	281		T11	278		T12	228
valid_sources[0x79]	12384	1			T4	370		T7	2		T11	231
valid_sources[0x7a]	11031	1			T11	250		T12	211		T18	608
valid_sources[0x7b]	11535	1			T1	1		T4	514		T11	248
valid_sources[0x7c]	12058	1			T4	459		T7	1		T10	22
valid_sources[0x7d]	11952	1			T4	361		T11	267		T16	3
valid_sources[0x7e]	12232	1			T11	219		T12	265		T18	650
valid_sources[0x7f]	13397	1			T4	485		T11	269		T12	248
valid_sources[0x80]	12186	1			T4	418		T11	287		T12	233

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

743454

1

T1

12

T4

15365

T5

11

values[0x0]

all_enables

biggest_size

1113146

1

T4

22930

T11

23208

T12

22348

values[0x1]

all_enables

biggest_size

1113383

1

T4

22878

T11

23546

T12

22567

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	211597	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2280222

1

T1

12

T3

1

T4

44342

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	612002	1			T1	23		T2	1		T4	11946
values[0x0]	869906	1			T3	1		T4	16763		T8	5
values[0x1]	1009911	1			T3	1		T4	19947		T8	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	91005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2400814

1

T1

13

T2

1

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9172	1			T4	189		T11	145		T12	146
valid_sources[0x01]	9759	1			T4	181		T11	253		T12	195
valid_sources[0x02]	9674	1			T4	216		T11	205		T12	165
valid_sources[0x03]	8879	1			T4	208		T11	262		T12	172
valid_sources[0x04]	9456	1			T4	187		T25	1		T11	198
valid_sources[0x05]	10072	1			T4	182		T11	204		T12	200
valid_sources[0x06]	10648	1			T4	214		T11	183		T12	178
valid_sources[0x07]	9382	1			T4	188		T23	1		T11	196
valid_sources[0x08]	9348	1			T4	189		T11	288		T12	205
valid_sources[0x09]	10469	1			T4	168		T11	205		T12	215
valid_sources[0x0a]	9512	1			T4	207		T11	213		T12	175
valid_sources[0x0b]	9519	1			T4	188		T11	222		T12	205
valid_sources[0x0c]	11128	1			T4	159		T11	238		T12	166
valid_sources[0x0d]	9623	1			T4	166		T11	236		T12	221
valid_sources[0x0e]	9855	1			T4	208		T11	165		T12	226
valid_sources[0x0f]	9866	1			T4	215		T11	201		T12	125
valid_sources[0x10]	9903	1			T4	192		T11	178		T12	186
valid_sources[0x11]	10339	1			T4	183		T11	201		T12	168
valid_sources[0x12]	9084	1			T4	216		T9	3		T11	183
valid_sources[0x13]	9371	1			T4	155		T11	181		T12	128
valid_sources[0x14]	9083	1			T4	194		T11	202		T12	186
valid_sources[0x15]	9536	1			T4	172		T11	184		T12	250
valid_sources[0x16]	8569	1			T4	167		T11	246		T12	163
valid_sources[0x17]	11445	1			T4	183		T11	158		T12	184
valid_sources[0x18]	9281	1			T4	199		T11	216		T56	1
valid_sources[0x19]	8924	1			T4	205		T11	214		T12	224
valid_sources[0x1a]	10257	1			T4	136		T11	314		T12	194
valid_sources[0x1b]	10001	1			T4	218		T11	159		T12	179
valid_sources[0x1c]	10004	1			T3	1		T4	218		T11	208
valid_sources[0x1d]	9309	1			T4	176		T11	195		T53	1
valid_sources[0x1e]	10156	1			T4	197		T11	185		T12	168
valid_sources[0x1f]	9259	1			T4	179		T11	238		T53	1
valid_sources[0x20]	10177	1			T4	178		T11	172		T12	192
valid_sources[0x21]	10349	1			T1	2		T4	188		T11	182
valid_sources[0x22]	9038	1			T4	178		T11	221		T12	190
valid_sources[0x23]	10051	1			T1	4		T4	161		T11	210
valid_sources[0x24]	9566	1			T4	185		T11	214		T12	188
valid_sources[0x25]	10207	1			T4	185		T11	260		T12	223
valid_sources[0x26]	10003	1			T4	203		T11	176		T12	186
valid_sources[0x27]	9345	1			T4	180		T11	205		T12	163
valid_sources[0x28]	9934	1			T4	201		T11	230		T12	158
valid_sources[0x29]	9242	1			T4	194		T11	248		T12	148
valid_sources[0x2a]	10514	1			T4	203		T11	207		T12	125
valid_sources[0x2b]	10274	1			T4	154		T11	245		T12	181
valid_sources[0x2c]	10685	1			T4	230		T11	214		T12	219
valid_sources[0x2d]	9930	1			T4	213		T11	231		T12	148
valid_sources[0x2e]	10975	1			T4	180		T11	257		T12	247
valid_sources[0x2f]	9061	1			T4	151		T11	171		T12	193
valid_sources[0x30]	9218	1			T4	217		T11	183		T12	137
valid_sources[0x31]	9437	1			T4	196		T11	202		T12	198
valid_sources[0x32]	9848	1			T4	165		T11	221		T12	185
valid_sources[0x33]	11184	1			T1	1		T4	215		T11	192
valid_sources[0x34]	9965	1			T4	196		T11	264		T53	1
valid_sources[0x35]	9156	1			T4	191		T11	201		T12	249
valid_sources[0x36]	10008	1			T4	212		T11	226		T12	216
valid_sources[0x37]	9423	1			T4	206		T11	204		T12	168
valid_sources[0x38]	9887	1			T4	221		T11	232		T12	182
valid_sources[0x39]	10269	1			T4	176		T11	175		T12	135
valid_sources[0x3a]	9555	1			T4	201		T8	1		T11	222
valid_sources[0x3b]	9465	1			T4	227		T11	221		T12	163
valid_sources[0x3c]	10746	1			T4	187		T11	175		T12	194
valid_sources[0x3d]	11796	1			T4	211		T11	191		T12	136
valid_sources[0x3e]	9749	1			T4	169		T9	3		T11	194
valid_sources[0x3f]	9066	1			T4	214		T11	175		T12	208
valid_sources[0x40]	8654	1			T4	234		T11	260		T12	139
valid_sources[0x41]	9916	1			T4	164		T11	205		T12	173
valid_sources[0x42]	9816	1			T4	165		T11	197		T12	177
valid_sources[0x43]	10339	1			T4	250		T11	207		T12	179
valid_sources[0x44]	9908	1			T4	224		T11	218		T12	114
valid_sources[0x45]	9659	1			T4	191		T11	232		T12	179
valid_sources[0x46]	9797	1			T4	224		T11	183		T53	1
valid_sources[0x47]	8923	1			T4	193		T11	141		T12	201
valid_sources[0x48]	9961	1			T4	161		T11	191		T12	212
valid_sources[0x49]	10091	1			T4	171		T11	228		T12	222
valid_sources[0x4a]	9835	1			T4	226		T11	167		T12	258
valid_sources[0x4b]	9444	1			T4	151		T11	233		T12	177
valid_sources[0x4c]	9442	1			T4	177		T11	260		T53	2
valid_sources[0x4d]	8913	1			T4	175		T11	147		T12	180
valid_sources[0x4e]	9288	1			T4	200		T11	167		T12	159
valid_sources[0x4f]	10245	1			T4	205		T11	259		T12	128
valid_sources[0x50]	9859	1			T4	215		T11	175		T12	149
valid_sources[0x51]	10142	1			T4	182		T11	218		T12	229
valid_sources[0x52]	9781	1			T4	193		T11	196		T12	185
valid_sources[0x53]	9735	1			T4	170		T11	210		T12	213
valid_sources[0x54]	9923	1			T4	186		T11	210		T12	222
valid_sources[0x55]	9028	1			T4	234		T11	200		T12	163
valid_sources[0x56]	9493	1			T4	190		T11	225		T12	194
valid_sources[0x57]	9711	1			T4	202		T8	3		T11	238
valid_sources[0x58]	10014	1			T4	190		T24	18		T11	192
valid_sources[0x59]	9251	1			T4	244		T11	192		T12	174
valid_sources[0x5a]	9361	1			T4	182		T11	247		T12	227
valid_sources[0x5b]	9084	1			T4	183		T11	231		T12	173
valid_sources[0x5c]	9252	1			T1	2		T4	146		T11	256
valid_sources[0x5d]	9842	1			T4	203		T11	176		T56	1
valid_sources[0x5e]	9174	1			T4	194		T11	209		T12	177
valid_sources[0x5f]	9305	1			T4	169		T11	210		T12	140
valid_sources[0x60]	10343	1			T4	194		T11	200		T12	191
valid_sources[0x61]	9400	1			T4	186		T11	205		T12	183
valid_sources[0x62]	9208	1			T4	218		T11	171		T12	234
valid_sources[0x63]	9348	1			T4	162		T11	237		T56	1
valid_sources[0x64]	10066	1			T4	196		T11	250		T53	3
valid_sources[0x65]	9247	1			T4	152		T11	169		T12	234
valid_sources[0x66]	9715	1			T4	210		T11	212		T12	165
valid_sources[0x67]	10734	1			T4	185		T11	260		T12	145
valid_sources[0x68]	10088	1			T4	216		T11	178		T12	105
valid_sources[0x69]	9561	1			T4	196		T11	207		T12	217
valid_sources[0x6a]	9535	1			T4	166		T11	213		T12	211
valid_sources[0x6b]	9020	1			T4	170		T11	224		T12	179
valid_sources[0x6c]	9809	1			T4	159		T11	210		T12	178
valid_sources[0x6d]	10297	1			T4	224		T11	214		T12	206
valid_sources[0x6e]	9945	1			T4	196		T11	171		T12	217
valid_sources[0x6f]	9065	1			T4	198		T11	218		T12	134
valid_sources[0x70]	10689	1			T4	219		T11	145		T12	178
valid_sources[0x71]	10485	1			T4	156		T11	177		T12	220
valid_sources[0x72]	9385	1			T4	154		T11	161		T12	144
valid_sources[0x73]	9524	1			T3	1		T4	160		T11	204
valid_sources[0x74]	7820	1			T4	162		T11	168		T12	158
valid_sources[0x75]	9816	1			T4	156		T11	143		T12	161
valid_sources[0x76]	9531	1			T4	219		T11	229		T12	204
valid_sources[0x77]	8780	1			T1	1		T4	188		T11	224
valid_sources[0x78]	9147	1			T4	164		T11	224		T12	185
valid_sources[0x79]	9316	1			T4	194		T11	160		T12	199
valid_sources[0x7a]	9255	1			T4	168		T11	251		T12	217
valid_sources[0x7b]	8837	1			T4	158		T11	207		T12	212
valid_sources[0x7c]	10099	1			T4	171		T11	187		T12	172
valid_sources[0x7d]	9467	1			T4	246		T11	246		T12	171
valid_sources[0x7e]	9550	1			T4	187		T11	249		T12	202
valid_sources[0x7f]	9254	1			T4	164		T11	232		T12	203
valid_sources[0x80]	9735	1			T4	197		T8	1		T11	311

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

572833

1

T1

12

T4

11211

T10

27

values[0x0]

all_enables

biggest_size

852622

1

T3

1

T4

16414

T8

1

values[0x1]

all_enables

biggest_size

854767

1

T4

16717

T8

1

T9

2