Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5480577

1

T4

118120

T5

118

T7

90

full_word

3474841

1

T1

8

T4

72101

T5

11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8955128	1			T1	8		T4	190221		T5	129
auto[TlIntgErrCmd]	108	1			T50	2		T51	8		T52	4
auto[TlIntgErrData]	89	1			T50	4		T51	3		T52	5
auto[TlIntgErrBoth]	93	1			T50	4		T51	9		T52	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1382695

1

T1

8

T4

29251

T5

129

auto[1]

7572723

1

T4

160970

T11

163630

T12

145897

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	565675	1			T4	12294		T5	118		T7	90
auto[TlIntgErrNone]	partial	auto[1]	4914637	1			T4	105826		T11	107339		T12	92956
auto[TlIntgErrNone]	full_word	auto[0]	816890	1			T1	8		T4	16957		T5	11
auto[TlIntgErrNone]	full_word	auto[1]	2657926	1			T4	55144		T11	56291		T12	52941
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T50	2		T51	4		T100	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T51	4		T52	4		T100	7
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T107	1		T109	1		T110	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T102	1		T104	1		T108	3
auto[TlIntgErrData]	partial	auto[0]	46	1			T51	1		T52	2		T100	3
auto[TlIntgErrData]	partial	auto[1]	31	1			T50	4		T51	1		T52	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T52	1		T103	1		T104	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T51	1		T100	1		T101	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T50	2		T51	4		T52	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T50	2		T51	5		T100	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T104	1		T110	1		T111	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T110	1		-	-		-	-