Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3070721

1

T1

43

T5

31

T8

96

full_word

1967984

1

T1

7

T4

4

T5

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5038385	1			T1	50		T4	4		T5	35
auto[TlIntgErrCmd]	130	1			T58	7		T59	3		T60	2
auto[TlIntgErrData]	90	1			T58	7		T59	5		T60	1
auto[TlIntgErrBoth]	100	1			T58	6		T59	2		T60	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

789323

1

T1

50

T4

4

T5

35

auto[1]

4249382

1

T13

123591

T14

457501

T15

287077

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	323409	1			T1	43		T5	31		T8	96
auto[TlIntgErrNone]	partial	auto[1]	2747016	1			T13	79185		T14	296739		T15	185435
auto[TlIntgErrNone]	full_word	auto[0]	465772	1			T1	7		T4	4		T5	4
auto[TlIntgErrNone]	full_word	auto[1]	1502188	1			T13	44406		T14	160762		T15	101642
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T58	1		T59	1		T60	1
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T58	5		T59	1		T60	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T58	1		T125	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T59	1		T126	1		T125	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T58	3		T59	4		T117	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T58	3		T60	1		T117	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T59	1		T118	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T58	1		T120	1		T124	2
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T58	4		T60	4		T117	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T58	2		T59	2		T60	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T117	1		T118	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T60	1		T123	1		T128	1