Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52245	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1367754

1

T2

3

T5

2

T6

35422

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	367443	1			T2	3		T5	28		T6	9258
values[0x0]	516694	1			T6	13429		T11	40787		T12	44535
values[0x1]	535862	1			T6	13875		T11	42360		T12	45891

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27436	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1392563

1

T2

3

T5

14

T6

35941

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5814	1			T6	173		T9	2		T15	1
valid_sources[0x01]	6217	1			T6	122		T11	409		T12	454
valid_sources[0x02]	5898	1			T6	156		T9	1		T10	18
valid_sources[0x03]	7294	1			T6	150		T15	2		T11	461
valid_sources[0x04]	4956	1			T6	152		T11	436		T12	423
valid_sources[0x05]	5742	1			T6	152		T11	471		T12	465
valid_sources[0x06]	5644	1			T6	143		T15	3		T11	439
valid_sources[0x07]	5314	1			T6	129		T9	1		T11	469
valid_sources[0x08]	6321	1			T6	147		T11	414		T12	524
valid_sources[0x09]	5382	1			T6	127		T15	1		T11	434
valid_sources[0x0a]	6092	1			T5	1		T6	148		T11	437
valid_sources[0x0b]	6787	1			T6	135		T11	425		T12	456
valid_sources[0x0c]	5345	1			T6	125		T9	1		T11	422
valid_sources[0x0d]	5451	1			T6	141		T15	1		T11	444
valid_sources[0x0e]	5587	1			T6	136		T15	1		T11	456
valid_sources[0x0f]	5789	1			T6	150		T15	1		T11	466
valid_sources[0x10]	5507	1			T6	151		T11	427		T12	462
valid_sources[0x11]	5730	1			T6	145		T15	2		T11	405
valid_sources[0x12]	4872	1			T6	149		T11	453		T12	507
valid_sources[0x13]	5022	1			T6	131		T11	455		T12	543
valid_sources[0x14]	4728	1			T6	142		T15	1		T11	461
valid_sources[0x15]	5471	1			T6	121		T9	2		T11	411
valid_sources[0x16]	5997	1			T6	155		T9	1		T11	444
valid_sources[0x17]	5198	1			T6	147		T11	450		T12	474
valid_sources[0x18]	5338	1			T6	139		T11	440		T12	466
valid_sources[0x19]	6632	1			T6	125		T9	1		T15	3
valid_sources[0x1a]	4872	1			T6	129		T11	407		T12	427
valid_sources[0x1b]	5558	1			T6	145		T15	1		T11	422
valid_sources[0x1c]	4592	1			T6	130		T15	1		T11	444
valid_sources[0x1d]	5298	1			T6	106		T9	1		T11	449
valid_sources[0x1e]	4926	1			T5	1		T6	128		T15	1
valid_sources[0x1f]	4907	1			T6	133		T11	425		T12	444
valid_sources[0x20]	4701	1			T6	136		T11	417		T12	438
valid_sources[0x21]	5546	1			T6	167		T11	457		T12	464
valid_sources[0x22]	4813	1			T6	140		T11	441		T12	473
valid_sources[0x23]	5099	1			T6	129		T11	408		T12	509
valid_sources[0x24]	5803	1			T6	143		T11	436		T12	455
valid_sources[0x25]	5827	1			T6	140		T10	23		T15	1
valid_sources[0x26]	6288	1			T6	140		T9	1		T11	421
valid_sources[0x27]	5627	1			T6	173		T11	396		T12	396
valid_sources[0x28]	5290	1			T6	141		T11	451		T12	411
valid_sources[0x29]	5577	1			T6	171		T11	438		T12	424
valid_sources[0x2a]	5587	1			T5	1		T6	157		T15	1
valid_sources[0x2b]	4832	1			T6	142		T11	426		T12	508
valid_sources[0x2c]	4696	1			T6	159		T9	1		T11	439
valid_sources[0x2d]	5532	1			T6	141		T11	434		T12	446
valid_sources[0x2e]	6029	1			T6	145		T11	444		T12	479
valid_sources[0x2f]	4791	1			T6	135		T9	2		T15	1
valid_sources[0x30]	7417	1			T5	1		T6	166		T9	1
valid_sources[0x31]	4982	1			T6	161		T9	2		T15	1
valid_sources[0x32]	6211	1			T6	134		T15	3		T11	418
valid_sources[0x33]	5707	1			T6	135		T15	2		T11	441
valid_sources[0x34]	4513	1			T6	128		T9	2		T11	452
valid_sources[0x35]	5868	1			T6	126		T11	455		T12	470
valid_sources[0x36]	4948	1			T6	135		T9	1		T11	421
valid_sources[0x37]	5503	1			T6	128		T9	1		T15	2
valid_sources[0x38]	4644	1			T6	127		T15	2		T11	455
valid_sources[0x39]	5229	1			T6	147		T9	1		T11	404
valid_sources[0x3a]	6587	1			T6	148		T11	458		T12	489
valid_sources[0x3b]	4376	1			T6	128		T11	411		T12	442
valid_sources[0x3c]	5033	1			T6	155		T11	425		T12	439
valid_sources[0x3d]	5280	1			T2	1		T6	153		T11	421
valid_sources[0x3e]	5301	1			T6	136		T11	487		T12	521
valid_sources[0x3f]	5766	1			T6	116		T11	445		T12	467
valid_sources[0x40]	5824	1			T6	134		T9	1		T15	2
valid_sources[0x41]	5781	1			T6	171		T9	1		T11	415
valid_sources[0x42]	4964	1			T6	119		T11	436		T12	382
valid_sources[0x43]	5773	1			T6	146		T9	2		T11	438
valid_sources[0x44]	6128	1			T6	136		T11	422		T12	433
valid_sources[0x45]	4901	1			T6	175		T15	2		T11	417
valid_sources[0x46]	5196	1			T5	1		T6	125		T15	2
valid_sources[0x47]	4741	1			T6	133		T9	2		T11	424
valid_sources[0x48]	5602	1			T6	152		T11	441		T12	478
valid_sources[0x49]	4915	1			T6	139		T15	1		T11	422
valid_sources[0x4a]	5240	1			T6	144		T11	478		T12	467
valid_sources[0x4b]	5009	1			T6	135		T11	425		T12	448
valid_sources[0x4c]	5907	1			T6	122		T15	2		T11	401
valid_sources[0x4d]	6117	1			T6	171		T11	439		T12	501
valid_sources[0x4e]	5644	1			T6	165		T15	1		T11	460
valid_sources[0x4f]	6404	1			T6	148		T15	6		T11	398
valid_sources[0x50]	5740	1			T6	125		T15	1		T11	397
valid_sources[0x51]	4991	1			T6	145		T9	1		T15	1
valid_sources[0x52]	4934	1			T6	153		T11	420		T12	525
valid_sources[0x53]	5222	1			T6	152		T9	1		T15	1
valid_sources[0x54]	4991	1			T6	153		T9	1		T11	425
valid_sources[0x55]	6688	1			T6	145		T9	1		T15	2
valid_sources[0x56]	5091	1			T6	145		T11	417		T12	434
valid_sources[0x57]	5893	1			T6	126		T9	1		T11	414
valid_sources[0x58]	5923	1			T5	1		T6	147		T15	1
valid_sources[0x59]	6899	1			T6	166		T15	4		T11	434
valid_sources[0x5a]	5428	1			T5	1		T6	155		T15	1
valid_sources[0x5b]	4622	1			T6	138		T11	427		T12	470
valid_sources[0x5c]	5271	1			T6	145		T9	1		T11	427
valid_sources[0x5d]	5919	1			T6	170		T15	3		T11	411
valid_sources[0x5e]	5486	1			T6	135		T15	1		T11	417
valid_sources[0x5f]	6183	1			T6	136		T15	2		T11	463
valid_sources[0x60]	5628	1			T6	153		T15	2		T11	440
valid_sources[0x61]	5478	1			T6	141		T11	424		T12	471
valid_sources[0x62]	5477	1			T6	161		T11	410		T12	431
valid_sources[0x63]	5385	1			T2	1		T6	193		T15	2
valid_sources[0x64]	6282	1			T6	133		T11	438		T12	429
valid_sources[0x65]	5315	1			T5	1		T6	132		T11	415
valid_sources[0x66]	6731	1			T6	119		T11	429		T12	399
valid_sources[0x67]	4987	1			T6	168		T11	403		T12	464
valid_sources[0x68]	4796	1			T6	131		T15	1		T11	486
valid_sources[0x69]	4787	1			T6	131		T15	1		T11	450
valid_sources[0x6a]	5112	1			T6	145		T9	1		T15	2
valid_sources[0x6b]	5675	1			T6	154		T11	421		T12	454
valid_sources[0x6c]	6716	1			T6	153		T15	3		T11	416
valid_sources[0x6d]	6175	1			T6	127		T9	1		T11	445
valid_sources[0x6e]	5215	1			T6	152		T9	1		T15	1
valid_sources[0x6f]	5768	1			T5	1		T6	125		T9	2
valid_sources[0x70]	6645	1			T6	158		T11	445		T12	485
valid_sources[0x71]	6018	1			T6	102		T9	1		T15	2
valid_sources[0x72]	5189	1			T6	146		T15	4		T11	403
valid_sources[0x73]	5520	1			T5	1		T6	117		T11	428
valid_sources[0x74]	5657	1			T6	138		T11	391		T12	490
valid_sources[0x75]	5685	1			T6	147		T15	3		T11	409
valid_sources[0x76]	5133	1			T6	143		T11	424		T12	556
valid_sources[0x77]	5955	1			T6	129		T9	1		T15	1
valid_sources[0x78]	5899	1			T6	127		T11	421		T12	515
valid_sources[0x79]	5051	1			T5	2		T6	153		T15	1
valid_sources[0x7a]	5215	1			T6	118		T15	1		T11	430
valid_sources[0x7b]	6202	1			T6	155		T11	423		T12	477
valid_sources[0x7c]	4930	1			T6	143		T11	450		T12	539
valid_sources[0x7d]	5367	1			T6	149		T15	1		T11	424
valid_sources[0x7e]	5075	1			T6	121		T11	427		T12	469
valid_sources[0x7f]	4817	1			T6	159		T9	1		T11	457
valid_sources[0x80]	5782	1			T6	128		T11	406		T12	477

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

343473

1

T2

3

T5

2

T6

8919

values[0x0]

all_enables

biggest_size

512064

1

T6

13305

T11

40417

T12

44160

values[0x1]

all_enables

biggest_size

512217

1

T6

13198

T11

40507

T12

43982

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	102107	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1063195

1

T2

13

T3

3

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	288819	1			T1	1		T2	21		T4	1
values[0x0]	406824	1			T3	4		T6	11102		T8	7
values[0x1]	469659	1			T3	9		T6	12972		T8	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45361	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1119941

1

T2

13

T3

3

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4375	1			T6	184		T11	328		T12	479
valid_sources[0x01]	4844	1			T6	117		T11	341		T12	458
valid_sources[0x02]	5216	1			T6	89		T11	408		T12	436
valid_sources[0x03]	4091	1			T6	144		T11	345		T12	82
valid_sources[0x04]	4490	1			T6	97		T11	396		T12	151
valid_sources[0x05]	4447	1			T6	191		T11	333		T12	224
valid_sources[0x06]	3838	1			T6	91		T11	388		T12	262
valid_sources[0x07]	4257	1			T6	110		T11	351		T12	38
valid_sources[0x08]	5544	1			T6	69		T11	304		T12	534
valid_sources[0x09]	3658	1			T6	131		T11	417		T12	55
valid_sources[0x0a]	4694	1			T6	70		T11	333		T12	709
valid_sources[0x0b]	3846	1			T6	55		T11	335		T12	348
valid_sources[0x0c]	3664	1			T6	76		T11	335		T12	267
valid_sources[0x0d]	4811	1			T6	203		T11	328		T12	342
valid_sources[0x0e]	4324	1			T6	135		T11	277		T12	52
valid_sources[0x0f]	3933	1			T6	168		T11	363		T12	345
valid_sources[0x10]	4295	1			T6	106		T11	367		T12	378
valid_sources[0x11]	4820	1			T6	196		T11	248		T12	826
valid_sources[0x12]	4223	1			T6	156		T11	337		T12	441
valid_sources[0x13]	4265	1			T6	131		T11	362		T12	82
valid_sources[0x14]	5090	1			T6	186		T11	325		T12	687
valid_sources[0x15]	5436	1			T6	118		T11	358		T12	206
valid_sources[0x16]	4848	1			T6	93		T11	375		T12	208
valid_sources[0x17]	4580	1			T2	3		T6	110		T11	298
valid_sources[0x18]	5277	1			T6	104		T11	362		T12	342
valid_sources[0x19]	4804	1			T6	123		T11	291		T12	605
valid_sources[0x1a]	4638	1			T6	57		T11	350		T12	359
valid_sources[0x1b]	4839	1			T6	161		T11	370		T12	742
valid_sources[0x1c]	4567	1			T6	189		T11	336		T12	105
valid_sources[0x1d]	3861	1			T6	95		T11	281		T12	70
valid_sources[0x1e]	4308	1			T6	168		T11	347		T12	116
valid_sources[0x1f]	5260	1			T6	173		T11	408		T12	1022
valid_sources[0x20]	4879	1			T6	159		T11	368		T12	580
valid_sources[0x21]	3971	1			T6	157		T11	349		T12	31
valid_sources[0x22]	4342	1			T6	229		T11	333		T12	276
valid_sources[0x23]	4370	1			T6	93		T11	313		T12	223
valid_sources[0x24]	4703	1			T6	150		T11	302		T12	359
valid_sources[0x25]	4352	1			T6	204		T11	354		T12	508
valid_sources[0x26]	4253	1			T6	164		T11	343		T12	191
valid_sources[0x27]	4114	1			T6	61		T11	361		T12	266
valid_sources[0x28]	4901	1			T6	155		T11	340		T12	370
valid_sources[0x29]	4981	1			T6	80		T11	379		T12	100
valid_sources[0x2a]	5126	1			T6	158		T11	360		T12	296
valid_sources[0x2b]	4636	1			T6	121		T11	347		T12	843
valid_sources[0x2c]	4600	1			T6	75		T11	329		T12	387
valid_sources[0x2d]	4914	1			T6	158		T11	370		T12	782
valid_sources[0x2e]	4287	1			T2	1		T6	140		T11	378
valid_sources[0x2f]	4757	1			T6	32		T11	376		T12	756
valid_sources[0x30]	4758	1			T6	152		T11	357		T12	337
valid_sources[0x31]	4439	1			T6	192		T11	291		T12	545
valid_sources[0x32]	4947	1			T2	1		T6	118		T11	338
valid_sources[0x33]	4889	1			T6	262		T11	293		T12	200
valid_sources[0x34]	3965	1			T6	180		T11	346		T12	223
valid_sources[0x35]	4744	1			T6	94		T11	361		T12	180
valid_sources[0x36]	4174	1			T6	194		T11	358		T12	289
valid_sources[0x37]	4744	1			T6	95		T11	336		T12	343
valid_sources[0x38]	3966	1			T2	5		T6	137		T11	325
valid_sources[0x39]	4425	1			T6	173		T11	321		T12	93
valid_sources[0x3a]	3999	1			T6	97		T11	378		T12	254
valid_sources[0x3b]	4659	1			T6	95		T11	337		T12	685
valid_sources[0x3c]	4263	1			T6	135		T11	319		T12	23
valid_sources[0x3d]	3964	1			T6	115		T11	354		T12	518
valid_sources[0x3e]	4156	1			T6	47		T11	347		T12	178
valid_sources[0x3f]	4578	1			T6	77		T11	389		T12	155
valid_sources[0x40]	4413	1			T6	148		T11	338		T12	528
valid_sources[0x41]	4178	1			T6	137		T11	346		T12	841
valid_sources[0x42]	4324	1			T6	61		T11	298		T12	783
valid_sources[0x43]	4387	1			T6	91		T11	327		T12	221
valid_sources[0x44]	4140	1			T6	139		T11	303		T12	230
valid_sources[0x45]	5159	1			T6	135		T11	335		T12	454
valid_sources[0x46]	3459	1			T6	132		T11	361		T12	397
valid_sources[0x47]	4606	1			T6	150		T11	364		T12	640
valid_sources[0x48]	5160	1			T2	3		T6	196		T11	334
valid_sources[0x49]	4144	1			T6	113		T11	397		T12	194
valid_sources[0x4a]	3758	1			T6	135		T11	352		T12	316
valid_sources[0x4b]	4574	1			T6	85		T11	387		T12	250
valid_sources[0x4c]	4616	1			T6	177		T11	311		T12	439
valid_sources[0x4d]	4609	1			T6	72		T11	314		T12	558
valid_sources[0x4e]	4657	1			T6	178		T11	328		T12	67
valid_sources[0x4f]	4138	1			T6	75		T11	303		T12	822
valid_sources[0x50]	5183	1			T6	174		T11	330		T12	613
valid_sources[0x51]	3941	1			T6	121		T11	380		T12	328
valid_sources[0x52]	4244	1			T6	70		T11	294		T12	511
valid_sources[0x53]	4320	1			T6	200		T11	293		T12	449
valid_sources[0x54]	5072	1			T6	155		T11	342		T12	496
valid_sources[0x55]	4783	1			T6	136		T11	308		T12	601
valid_sources[0x56]	4596	1			T6	76		T11	343		T12	116
valid_sources[0x57]	4970	1			T2	1		T6	133		T11	341
valid_sources[0x58]	4455	1			T6	129		T11	274		T12	389
valid_sources[0x59]	4118	1			T6	30		T11	372		T12	559
valid_sources[0x5a]	4530	1			T6	95		T11	314		T12	241
valid_sources[0x5b]	4684	1			T6	83		T7	1		T11	333
valid_sources[0x5c]	4182	1			T6	133		T11	318		T12	579
valid_sources[0x5d]	3703	1			T6	192		T11	315		T12	436
valid_sources[0x5e]	4426	1			T6	64		T11	333		T12	454
valid_sources[0x5f]	5155	1			T2	1		T6	107		T11	337
valid_sources[0x60]	4784	1			T6	108		T11	342		T12	436
valid_sources[0x61]	4900	1			T6	144		T11	351		T12	319
valid_sources[0x62]	4333	1			T6	96		T11	308		T40	1
valid_sources[0x63]	4587	1			T6	47		T11	319		T12	602
valid_sources[0x64]	4414	1			T6	161		T11	329		T12	531
valid_sources[0x65]	4850	1			T6	64		T11	317		T12	509
valid_sources[0x66]	4627	1			T6	171		T11	357		T12	141
valid_sources[0x67]	5492	1			T6	175		T11	407		T12	649
valid_sources[0x68]	4195	1			T6	183		T11	305		T12	424
valid_sources[0x69]	4230	1			T6	111		T11	315		T12	302
valid_sources[0x6a]	4229	1			T6	167		T11	317		T12	205
valid_sources[0x6b]	5331	1			T6	53		T11	387		T12	517
valid_sources[0x6c]	5074	1			T6	91		T11	347		T12	824
valid_sources[0x6d]	5698	1			T6	75		T11	363		T12	421
valid_sources[0x6e]	4476	1			T2	1		T6	119		T11	348
valid_sources[0x6f]	5383	1			T2	2		T6	104		T11	348
valid_sources[0x70]	4154	1			T6	139		T11	319		T12	189
valid_sources[0x71]	4114	1			T6	27		T11	351		T12	207
valid_sources[0x72]	4601	1			T6	88		T11	345		T12	422
valid_sources[0x73]	4916	1			T6	110		T11	387		T12	419
valid_sources[0x74]	3940	1			T6	96		T11	331		T12	454
valid_sources[0x75]	3764	1			T6	104		T11	296		T12	26
valid_sources[0x76]	3596	1			T6	67		T11	331		T12	343
valid_sources[0x77]	4434	1			T6	170		T11	333		T12	105
valid_sources[0x78]	4841	1			T6	165		T11	323		T12	336
valid_sources[0x79]	4337	1			T2	1		T6	77		T11	316
valid_sources[0x7a]	4349	1			T6	32		T11	373		T12	539
valid_sources[0x7b]	3748	1			T6	150		T11	344		T12	457
valid_sources[0x7c]	5706	1			T6	140		T11	310		T12	806
valid_sources[0x7d]	5111	1			T6	108		T11	360		T12	725
valid_sources[0x7e]	5122	1			T6	229		T11	293		T12	562
valid_sources[0x7f]	3924	1			T6	76		T11	363		T12	33
valid_sources[0x80]	4612	1			T6	149		T11	373		T12	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

267397

1

T2

13

T4

1

T5

10

values[0x0]

all_enables

biggest_size

398410

1

T3

3

T6

10883

T8

5

values[0x1]

all_enables

biggest_size

397388

1

T6

10878

T8

1

T11

29768