Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2545147

1

T5

26

T6

70801

T9

61

full_word

1600352

1

T2

2

T5

2

T6

41844

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4145219	1			T2	2		T5	28		T6	112645
auto[TlIntgErrCmd]	90	1			T48	9		T49	5		T50	3
auto[TlIntgErrData]	101	1			T48	6		T49	4		T50	5
auto[TlIntgErrBoth]	89	1			T48	5		T49	1		T50	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

652070

1

T2

2

T5

28

T6

16901

auto[1]

3493429

1

T6

95744

T11

276576

T12

300205

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	274543	1			T5	26		T6	7104		T9	61
auto[TlIntgErrNone]	partial	auto[1]	2270347	1			T6	63697		T11	179802		T12	194933
auto[TlIntgErrNone]	full_word	auto[0]	377404	1			T2	2		T5	2		T6	9797
auto[TlIntgErrNone]	full_word	auto[1]	1222925	1			T6	32047		T11	96774		T12	105272
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T48	3		T49	1		T106	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T48	6		T49	4		T50	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T107	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T50	1		T106	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T48	3		T49	4		T50	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T48	2		T50	3		T106	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T48	1		T110	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T116	1		T115	1		T117	2
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T48	1		T49	1		T50	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T48	3		T106	1		T114	7
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T114	1		T118	1		T112	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T48	1		T109	1		T107	1