Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66784	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2076171

1

T1

18

T3

26

T4

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	545159	1			T1	214		T3	340		T4	374
values[0x0]	785142	1			T13	71544		T14	48701		T15	19638
values[0x1]	812654	1			T13	73611		T14	50482		T15	20610

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36125	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2106830

1

T1

127

T3

184

T4

222

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7584	1			T3	1		T4	1		T16	2
valid_sources[0x01]	8174	1			T4	4		T11	2		T21	1
valid_sources[0x02]	7894	1			T3	2		T4	1		T11	1
valid_sources[0x03]	8175	1			T4	1		T11	2		T21	1
valid_sources[0x04]	8031	1			T17	1		T13	731		T14	469
valid_sources[0x05]	8506	1			T4	1		T5	2		T21	1
valid_sources[0x06]	8632	1			T3	1		T4	1		T21	2
valid_sources[0x07]	8674	1			T3	1		T4	2		T11	3
valid_sources[0x08]	7740	1			T3	5		T4	1		T21	2
valid_sources[0x09]	8289	1			T4	1		T21	2		T13	721
valid_sources[0x0a]	9141	1			T4	3		T21	1		T13	796
valid_sources[0x0b]	7890	1			T3	1		T4	1		T11	1
valid_sources[0x0c]	8514	1			T11	1		T13	750		T14	482
valid_sources[0x0d]	8029	1			T4	1		T5	1		T21	3
valid_sources[0x0e]	8583	1			T3	4		T4	1		T17	1
valid_sources[0x0f]	7967	1			T3	1		T13	715		T14	532
valid_sources[0x10]	8314	1			T3	2		T4	1		T5	7
valid_sources[0x11]	8386	1			T3	1		T11	1		T13	783
valid_sources[0x12]	8988	1			T3	2		T13	731		T14	555
valid_sources[0x13]	7890	1			T4	6		T21	2		T13	749
valid_sources[0x14]	7744	1			T1	30		T3	4		T4	3
valid_sources[0x15]	7702	1			T3	2		T4	1		T21	2
valid_sources[0x16]	7686	1			T3	5		T21	2		T13	806
valid_sources[0x17]	8567	1			T3	5		T4	3		T16	3
valid_sources[0x18]	8775	1			T3	1		T4	3		T11	2
valid_sources[0x19]	8222	1			T3	1		T4	1		T21	5
valid_sources[0x1a]	8211	1			T4	2		T16	4		T21	1
valid_sources[0x1b]	8895	1			T3	1		T11	3		T21	2
valid_sources[0x1c]	9834	1			T3	1		T4	2		T11	1
valid_sources[0x1d]	7881	1			T3	1		T4	1		T21	2
valid_sources[0x1e]	8052	1			T1	23		T3	2		T11	1
valid_sources[0x1f]	7603	1			T4	4		T11	2		T21	2
valid_sources[0x20]	7742	1			T21	2		T13	760		T14	551
valid_sources[0x21]	8178	1			T3	1		T11	1		T21	1
valid_sources[0x22]	9335	1			T4	1		T13	750		T14	490
valid_sources[0x23]	8015	1			T4	2		T11	5		T21	1
valid_sources[0x24]	8659	1			T4	1		T11	2		T13	794
valid_sources[0x25]	7838	1			T3	4		T21	1		T17	1
valid_sources[0x26]	8206	1			T3	2		T4	1		T21	1
valid_sources[0x27]	7975	1			T3	3		T21	1		T13	716
valid_sources[0x28]	8751	1			T11	2		T21	1		T13	732
valid_sources[0x29]	7963	1			T11	1		T13	700		T14	525
valid_sources[0x2a]	7859	1			T4	1		T21	2		T13	746
valid_sources[0x2b]	9495	1			T3	2		T4	5		T11	1
valid_sources[0x2c]	7767	1			T3	4		T11	1		T21	3
valid_sources[0x2d]	8178	1			T4	1		T21	3		T13	751
valid_sources[0x2e]	7948	1			T3	6		T11	2		T21	1
valid_sources[0x2f]	7920	1			T3	1		T4	1		T16	5
valid_sources[0x30]	7981	1			T3	1		T4	5		T21	1
valid_sources[0x31]	9510	1			T4	4		T21	2		T13	732
valid_sources[0x32]	7936	1			T11	1		T21	1		T17	1
valid_sources[0x33]	8589	1			T3	1		T4	1		T5	4
valid_sources[0x34]	8413	1			T16	6		T11	2		T13	713
valid_sources[0x35]	8308	1			T3	3		T4	2		T16	2
valid_sources[0x36]	8387	1			T3	1		T4	3		T21	2
valid_sources[0x37]	7918	1			T3	1		T4	1		T11	1
valid_sources[0x38]	7674	1			T3	2		T16	2		T11	1
valid_sources[0x39]	8322	1			T4	1		T21	2		T13	805
valid_sources[0x3a]	8255	1			T3	2		T4	2		T21	3
valid_sources[0x3b]	8703	1			T3	2		T4	3		T11	1
valid_sources[0x3c]	8581	1			T3	3		T4	1		T21	3
valid_sources[0x3d]	8127	1			T3	1		T11	3		T21	1
valid_sources[0x3e]	8996	1			T3	9		T4	4		T16	4
valid_sources[0x3f]	7769	1			T3	1		T4	1		T5	4
valid_sources[0x40]	8334	1			T4	3		T21	1		T17	2
valid_sources[0x41]	8118	1			T3	1		T4	1		T21	1
valid_sources[0x42]	8007	1			T3	2		T4	2		T11	1
valid_sources[0x43]	8966	1			T3	6		T4	1		T21	1
valid_sources[0x44]	8168	1			T4	6		T16	1		T21	1
valid_sources[0x45]	9688	1			T3	3		T21	1		T13	769
valid_sources[0x46]	7956	1			T3	5		T4	2		T5	1
valid_sources[0x47]	7866	1			T3	2		T4	4		T21	1
valid_sources[0x48]	7642	1			T17	2		T13	738		T14	542
valid_sources[0x49]	9054	1			T4	2		T11	2		T21	1
valid_sources[0x4a]	8499	1			T4	5		T21	3		T13	811
valid_sources[0x4b]	8054	1			T3	1		T4	2		T16	4
valid_sources[0x4c]	7780	1			T3	5		T13	788		T14	483
valid_sources[0x4d]	7892	1			T21	2		T13	723		T113	1
valid_sources[0x4e]	7581	1			T3	1		T4	1		T21	2
valid_sources[0x4f]	9373	1			T3	1		T4	2		T21	1
valid_sources[0x50]	8173	1			T3	1		T4	1		T13	737
valid_sources[0x51]	8311	1			T3	1		T11	1		T21	1
valid_sources[0x52]	8702	1			T3	4		T4	3		T11	1
valid_sources[0x53]	8266	1			T11	2		T13	749		T113	2
valid_sources[0x54]	7590	1			T3	2		T21	2		T13	745
valid_sources[0x55]	8602	1			T3	1		T4	2		T11	1
valid_sources[0x56]	8202	1			T3	2		T21	5		T17	2
valid_sources[0x57]	8173	1			T3	2		T21	1		T17	2
valid_sources[0x58]	9221	1			T4	1		T21	1		T13	753
valid_sources[0x59]	8564	1			T3	2		T4	1		T13	790
valid_sources[0x5a]	8200	1			T3	1		T4	1		T11	1
valid_sources[0x5b]	7635	1			T16	13		T21	1		T13	783
valid_sources[0x5c]	7866	1			T3	1		T4	3		T5	3
valid_sources[0x5d]	7694	1			T3	1		T5	2		T11	2
valid_sources[0x5e]	8675	1			T3	2		T11	1		T17	1
valid_sources[0x5f]	8013	1			T4	1		T13	754		T14	505
valid_sources[0x60]	7625	1			T3	4		T13	809		T14	524
valid_sources[0x61]	7777	1			T11	1		T21	2		T17	2
valid_sources[0x62]	8778	1			T11	1		T21	2		T13	793
valid_sources[0x63]	8308	1			T4	2		T11	1		T21	4
valid_sources[0x64]	9445	1			T3	2		T4	2		T11	1
valid_sources[0x65]	8101	1			T4	2		T5	4		T16	3
valid_sources[0x66]	10461	1			T3	3		T4	1		T13	779
valid_sources[0x67]	7910	1			T3	4		T4	1		T21	2
valid_sources[0x68]	8181	1			T4	1		T21	1		T13	751
valid_sources[0x69]	9151	1			T4	1		T21	2		T13	733
valid_sources[0x6a]	8065	1			T4	1		T13	727		T14	566
valid_sources[0x6b]	8246	1			T4	2		T17	1		T13	707
valid_sources[0x6c]	8523	1			T3	2		T4	7		T16	3
valid_sources[0x6d]	7839	1			T3	4		T4	2		T21	1
valid_sources[0x6e]	8817	1			T4	6		T21	2		T17	1
valid_sources[0x6f]	9761	1			T3	1		T4	13		T11	1
valid_sources[0x70]	7378	1			T3	3		T11	1		T21	1
valid_sources[0x71]	8068	1			T4	1		T11	1		T13	789
valid_sources[0x72]	7956	1			T4	3		T11	1		T21	3
valid_sources[0x73]	8344	1			T4	3		T16	4		T11	1
valid_sources[0x74]	8112	1			T4	1		T21	2		T13	760
valid_sources[0x75]	8822	1			T3	2		T4	1		T21	1
valid_sources[0x76]	7751	1			T3	1		T11	3		T21	2
valid_sources[0x77]	8859	1			T3	1		T11	1		T21	3
valid_sources[0x78]	7864	1			T3	1		T21	1		T13	745
valid_sources[0x79]	8226	1			T3	1		T4	2		T11	2
valid_sources[0x7a]	7813	1			T3	2		T5	8		T16	2
valid_sources[0x7b]	7934	1			T21	1		T13	800		T113	2
valid_sources[0x7c]	9555	1			T4	1		T21	1		T13	744
valid_sources[0x7d]	7887	1			T3	4		T4	1		T13	695
valid_sources[0x7e]	7938	1			T3	1		T21	2		T13	790
valid_sources[0x7f]	8613	1			T3	1		T11	1		T21	1
valid_sources[0x80]	7656	1			T3	4		T4	1		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

521614

1

T1

18

T3

26

T4

33

values[0x0]

all_enables

biggest_size

778135

1

T13

70951

T14

48244

T15

19451

values[0x1]

all_enables

biggest_size

776422

1

T13

70497

T14

48243

T15

19666

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151085	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1610452

1

T5

13

T6

1

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	432533	1			T2	1		T5	32		T7	1
values[0x0]	616112	1			T6	7		T9	1		T10	8
values[0x1]	712892	1			T6	6		T9	1		T10	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65976	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1695561

1

T5

18

T6

2

T7

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6512	1			T13	616		T14	407		T15	182
valid_sources[0x01]	6719	1			T5	1		T13	598		T14	393
valid_sources[0x02]	7052	1			T13	597		T14	418		T15	158
valid_sources[0x03]	6870	1			T12	1		T13	552		T14	424
valid_sources[0x04]	6613	1			T5	1		T13	578		T53	1
valid_sources[0x05]	6584	1			T13	582		T23	12		T14	378
valid_sources[0x06]	7649	1			T5	1		T29	2		T13	598
valid_sources[0x07]	6855	1			T13	566		T14	435		T15	152
valid_sources[0x08]	7680	1			T13	621		T14	395		T15	184
valid_sources[0x09]	7139	1			T5	1		T13	589		T14	402
valid_sources[0x0a]	7704	1			T13	572		T14	423		T15	189
valid_sources[0x0b]	6283	1			T5	3		T10	1		T13	619
valid_sources[0x0c]	6218	1			T13	550		T14	393		T15	136
valid_sources[0x0d]	6562	1			T13	584		T14	421		T15	169
valid_sources[0x0e]	6502	1			T13	655		T14	374		T15	169
valid_sources[0x0f]	7011	1			T13	625		T14	442		T15	187
valid_sources[0x10]	6896	1			T13	617		T14	419		T15	160
valid_sources[0x11]	6339	1			T17	1		T13	640		T14	393
valid_sources[0x12]	6259	1			T13	608		T14	391		T15	169
valid_sources[0x13]	7319	1			T13	568		T14	403		T15	172
valid_sources[0x14]	6512	1			T13	615		T14	420		T15	157
valid_sources[0x15]	6664	1			T13	629		T14	368		T15	158
valid_sources[0x16]	7119	1			T5	1		T13	594		T14	403
valid_sources[0x17]	6544	1			T13	567		T14	381		T15	178
valid_sources[0x18]	6856	1			T13	562		T14	389		T15	172
valid_sources[0x19]	5933	1			T13	563		T53	1		T14	460
valid_sources[0x1a]	7033	1			T5	1		T13	569		T14	392
valid_sources[0x1b]	7275	1			T13	569		T14	375		T15	200
valid_sources[0x1c]	7650	1			T17	1		T13	637		T14	419
valid_sources[0x1d]	6448	1			T13	589		T52	4		T14	412
valid_sources[0x1e]	6259	1			T13	633		T14	397		T15	182
valid_sources[0x1f]	6406	1			T13	611		T14	415		T15	184
valid_sources[0x20]	6806	1			T13	649		T14	375		T15	193
valid_sources[0x21]	7294	1			T16	6		T13	586		T14	434
valid_sources[0x22]	7003	1			T5	1		T12	1		T13	596
valid_sources[0x23]	7231	1			T13	578		T14	405		T15	166
valid_sources[0x24]	7231	1			T13	581		T14	447		T15	151
valid_sources[0x25]	6435	1			T5	1		T13	590		T14	398
valid_sources[0x26]	6518	1			T17	2		T13	558		T14	412
valid_sources[0x27]	6881	1			T13	653		T14	407		T15	151
valid_sources[0x28]	6087	1			T13	612		T14	412		T15	154
valid_sources[0x29]	7380	1			T8	1		T16	3		T13	613
valid_sources[0x2a]	6782	1			T13	623		T14	405		T15	160
valid_sources[0x2b]	6583	1			T13	517		T14	440		T15	168
valid_sources[0x2c]	7267	1			T13	585		T14	407		T15	135
valid_sources[0x2d]	6920	1			T13	598		T14	393		T15	153
valid_sources[0x2e]	6968	1			T17	1		T13	613		T22	2
valid_sources[0x2f]	6931	1			T13	638		T14	419		T15	177
valid_sources[0x30]	7599	1			T29	1		T13	619		T14	411
valid_sources[0x31]	7320	1			T13	581		T14	368		T15	163
valid_sources[0x32]	6202	1			T13	579		T14	444		T15	185
valid_sources[0x33]	6414	1			T13	591		T14	370		T15	173
valid_sources[0x34]	7265	1			T13	581		T14	394		T15	171
valid_sources[0x35]	6778	1			T29	1		T13	547		T14	378
valid_sources[0x36]	7243	1			T13	642		T14	416		T15	156
valid_sources[0x37]	7244	1			T29	1		T13	621		T14	413
valid_sources[0x38]	6828	1			T13	567		T14	411		T15	190
valid_sources[0x39]	6296	1			T13	555		T14	386		T15	170
valid_sources[0x3a]	7787	1			T13	583		T14	364		T15	178
valid_sources[0x3b]	6962	1			T24	1		T17	3		T13	609
valid_sources[0x3c]	6926	1			T5	1		T13	596		T14	366
valid_sources[0x3d]	6710	1			T13	540		T14	392		T15	154
valid_sources[0x3e]	7336	1			T13	618		T14	391		T15	194
valid_sources[0x3f]	6679	1			T13	570		T14	363		T15	157
valid_sources[0x40]	7164	1			T13	612		T14	446		T15	172
valid_sources[0x41]	6620	1			T13	631		T14	400		T15	171
valid_sources[0x42]	7342	1			T13	585		T14	385		T15	178
valid_sources[0x43]	6319	1			T13	592		T14	417		T15	172
valid_sources[0x44]	6266	1			T13	592		T20	3		T14	414
valid_sources[0x45]	7146	1			T13	610		T14	400		T15	171
valid_sources[0x46]	7468	1			T16	1		T13	614		T14	444
valid_sources[0x47]	6256	1			T13	549		T14	421		T15	170
valid_sources[0x48]	6528	1			T13	608		T20	1		T14	446
valid_sources[0x49]	6864	1			T13	552		T14	427		T15	164
valid_sources[0x4a]	7193	1			T13	644		T14	398		T15	175
valid_sources[0x4b]	6443	1			T5	2		T13	545		T14	365
valid_sources[0x4c]	7047	1			T13	638		T14	441		T15	155
valid_sources[0x4d]	7308	1			T5	1		T13	594		T14	424
valid_sources[0x4e]	7199	1			T13	621		T14	381		T15	150
valid_sources[0x4f]	6653	1			T13	629		T14	385		T15	175
valid_sources[0x50]	7165	1			T13	620		T14	396		T15	177
valid_sources[0x51]	7116	1			T17	2		T13	576		T14	432
valid_sources[0x52]	6550	1			T13	572		T14	384		T15	166
valid_sources[0x53]	7149	1			T13	645		T14	395		T15	162
valid_sources[0x54]	7109	1			T24	1		T13	578		T14	450
valid_sources[0x55]	6207	1			T5	1		T13	584		T14	379
valid_sources[0x56]	6748	1			T10	2		T13	553		T14	372
valid_sources[0x57]	6923	1			T13	553		T14	415		T15	164
valid_sources[0x58]	7023	1			T13	620		T51	16		T14	386
valid_sources[0x59]	7773	1			T10	4		T13	623		T14	347
valid_sources[0x5a]	7151	1			T12	1		T13	553		T14	382
valid_sources[0x5b]	7160	1			T13	629		T14	422		T15	193
valid_sources[0x5c]	6279	1			T13	587		T52	1		T14	398
valid_sources[0x5d]	6781	1			T5	1		T13	580		T14	402
valid_sources[0x5e]	7838	1			T13	594		T14	389		T15	180
valid_sources[0x5f]	6828	1			T13	608		T14	389		T15	173
valid_sources[0x60]	7224	1			T13	644		T14	384		T15	149
valid_sources[0x61]	7269	1			T13	609		T22	1		T14	402
valid_sources[0x62]	5942	1			T13	556		T14	461		T15	133
valid_sources[0x63]	6521	1			T13	555		T14	410		T15	183
valid_sources[0x64]	7940	1			T16	9		T13	577		T14	403
valid_sources[0x65]	6802	1			T13	619		T14	432		T15	174
valid_sources[0x66]	6687	1			T13	591		T14	409		T15	145
valid_sources[0x67]	6769	1			T29	2		T13	597		T52	4
valid_sources[0x68]	6113	1			T13	638		T14	368		T15	172
valid_sources[0x69]	6951	1			T13	640		T22	2		T14	418
valid_sources[0x6a]	6842	1			T12	2		T13	645		T14	477
valid_sources[0x6b]	6718	1			T13	604		T14	413		T15	149
valid_sources[0x6c]	7295	1			T29	1		T13	621		T14	397
valid_sources[0x6d]	6767	1			T13	570		T14	469		T15	171
valid_sources[0x6e]	6196	1			T5	1		T13	539		T14	429
valid_sources[0x6f]	6508	1			T12	1		T13	587		T14	375
valid_sources[0x70]	6351	1			T13	600		T14	406		T15	191
valid_sources[0x71]	6780	1			T13	563		T14	378		T15	164
valid_sources[0x72]	6507	1			T13	593		T14	449		T15	170
valid_sources[0x73]	6790	1			T13	638		T20	14		T53	1
valid_sources[0x74]	7826	1			T13	593		T14	437		T15	168
valid_sources[0x75]	6579	1			T13	569		T14	377		T15	182
valid_sources[0x76]	7328	1			T13	620		T14	419		T15	147
valid_sources[0x77]	8277	1			T16	6		T13	622		T14	397
valid_sources[0x78]	6775	1			T16	1		T13	600		T14	361
valid_sources[0x79]	7182	1			T16	6		T13	583		T38	1
valid_sources[0x7a]	7099	1			T10	2		T13	650		T14	443
valid_sources[0x7b]	6941	1			T5	1		T13	554		T14	385
valid_sources[0x7c]	7669	1			T13	600		T14	420		T15	167
valid_sources[0x7d]	7199	1			T13	608		T14	397		T15	147
valid_sources[0x7e]	7277	1			T13	599		T14	403		T15	190
valid_sources[0x7f]	6456	1			T24	1		T13	580		T14	407
valid_sources[0x80]	6475	1			T13	668		T14	391		T15	178

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

403220

1

T5

13

T7

1

T16

43

values[0x0]

all_enables

biggest_size

603852

1

T6

1

T9

1

T10

4

values[0x1]

all_enables

biggest_size

603380

1

T10

1

T29

2

T13

52533