Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3858752

1

T1

196

T3

314

T4

341

full_word

2430514

1

T1

18

T3

26

T4

33

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6288986	1			T1	214		T3	340		T4	374
auto[TlIntgErrCmd]	91	1			T54	2		T55	4		T56	8
auto[TlIntgErrData]	102	1			T54	4		T55	5		T56	5
auto[TlIntgErrBoth]	87	1			T54	4		T55	1		T56	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

975609

1

T1

214

T3

340

T4

374

auto[1]

5313657

1

T13

472645

T14

325607

T15

140164

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	402148	1			T1	196		T3	314		T4	341
auto[TlIntgErrNone]	partial	auto[1]	3456347	1			T13	304252		T14	210647		T15	92964
auto[TlIntgErrNone]	full_word	auto[0]	573341	1			T1	18		T3	26		T4	33
auto[TlIntgErrNone]	full_word	auto[1]	1857150	1			T13	168393		T14	114960		T15	47200
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T55	1		T56	1		T104	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T54	2		T55	2		T56	6
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T55	1		T56	1		T101	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T103	1		T108	1		T109	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T54	2		T55	3		T104	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T54	2		T55	2		T56	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T100	1		T107	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T56	1		T100	1		T101	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T54	2		T55	1		T56	3
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T54	2		T56	4		T104	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T104	1		T106	1		T108	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T101	1		T108	1		-	-