Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3166773

1

T4

106

T6

93

T7

32744

full_word

2016723

1

T3

2

T4

10

T5

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5183176	1			T3	2		T4	116		T5	2
auto[TlIntgErrCmd]	121	1			T47	8		T48	8		T49	5
auto[TlIntgErrData]	101	1			T47	8		T48	3		T49	1
auto[TlIntgErrBoth]	98	1			T47	4		T48	9		T49	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

810668

1

T3

2

T4

116

T5

2

auto[1]

4372828

1

T7

45023

T10

226121

T13

133682

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	335201	1			T4	106		T6	93		T7	3635
auto[TlIntgErrNone]	partial	auto[1]	2831285	1			T7	29109		T10	143850		T13	87578
auto[TlIntgErrNone]	full_word	auto[0]	475326	1			T3	2		T4	10		T5	2
auto[TlIntgErrNone]	full_word	auto[1]	1541364	1			T7	15914		T10	82271		T13	46104
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T47	3		T48	3		T49	3
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T47	4		T48	3		T49	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T47	1		T48	1		T107	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T48	1		T105	1		T107	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T47	5		T48	1		T49	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T47	1		T48	1		T101	6
auto[TlIntgErrData]	full_word	auto[0]	6	1			T47	1		T48	1		T106	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T47	1		T107	1		T108	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T47	2		T48	5		T49	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T47	2		T48	2		T49	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T104	1		T99	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T48	2		T99	1		T108	2