Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	81891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2804509

1

T1

20

T3

5

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	727862	1			T1	192		T3	55		T5	3
values[0x0]	1059119	1			T23	104316		T11	15558		T24	33749
values[0x1]	1099419	1			T23	108777		T11	16158		T24	34676

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44978	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2841422

1

T1

120

T3

35

T5

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11004	1			T1	4		T23	1109		T11	172
valid_sources[0x01]	11423	1			T7	1		T23	1136		T11	157
valid_sources[0x02]	10743	1			T1	10		T23	1116		T11	177
valid_sources[0x03]	11733	1			T23	1131		T11	159		T29	1
valid_sources[0x04]	11300	1			T23	1131		T11	175		T31	2
valid_sources[0x05]	10908	1			T7	1		T10	1		T23	1117
valid_sources[0x06]	10879	1			T7	1		T10	2		T17	9
valid_sources[0x07]	12663	1			T23	1111		T11	175		T31	1
valid_sources[0x08]	11274	1			T23	1107		T11	165		T29	1
valid_sources[0x09]	9964	1			T23	1098		T11	189		T58	1
valid_sources[0x0a]	12409	1			T7	1		T23	1122		T11	167
valid_sources[0x0b]	12163	1			T7	1		T23	1066		T11	193
valid_sources[0x0c]	10930	1			T3	10		T7	3		T10	1
valid_sources[0x0d]	10818	1			T10	1		T23	1051		T11	164
valid_sources[0x0e]	11037	1			T10	2		T17	8		T23	1116
valid_sources[0x0f]	12848	1			T10	1		T23	1091		T11	157
valid_sources[0x10]	10544	1			T23	1100		T11	169		T29	3
valid_sources[0x11]	11809	1			T23	1080		T11	184		T31	1
valid_sources[0x12]	10449	1			T23	1113		T11	187		T24	344
valid_sources[0x13]	10932	1			T23	1142		T11	154		T58	1
valid_sources[0x14]	12395	1			T23	1174		T11	185		T24	347
valid_sources[0x15]	10266	1			T7	1		T17	8		T23	1137
valid_sources[0x16]	13705	1			T7	1		T23	1033		T11	156
valid_sources[0x17]	10217	1			T10	1		T23	1067		T11	140
valid_sources[0x18]	11314	1			T7	2		T10	2		T23	1139
valid_sources[0x19]	10610	1			T10	2		T23	1048		T11	144
valid_sources[0x1a]	12375	1			T14	3		T23	1139		T11	197
valid_sources[0x1b]	9939	1			T23	1059		T11	188		T31	1
valid_sources[0x1c]	11216	1			T7	1		T10	1		T23	1116
valid_sources[0x1d]	11205	1			T8	45		T23	1055		T11	166
valid_sources[0x1e]	11695	1			T10	2		T52	1		T23	1079
valid_sources[0x1f]	10857	1			T23	1098		T11	163		T24	363
valid_sources[0x20]	11124	1			T7	3		T23	1145		T11	187
valid_sources[0x21]	11489	1			T23	1088		T11	171		T31	1
valid_sources[0x22]	12135	1			T23	1152		T11	174		T31	2
valid_sources[0x23]	11707	1			T23	1076		T11	138		T34	1
valid_sources[0x24]	11455	1			T1	1		T23	1118		T11	173
valid_sources[0x25]	11462	1			T7	1		T10	4		T23	1107
valid_sources[0x26]	11135	1			T10	1		T23	1123		T11	169
valid_sources[0x27]	12031	1			T7	2		T10	1		T23	1064
valid_sources[0x28]	13028	1			T10	1		T23	1148		T11	144
valid_sources[0x29]	11423	1			T1	8		T23	1115		T11	205
valid_sources[0x2a]	11671	1			T7	1		T23	1100		T11	149
valid_sources[0x2b]	11307	1			T7	1		T23	1085		T11	171
valid_sources[0x2c]	11091	1			T7	3		T23	1137		T11	199
valid_sources[0x2d]	11556	1			T1	3		T7	1		T23	1062
valid_sources[0x2e]	10911	1			T1	2		T7	1		T23	1180
valid_sources[0x2f]	12237	1			T10	1		T23	1085		T11	182
valid_sources[0x30]	10797	1			T23	1091		T11	158		T29	3
valid_sources[0x31]	11531	1			T23	1188		T11	155		T24	404
valid_sources[0x32]	9990	1			T23	1068		T11	158		T29	1
valid_sources[0x33]	10738	1			T7	1		T23	1145		T11	175
valid_sources[0x34]	10996	1			T7	1		T23	1060		T11	147
valid_sources[0x35]	12410	1			T1	1		T23	1032		T11	183
valid_sources[0x36]	12235	1			T7	1		T10	2		T23	1097
valid_sources[0x37]	10434	1			T7	1		T10	1		T23	1108
valid_sources[0x38]	11758	1			T7	1		T10	3		T23	1147
valid_sources[0x39]	10672	1			T10	1		T17	2		T23	1042
valid_sources[0x3a]	11771	1			T23	1035		T11	155		T13	2
valid_sources[0x3b]	11594	1			T7	1		T10	1		T23	1083
valid_sources[0x3c]	12624	1			T7	1		T23	1091		T11	171
valid_sources[0x3d]	12212	1			T1	1		T23	1089		T11	178
valid_sources[0x3e]	11420	1			T23	1083		T11	160		T29	1
valid_sources[0x3f]	11675	1			T23	1111		T11	189		T24	364
valid_sources[0x40]	12050	1			T23	1100		T11	161		T31	1
valid_sources[0x41]	11271	1			T17	1		T23	1110		T11	169
valid_sources[0x42]	11219	1			T1	3		T23	1058		T11	169
valid_sources[0x43]	11103	1			T10	1		T23	1094		T11	151
valid_sources[0x44]	11959	1			T10	1		T23	1118		T11	176
valid_sources[0x45]	10716	1			T52	1		T23	1100		T11	146
valid_sources[0x46]	12139	1			T1	8		T23	1087		T11	183
valid_sources[0x47]	10077	1			T23	1098		T11	165		T29	2
valid_sources[0x48]	10191	1			T1	4		T23	1030		T11	144
valid_sources[0x49]	11782	1			T7	1		T23	1118		T11	147
valid_sources[0x4a]	11378	1			T10	2		T23	1127		T11	182
valid_sources[0x4b]	10906	1			T23	1083		T11	157		T29	2
valid_sources[0x4c]	10181	1			T23	1080		T11	157		T24	392
valid_sources[0x4d]	10720	1			T23	1127		T11	175		T29	3
valid_sources[0x4e]	10795	1			T10	1		T23	1114		T11	146
valid_sources[0x4f]	10720	1			T10	1		T17	5		T23	1162
valid_sources[0x50]	12296	1			T1	4		T7	1		T10	1
valid_sources[0x51]	10277	1			T7	1		T8	40		T23	1113
valid_sources[0x52]	11077	1			T7	2		T23	1151		T11	168
valid_sources[0x53]	11007	1			T10	1		T23	1143		T11	168
valid_sources[0x54]	10548	1			T23	1096		T11	166		T24	363
valid_sources[0x55]	11741	1			T3	8		T23	1081		T11	135
valid_sources[0x56]	11781	1			T23	1131		T11	151		T58	1
valid_sources[0x57]	10054	1			T7	2		T23	1103		T11	111
valid_sources[0x58]	11731	1			T10	1		T23	1093		T11	197
valid_sources[0x59]	11161	1			T10	1		T23	1111		T11	187
valid_sources[0x5a]	10133	1			T7	1		T23	1141		T11	184
valid_sources[0x5b]	12000	1			T10	1		T23	1134		T11	163
valid_sources[0x5c]	11495	1			T7	1		T10	1		T23	1115
valid_sources[0x5d]	9872	1			T1	2		T10	2		T17	5
valid_sources[0x5e]	10790	1			T10	1		T23	1066		T11	136
valid_sources[0x5f]	12025	1			T17	11		T23	1101		T11	134
valid_sources[0x60]	9879	1			T7	1		T23	1055		T11	169
valid_sources[0x61]	11130	1			T7	1		T23	1096		T11	157
valid_sources[0x62]	11023	1			T10	1		T23	1179		T11	167
valid_sources[0x63]	11524	1			T7	3		T23	1120		T11	190
valid_sources[0x64]	10990	1			T7	1		T23	1110		T11	174
valid_sources[0x65]	11932	1			T16	1		T23	1067		T11	171
valid_sources[0x66]	12505	1			T10	3		T23	1181		T11	176
valid_sources[0x67]	11393	1			T1	1		T23	1097		T11	209
valid_sources[0x68]	10757	1			T23	1130		T11	165		T58	1
valid_sources[0x69]	11008	1			T7	1		T10	1		T23	1110
valid_sources[0x6a]	11074	1			T10	1		T23	1124		T11	176
valid_sources[0x6b]	10944	1			T23	1140		T11	169		T24	334
valid_sources[0x6c]	11768	1			T3	1		T7	1		T23	1062
valid_sources[0x6d]	10917	1			T1	8		T7	1		T23	1032
valid_sources[0x6e]	10331	1			T10	1		T23	1130		T11	142
valid_sources[0x6f]	12600	1			T7	2		T10	1		T23	1153
valid_sources[0x70]	10896	1			T8	84		T23	1098		T11	182
valid_sources[0x71]	12037	1			T10	1		T23	1090		T11	171
valid_sources[0x72]	12720	1			T23	1161		T11	201		T29	3
valid_sources[0x73]	10950	1			T23	1126		T11	167		T29	1
valid_sources[0x74]	11005	1			T1	1		T10	1		T23	1184
valid_sources[0x75]	12027	1			T7	1		T10	1		T23	1095
valid_sources[0x76]	11100	1			T23	1226		T11	171		T29	3
valid_sources[0x77]	11141	1			T7	2		T10	2		T23	1132
valid_sources[0x78]	10959	1			T7	1		T23	1057		T11	174
valid_sources[0x79]	10678	1			T7	1		T10	1		T23	1081
valid_sources[0x7a]	14086	1			T10	1		T23	1115		T11	173
valid_sources[0x7b]	12769	1			T17	5		T23	1113		T11	141
valid_sources[0x7c]	11444	1			T7	1		T23	1095		T11	210
valid_sources[0x7d]	11933	1			T1	2		T7	1		T23	1091
valid_sources[0x7e]	12166	1			T7	1		T10	1		T23	1123
valid_sources[0x7f]	11984	1			T23	1047		T11	137		T29	1
valid_sources[0x80]	11412	1			T7	1		T10	1		T23	1194

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

703135

1

T1

20

T3

5

T5

3

values[0x0]

all_enables

biggest_size

1049956

1

T23

103386

T11

15421

T24

33464

values[0x1]

all_enables

biggest_size

1051418

1

T23

103818

T11

15468

T24

33181

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2127383

1

T2

1

T4

1

T5

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	572162	1			T2	1		T5	22		T9	1
values[0x0]	813910	1			T4	2		T6	3		T21	3
values[0x1]	942998	1			T4	5		T6	4		T21	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	86923	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2242147

1

T2

1

T4

2

T5

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9385	1			T23	899		T11	142		T24	375
valid_sources[0x01]	9097	1			T15	1		T23	910		T11	178
valid_sources[0x02]	9167	1			T23	892		T18	4		T11	153
valid_sources[0x03]	8804	1			T16	1		T23	900		T11	145
valid_sources[0x04]	9440	1			T23	875		T11	141		T31	1
valid_sources[0x05]	8305	1			T23	856		T11	126		T24	264
valid_sources[0x06]	9498	1			T16	1		T15	1		T23	914
valid_sources[0x07]	8710	1			T23	924		T11	144		T24	178
valid_sources[0x08]	9496	1			T15	1		T23	898		T11	125
valid_sources[0x09]	9038	1			T23	862		T11	147		T31	2
valid_sources[0x0a]	9520	1			T14	1		T23	855		T11	151
valid_sources[0x0b]	8865	1			T23	873		T18	4		T11	138
valid_sources[0x0c]	9048	1			T5	1		T23	931		T11	128
valid_sources[0x0d]	8902	1			T23	900		T11	166		T24	467
valid_sources[0x0e]	8654	1			T23	931		T11	146		T24	105
valid_sources[0x0f]	9364	1			T23	847		T11	139		T24	488
valid_sources[0x10]	9536	1			T5	1		T23	902		T11	154
valid_sources[0x11]	9152	1			T23	821		T11	147		T24	269
valid_sources[0x12]	10105	1			T14	1		T23	916		T11	138
valid_sources[0x13]	9013	1			T16	1		T23	896		T11	166
valid_sources[0x14]	8939	1			T23	893		T11	130		T24	419
valid_sources[0x15]	8753	1			T23	919		T11	164		T31	1
valid_sources[0x16]	9968	1			T23	906		T11	146		T24	281
valid_sources[0x17]	9343	1			T23	875		T11	134		T24	247
valid_sources[0x18]	8757	1			T5	1		T23	868		T11	149
valid_sources[0x19]	8992	1			T23	862		T11	132		T24	604
valid_sources[0x1a]	9530	1			T16	3		T23	890		T11	144
valid_sources[0x1b]	8189	1			T23	877		T11	126		T31	1
valid_sources[0x1c]	9520	1			T16	1		T14	4		T15	1
valid_sources[0x1d]	8947	1			T15	1		T23	953		T11	144
valid_sources[0x1e]	8856	1			T23	888		T11	158		T24	224
valid_sources[0x1f]	10176	1			T23	855		T11	145		T28	2
valid_sources[0x20]	9167	1			T23	890		T11	134		T31	1
valid_sources[0x21]	8902	1			T23	952		T11	146		T57	1
valid_sources[0x22]	9745	1			T16	2		T23	856		T11	156
valid_sources[0x23]	9245	1			T52	12		T23	840		T11	131
valid_sources[0x24]	8691	1			T23	881		T11	121		T30	2
valid_sources[0x25]	9210	1			T23	908		T11	145		T28	2
valid_sources[0x26]	8798	1			T14	2		T23	903		T11	107
valid_sources[0x27]	9548	1			T23	865		T11	142		T24	2
valid_sources[0x28]	9295	1			T23	915		T11	153		T57	1
valid_sources[0x29]	9475	1			T23	898		T11	154		T24	687
valid_sources[0x2a]	9586	1			T23	866		T11	137		T31	2
valid_sources[0x2b]	8906	1			T14	1		T23	842		T11	133
valid_sources[0x2c]	8764	1			T23	846		T11	145		T24	339
valid_sources[0x2d]	9028	1			T5	1		T15	1		T23	871
valid_sources[0x2e]	9345	1			T14	1		T56	11		T23	914
valid_sources[0x2f]	9049	1			T4	1		T15	1		T23	900
valid_sources[0x30]	8605	1			T16	1		T23	893		T11	135
valid_sources[0x31]	9646	1			T23	928		T11	134		T24	273
valid_sources[0x32]	8347	1			T14	1		T15	1		T23	899
valid_sources[0x33]	9041	1			T23	897		T11	128		T24	280
valid_sources[0x34]	8721	1			T14	1		T23	910		T11	137
valid_sources[0x35]	8568	1			T23	852		T11	158		T24	307
valid_sources[0x36]	9058	1			T15	1		T23	868		T11	128
valid_sources[0x37]	8546	1			T4	1		T15	1		T23	884
valid_sources[0x38]	9438	1			T23	947		T11	128		T13	1
valid_sources[0x39]	9334	1			T23	889		T11	143		T24	543
valid_sources[0x3a]	9568	1			T23	893		T11	132		T24	546
valid_sources[0x3b]	9086	1			T23	886		T11	140		T24	46
valid_sources[0x3c]	9350	1			T23	937		T11	146		T24	359
valid_sources[0x3d]	8492	1			T14	1		T23	939		T11	138
valid_sources[0x3e]	8825	1			T23	888		T11	132		T24	112
valid_sources[0x3f]	9049	1			T5	1		T23	902		T11	136
valid_sources[0x40]	9504	1			T23	892		T11	122		T24	303
valid_sources[0x41]	9550	1			T23	871		T11	152		T32	3
valid_sources[0x42]	8441	1			T23	898		T11	132		T24	6
valid_sources[0x43]	8218	1			T23	914		T11	155		T24	108
valid_sources[0x44]	8936	1			T23	919		T11	153		T24	472
valid_sources[0x45]	8526	1			T23	908		T11	135		T24	345
valid_sources[0x46]	10481	1			T23	938		T11	168		T57	1
valid_sources[0x47]	9326	1			T16	2		T23	883		T18	1
valid_sources[0x48]	9245	1			T23	873		T11	130		T24	520
valid_sources[0x49]	9379	1			T23	824		T11	133		T31	1
valid_sources[0x4a]	9234	1			T16	2		T15	1		T23	910
valid_sources[0x4b]	9558	1			T16	2		T23	923		T11	142
valid_sources[0x4c]	9284	1			T23	872		T11	162		T24	244
valid_sources[0x4d]	8744	1			T23	878		T11	115		T24	240
valid_sources[0x4e]	8857	1			T5	1		T23	896		T11	152
valid_sources[0x4f]	8400	1			T23	876		T11	140		T24	454
valid_sources[0x50]	8997	1			T23	927		T11	123		T24	176
valid_sources[0x51]	9793	1			T14	2		T23	909		T11	148
valid_sources[0x52]	8151	1			T5	1		T23	901		T11	142
valid_sources[0x53]	8933	1			T14	3		T23	904		T11	134
valid_sources[0x54]	9412	1			T23	854		T11	145		T24	436
valid_sources[0x55]	8643	1			T23	895		T11	164		T31	2
valid_sources[0x56]	8442	1			T15	1		T23	887		T11	114
valid_sources[0x57]	9464	1			T16	1		T23	878		T11	127
valid_sources[0x58]	9164	1			T23	936		T11	145		T42	6
valid_sources[0x59]	9216	1			T4	1		T23	910		T11	146
valid_sources[0x5a]	9482	1			T5	1		T16	1		T23	859
valid_sources[0x5b]	9686	1			T16	1		T15	1		T23	917
valid_sources[0x5c]	8935	1			T15	1		T23	876		T11	162
valid_sources[0x5d]	9041	1			T5	1		T23	878		T11	158
valid_sources[0x5e]	9378	1			T16	2		T23	896		T11	166
valid_sources[0x5f]	9852	1			T23	887		T11	161		T24	757
valid_sources[0x60]	7750	1			T23	833		T11	126		T24	104
valid_sources[0x61]	9571	1			T23	887		T11	155		T31	1
valid_sources[0x62]	9445	1			T33	6		T23	842		T11	142
valid_sources[0x63]	8886	1			T23	901		T11	155		T24	120
valid_sources[0x64]	9317	1			T23	905		T11	144		T24	236
valid_sources[0x65]	9325	1			T23	906		T11	147		T24	300
valid_sources[0x66]	9102	1			T23	949		T11	136		T24	265
valid_sources[0x67]	9440	1			T2	1		T23	827		T11	148
valid_sources[0x68]	8814	1			T23	874		T11	141		T30	3
valid_sources[0x69]	8593	1			T5	1		T23	786		T11	164
valid_sources[0x6a]	8580	1			T23	943		T11	127		T24	153
valid_sources[0x6b]	9726	1			T23	933		T11	147		T24	348
valid_sources[0x6c]	9818	1			T23	904		T11	162		T24	364
valid_sources[0x6d]	9540	1			T23	923		T11	117		T31	2
valid_sources[0x6e]	8822	1			T23	922		T11	155		T24	197
valid_sources[0x6f]	8844	1			T14	1		T23	848		T11	133
valid_sources[0x70]	9518	1			T16	1		T23	894		T11	140
valid_sources[0x71]	9256	1			T23	922		T11	160		T31	1
valid_sources[0x72]	8391	1			T23	875		T11	149		T31	2
valid_sources[0x73]	8733	1			T23	845		T11	151		T24	42
valid_sources[0x74]	8703	1			T23	848		T11	118		T32	3
valid_sources[0x75]	8595	1			T23	866		T11	153		T24	1
valid_sources[0x76]	9511	1			T23	943		T11	156		T24	679
valid_sources[0x77]	9342	1			T23	837		T11	125		T24	71
valid_sources[0x78]	8860	1			T23	849		T27	19		T11	134
valid_sources[0x79]	8934	1			T14	1		T23	904		T11	113
valid_sources[0x7a]	9222	1			T5	1		T23	862		T11	133
valid_sources[0x7b]	8947	1			T23	854		T11	137		T24	132
valid_sources[0x7c]	9328	1			T23	876		T11	134		T31	1
valid_sources[0x7d]	9198	1			T14	1		T23	905		T11	130
valid_sources[0x7e]	8625	1			T23	869		T11	121		T24	88
valid_sources[0x7f]	9380	1			T9	1		T15	1		T23	901
valid_sources[0x80]	8610	1			T23	862		T11	148		T42	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

534405

1

T2

1

T5

9

T22

1

values[0x0]

all_enables

biggest_size

797397

1

T4

1

T6

1

T21

3

values[0x1]

all_enables

biggest_size

795581

1

T6

1

T56

2

T23

77871