Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5074557

1

T1

172

T3

50

T7

100

full_word

3271926

1

T1

20

T3

5

T5

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8346193	1			T1	192		T3	55		T5	2
auto[TlIntgErrCmd]	93	1			T49	7		T50	5		T51	3
auto[TlIntgErrData]	91	1			T49	3		T50	9		T51	2
auto[TlIntgErrBoth]	106	1			T49	10		T50	6		T51	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1295703

1

T1

192

T3

55

T5

2

auto[1]

7050780

1

T23

709970

T11

104471

T24

217249

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	524582	1			T1	172		T3	50		T7	100
auto[TlIntgErrNone]	partial	auto[1]	4549710	1			T23	462236		T11	67650		T24	138301
auto[TlIntgErrNone]	full_word	auto[0]	770976	1			T1	20		T3	5		T5	2
auto[TlIntgErrNone]	full_word	auto[1]	2500925	1			T23	247734		T11	36821		T24	78948
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T49	2		T50	4		T51	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T49	5		T50	1		T51	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T99	1		T100	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T101	1		T96	1		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1			T49	3		T50	5		T91	1
auto[TlIntgErrData]	partial	auto[1]	35	1			T50	4		T51	2		T91	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T91	1		T92	1		T102	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T95	1		T100	1		T96	2
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T49	2		T50	2		T92	5
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T49	6		T50	4		T51	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T49	1		T51	1		T103	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T49	1		T98	1		-	-