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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.35 96.89 92.42 97.67 100.00 98.62 97.45 98.37


Total test records in report: 432
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T298 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1937741559 Aug 08 06:08:04 PM PDT 24 Aug 08 06:08:10 PM PDT 24 842907771 ps
T299 /workspace/coverage/default/16.rom_ctrl_stress_all.3277253758 Aug 08 06:07:55 PM PDT 24 Aug 08 06:08:08 PM PDT 24 609845198 ps
T300 /workspace/coverage/default/31.rom_ctrl_alert_test.2471877784 Aug 08 06:08:03 PM PDT 24 Aug 08 06:08:08 PM PDT 24 88853435 ps
T22 /workspace/coverage/default/2.rom_ctrl_sec_cm.3042586914 Aug 08 06:07:42 PM PDT 24 Aug 08 06:08:37 PM PDT 24 352943748 ps
T301 /workspace/coverage/default/43.rom_ctrl_alert_test.680788256 Aug 08 06:08:11 PM PDT 24 Aug 08 06:08:15 PM PDT 24 321483464 ps
T302 /workspace/coverage/default/15.rom_ctrl_stress_all.1814256264 Aug 08 06:07:47 PM PDT 24 Aug 08 06:08:00 PM PDT 24 316886667 ps
T303 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2444784339 Aug 08 06:08:06 PM PDT 24 Aug 08 06:08:11 PM PDT 24 206025923 ps
T304 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2572837614 Aug 08 06:07:45 PM PDT 24 Aug 08 06:07:50 PM PDT 24 406728291 ps
T305 /workspace/coverage/default/34.rom_ctrl_alert_test.2091894696 Aug 08 06:07:59 PM PDT 24 Aug 08 06:08:04 PM PDT 24 89296157 ps
T306 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.641233399 Aug 08 06:07:40 PM PDT 24 Aug 08 06:09:39 PM PDT 24 9563846267 ps
T307 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.294410468 Aug 08 06:07:44 PM PDT 24 Aug 08 06:10:21 PM PDT 24 2842973836 ps
T308 /workspace/coverage/default/13.rom_ctrl_alert_test.1049659582 Aug 08 06:08:00 PM PDT 24 Aug 08 06:08:05 PM PDT 24 779053953 ps
T309 /workspace/coverage/default/28.rom_ctrl_alert_test.2033845600 Aug 08 06:07:50 PM PDT 24 Aug 08 06:07:54 PM PDT 24 172057812 ps
T310 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.474679000 Aug 08 06:08:23 PM PDT 24 Aug 08 06:09:50 PM PDT 24 2569330581 ps
T311 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2902157753 Aug 08 06:08:01 PM PDT 24 Aug 08 06:22:09 PM PDT 24 82146957081 ps
T312 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3496658884 Aug 08 06:07:48 PM PDT 24 Aug 08 06:07:57 PM PDT 24 531800482 ps
T313 /workspace/coverage/default/18.rom_ctrl_alert_test.2364324765 Aug 08 06:07:44 PM PDT 24 Aug 08 06:07:49 PM PDT 24 176752179 ps
T314 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1672447763 Aug 08 06:07:31 PM PDT 24 Aug 08 06:07:40 PM PDT 24 500338426 ps
T315 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1448361889 Aug 08 06:08:17 PM PDT 24 Aug 08 06:10:36 PM PDT 24 16425322378 ps
T316 /workspace/coverage/default/27.rom_ctrl_stress_all.341155091 Aug 08 06:07:52 PM PDT 24 Aug 08 06:08:01 PM PDT 24 559084370 ps
T317 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3642289078 Aug 08 06:07:45 PM PDT 24 Aug 08 06:07:57 PM PDT 24 994203974 ps
T318 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2615011613 Aug 08 06:08:00 PM PDT 24 Aug 08 06:10:32 PM PDT 24 3186007215 ps
T319 /workspace/coverage/default/24.rom_ctrl_alert_test.1655452753 Aug 08 06:08:12 PM PDT 24 Aug 08 06:08:17 PM PDT 24 127118696 ps
T320 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.975833147 Aug 08 06:08:06 PM PDT 24 Aug 08 06:08:16 PM PDT 24 645834413 ps
T321 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2610597187 Aug 08 06:07:34 PM PDT 24 Aug 08 06:07:41 PM PDT 24 139141330 ps
T322 /workspace/coverage/default/7.rom_ctrl_stress_all.1909428621 Aug 08 06:07:43 PM PDT 24 Aug 08 06:07:59 PM PDT 24 1184549659 ps
T323 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3601609721 Aug 08 06:08:12 PM PDT 24 Aug 08 06:08:24 PM PDT 24 520234744 ps
T324 /workspace/coverage/default/30.rom_ctrl_alert_test.3328962265 Aug 08 06:07:58 PM PDT 24 Aug 08 06:08:03 PM PDT 24 521138816 ps
T26 /workspace/coverage/default/4.rom_ctrl_sec_cm.498663821 Aug 08 06:07:39 PM PDT 24 Aug 08 06:09:17 PM PDT 24 746122173 ps
T325 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1629887556 Aug 08 06:08:13 PM PDT 24 Aug 08 06:08:29 PM PDT 24 5191701194 ps
T326 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.159039503 Aug 08 06:07:49 PM PDT 24 Aug 08 06:07:54 PM PDT 24 369519360 ps
T27 /workspace/coverage/default/0.rom_ctrl_sec_cm.1118935026 Aug 08 06:07:51 PM PDT 24 Aug 08 06:09:35 PM PDT 24 329239442 ps
T327 /workspace/coverage/default/0.rom_ctrl_alert_test.1602375027 Aug 08 06:07:30 PM PDT 24 Aug 08 06:07:36 PM PDT 24 132261624 ps
T328 /workspace/coverage/default/42.rom_ctrl_stress_all.4119527132 Aug 08 06:08:19 PM PDT 24 Aug 08 06:08:29 PM PDT 24 489159498 ps
T329 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2754180066 Aug 08 06:08:06 PM PDT 24 Aug 08 06:08:12 PM PDT 24 533502900 ps
T330 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2301519808 Aug 08 06:07:39 PM PDT 24 Aug 08 06:07:44 PM PDT 24 197644911 ps
T331 /workspace/coverage/default/11.rom_ctrl_alert_test.4034347938 Aug 08 06:08:09 PM PDT 24 Aug 08 06:08:14 PM PDT 24 518239750 ps
T64 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1234206225 Aug 08 05:39:44 PM PDT 24 Aug 08 05:39:51 PM PDT 24 137754870 ps
T65 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.56248777 Aug 08 05:39:30 PM PDT 24 Aug 08 05:39:35 PM PDT 24 498671787 ps
T66 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3830473615 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:05 PM PDT 24 89095675 ps
T332 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1509057749 Aug 08 05:39:44 PM PDT 24 Aug 08 05:39:49 PM PDT 24 127535771 ps
T333 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1195489953 Aug 08 05:39:59 PM PDT 24 Aug 08 05:40:08 PM PDT 24 498312608 ps
T334 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1598328349 Aug 08 05:39:42 PM PDT 24 Aug 08 05:39:48 PM PDT 24 511399513 ps
T111 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.658729581 Aug 08 05:39:31 PM PDT 24 Aug 08 05:39:36 PM PDT 24 173147205 ps
T73 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.786756135 Aug 08 05:39:40 PM PDT 24 Aug 08 05:40:08 PM PDT 24 1072677339 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.368103763 Aug 08 05:39:30 PM PDT 24 Aug 08 05:39:34 PM PDT 24 300098404 ps
T74 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1882651060 Aug 08 05:39:41 PM PDT 24 Aug 08 05:39:45 PM PDT 24 85858290 ps
T335 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.429867472 Aug 08 05:39:41 PM PDT 24 Aug 08 05:39:47 PM PDT 24 135131921 ps
T336 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2456737875 Aug 08 05:39:44 PM PDT 24 Aug 08 05:39:49 PM PDT 24 204091762 ps
T75 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1668899306 Aug 08 05:39:24 PM PDT 24 Aug 08 05:39:42 PM PDT 24 739749994 ps
T337 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1064863074 Aug 08 05:39:59 PM PDT 24 Aug 08 05:40:07 PM PDT 24 559213979 ps
T76 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1001698281 Aug 08 05:40:01 PM PDT 24 Aug 08 05:40:20 PM PDT 24 378558925 ps
T115 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3820103787 Aug 08 05:39:32 PM PDT 24 Aug 08 05:39:36 PM PDT 24 335405636 ps
T338 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.694114437 Aug 08 05:39:50 PM PDT 24 Aug 08 05:39:56 PM PDT 24 520890430 ps
T113 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.829735829 Aug 08 05:40:01 PM PDT 24 Aug 08 05:40:19 PM PDT 24 1489280641 ps
T339 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4265843089 Aug 08 05:39:44 PM PDT 24 Aug 08 05:39:48 PM PDT 24 332864276 ps
T340 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1985485646 Aug 08 05:40:03 PM PDT 24 Aug 08 05:40:12 PM PDT 24 136755115 ps
T341 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.478975417 Aug 08 05:40:13 PM PDT 24 Aug 08 05:40:19 PM PDT 24 135921660 ps
T342 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2057590001 Aug 08 05:39:49 PM PDT 24 Aug 08 05:39:55 PM PDT 24 539890543 ps
T114 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2530856844 Aug 08 05:39:44 PM PDT 24 Aug 08 05:39:48 PM PDT 24 85851372 ps
T61 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2521346961 Aug 08 05:39:58 PM PDT 24 Aug 08 05:40:35 PM PDT 24 578182381 ps
T343 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1947476154 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:04 PM PDT 24 91911631 ps
T344 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3780207862 Aug 08 05:39:41 PM PDT 24 Aug 08 05:39:46 PM PDT 24 132622103 ps
T77 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.589834962 Aug 08 05:39:59 PM PDT 24 Aug 08 05:40:04 PM PDT 24 592197176 ps
T78 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1935823753 Aug 08 05:39:43 PM PDT 24 Aug 08 05:39:50 PM PDT 24 2640958866 ps
T345 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.513487521 Aug 08 05:39:49 PM PDT 24 Aug 08 05:39:54 PM PDT 24 956636428 ps
T346 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1411083506 Aug 08 05:39:50 PM PDT 24 Aug 08 05:39:56 PM PDT 24 272653068 ps
T347 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2174301000 Aug 08 05:39:58 PM PDT 24 Aug 08 05:40:17 PM PDT 24 363066884 ps
T348 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3283868792 Aug 08 05:39:31 PM PDT 24 Aug 08 05:39:36 PM PDT 24 622182592 ps
T349 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3746842898 Aug 08 05:39:59 PM PDT 24 Aug 08 05:40:04 PM PDT 24 90818323 ps
T350 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.380850331 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:04 PM PDT 24 639067765 ps
T351 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4164214871 Aug 08 05:39:59 PM PDT 24 Aug 08 05:40:07 PM PDT 24 169557927 ps
T62 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2189903299 Aug 08 05:39:31 PM PDT 24 Aug 08 05:40:43 PM PDT 24 994066832 ps
T352 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.621848280 Aug 08 05:39:50 PM PDT 24 Aug 08 05:39:56 PM PDT 24 422999512 ps
T353 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3866009528 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:04 PM PDT 24 86326457 ps
T354 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1893497615 Aug 08 05:39:22 PM PDT 24 Aug 08 05:39:27 PM PDT 24 226077524 ps
T79 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.921596925 Aug 08 05:40:01 PM PDT 24 Aug 08 05:40:06 PM PDT 24 500794013 ps
T355 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3917779024 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:06 PM PDT 24 194170551 ps
T85 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4140877371 Aug 08 05:39:40 PM PDT 24 Aug 08 05:39:46 PM PDT 24 94912304 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3893866362 Aug 08 05:39:32 PM PDT 24 Aug 08 05:39:50 PM PDT 24 361507596 ps
T63 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.440496065 Aug 08 05:39:26 PM PDT 24 Aug 08 05:40:43 PM PDT 24 651650222 ps
T356 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2626976189 Aug 08 05:39:44 PM PDT 24 Aug 08 05:39:49 PM PDT 24 126335055 ps
T357 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2359657827 Aug 08 05:39:49 PM PDT 24 Aug 08 05:39:54 PM PDT 24 131481963 ps
T358 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1060650124 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:05 PM PDT 24 380833050 ps
T359 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.47721515 Aug 08 05:39:41 PM PDT 24 Aug 08 05:40:03 PM PDT 24 1866049372 ps
T360 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1743784292 Aug 08 05:39:29 PM PDT 24 Aug 08 05:39:34 PM PDT 24 362220201 ps
T119 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3097900614 Aug 08 05:40:01 PM PDT 24 Aug 08 05:41:12 PM PDT 24 551193802 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2806408773 Aug 08 05:39:32 PM PDT 24 Aug 08 05:39:36 PM PDT 24 1037099590 ps
T128 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.505193591 Aug 08 05:39:59 PM PDT 24 Aug 08 05:41:10 PM PDT 24 287562695 ps
T361 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2920943183 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:06 PM PDT 24 590749480 ps
T362 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2296656167 Aug 08 05:39:59 PM PDT 24 Aug 08 05:40:22 PM PDT 24 1043375457 ps
T363 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2124681931 Aug 08 05:39:50 PM PDT 24 Aug 08 05:40:10 PM PDT 24 380399949 ps
T364 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4112128981 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:11 PM PDT 24 155463377 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2422575632 Aug 08 05:39:31 PM PDT 24 Aug 08 05:39:37 PM PDT 24 131436815 ps
T366 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2950221574 Aug 08 05:39:24 PM PDT 24 Aug 08 05:39:33 PM PDT 24 130912293 ps
T120 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3180559458 Aug 08 05:39:49 PM PDT 24 Aug 08 05:41:00 PM PDT 24 1329238874 ps
T367 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1650825536 Aug 08 05:39:42 PM PDT 24 Aug 08 05:39:47 PM PDT 24 350178888 ps
T126 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2250787525 Aug 08 05:39:39 PM PDT 24 Aug 08 05:40:16 PM PDT 24 168934937 ps
T368 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1882205122 Aug 08 05:39:41 PM PDT 24 Aug 08 05:39:51 PM PDT 24 2033551110 ps
T369 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2353860367 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:09 PM PDT 24 543838966 ps
T370 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1855261487 Aug 08 05:39:58 PM PDT 24 Aug 08 05:40:04 PM PDT 24 153695002 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.62193577 Aug 08 05:39:39 PM PDT 24 Aug 08 05:39:47 PM PDT 24 438798049 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4253211059 Aug 08 05:39:33 PM PDT 24 Aug 08 05:39:38 PM PDT 24 501468010 ps
T122 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3683251434 Aug 08 05:39:30 PM PDT 24 Aug 08 05:40:41 PM PDT 24 278493924 ps
T373 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3009183847 Aug 08 05:39:39 PM PDT 24 Aug 08 05:39:44 PM PDT 24 290868432 ps
T87 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3465679951 Aug 08 05:40:01 PM PDT 24 Aug 08 05:40:06 PM PDT 24 752919582 ps
T88 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2393297534 Aug 08 05:39:49 PM PDT 24 Aug 08 05:40:11 PM PDT 24 2091583365 ps
T374 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.250672395 Aug 08 05:39:49 PM PDT 24 Aug 08 05:39:59 PM PDT 24 138154727 ps
T375 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2694146977 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:07 PM PDT 24 346411405 ps
T124 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3260757255 Aug 08 05:39:49 PM PDT 24 Aug 08 05:40:28 PM PDT 24 2366393971 ps
T376 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1215486956 Aug 08 05:39:42 PM PDT 24 Aug 08 05:40:19 PM PDT 24 596213042 ps
T377 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2706168875 Aug 08 05:39:48 PM PDT 24 Aug 08 05:39:55 PM PDT 24 592856547 ps
T378 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.779348107 Aug 08 05:40:01 PM PDT 24 Aug 08 05:40:39 PM PDT 24 212561760 ps
T89 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3857469119 Aug 08 05:39:44 PM PDT 24 Aug 08 05:39:48 PM PDT 24 86172999 ps
T379 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.916333999 Aug 08 05:39:31 PM PDT 24 Aug 08 05:39:36 PM PDT 24 252173720 ps
T380 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2544626482 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:05 PM PDT 24 219065567 ps
T381 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.483119931 Aug 08 05:39:40 PM PDT 24 Aug 08 05:39:45 PM PDT 24 1771302112 ps
T382 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2778399870 Aug 08 05:39:32 PM PDT 24 Aug 08 05:39:41 PM PDT 24 474418993 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2331359496 Aug 08 05:39:59 PM PDT 24 Aug 08 05:40:06 PM PDT 24 139772790 ps
T384 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2412922909 Aug 08 05:39:30 PM PDT 24 Aug 08 05:39:35 PM PDT 24 538354781 ps
T90 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3329475092 Aug 08 05:39:44 PM PDT 24 Aug 08 05:40:17 PM PDT 24 797585988 ps
T385 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4115223813 Aug 08 05:40:01 PM PDT 24 Aug 08 05:40:28 PM PDT 24 1103048259 ps
T386 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2489032800 Aug 08 05:39:40 PM PDT 24 Aug 08 05:39:46 PM PDT 24 482363834 ps
T387 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.298220371 Aug 08 05:39:30 PM PDT 24 Aug 08 05:39:50 PM PDT 24 374533064 ps
T388 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1719452133 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:36 PM PDT 24 531157531 ps
T389 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4240876197 Aug 08 05:39:49 PM PDT 24 Aug 08 05:39:55 PM PDT 24 518493311 ps
T390 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1284853177 Aug 08 05:39:32 PM PDT 24 Aug 08 05:39:39 PM PDT 24 1135528562 ps
T391 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3441137166 Aug 08 05:40:01 PM PDT 24 Aug 08 05:40:06 PM PDT 24 1040259390 ps
T392 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4082870203 Aug 08 05:39:41 PM PDT 24 Aug 08 05:39:46 PM PDT 24 250164985 ps
T393 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1281739748 Aug 08 05:39:49 PM PDT 24 Aug 08 05:39:56 PM PDT 24 96724767 ps
T394 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1166030662 Aug 08 05:39:30 PM PDT 24 Aug 08 05:39:37 PM PDT 24 732523726 ps
T91 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2419923323 Aug 08 05:39:40 PM PDT 24 Aug 08 05:39:45 PM PDT 24 248755072 ps
T127 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1935800917 Aug 08 05:39:43 PM PDT 24 Aug 08 05:40:54 PM PDT 24 248014341 ps
T395 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3808768877 Aug 08 05:39:49 PM PDT 24 Aug 08 05:39:57 PM PDT 24 510240804 ps
T396 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.753559111 Aug 08 05:39:49 PM PDT 24 Aug 08 05:39:55 PM PDT 24 188256037 ps
T397 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.503103791 Aug 08 05:39:57 PM PDT 24 Aug 08 05:40:02 PM PDT 24 255016975 ps
T125 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.801644999 Aug 08 05:40:01 PM PDT 24 Aug 08 05:41:10 PM PDT 24 756023865 ps
T398 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3592330311 Aug 08 05:39:42 PM PDT 24 Aug 08 05:39:47 PM PDT 24 963732511 ps
T399 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1201581052 Aug 08 05:39:59 PM PDT 24 Aug 08 05:40:04 PM PDT 24 132264612 ps
T400 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1813873241 Aug 08 05:39:50 PM PDT 24 Aug 08 05:40:00 PM PDT 24 499050250 ps
T92 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.393703643 Aug 08 05:39:31 PM PDT 24 Aug 08 05:40:03 PM PDT 24 814504532 ps
T401 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1107008033 Aug 08 05:39:40 PM PDT 24 Aug 08 05:39:49 PM PDT 24 128200158 ps
T402 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1914504153 Aug 08 05:39:29 PM PDT 24 Aug 08 05:39:34 PM PDT 24 88119351 ps
T403 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2108388690 Aug 08 05:39:30 PM PDT 24 Aug 08 05:39:35 PM PDT 24 321198078 ps
T404 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1657550446 Aug 08 05:39:44 PM PDT 24 Aug 08 05:39:53 PM PDT 24 85462798 ps
T405 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4204415913 Aug 08 05:39:59 PM PDT 24 Aug 08 05:40:36 PM PDT 24 3456040368 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.544467682 Aug 08 05:39:31 PM PDT 24 Aug 08 05:39:36 PM PDT 24 216058965 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2044602785 Aug 08 05:39:31 PM PDT 24 Aug 08 05:39:37 PM PDT 24 769427344 ps
T408 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.111514589 Aug 08 05:39:58 PM PDT 24 Aug 08 05:40:04 PM PDT 24 271323827 ps
T409 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2532830517 Aug 08 05:39:44 PM PDT 24 Aug 08 05:39:49 PM PDT 24 116133810 ps
T94 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1889663198 Aug 08 05:39:51 PM PDT 24 Aug 08 05:40:23 PM PDT 24 818877256 ps
T410 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1617436353 Aug 08 05:39:43 PM PDT 24 Aug 08 05:40:20 PM PDT 24 155947614 ps
T123 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3529545256 Aug 08 05:39:49 PM PDT 24 Aug 08 05:40:26 PM PDT 24 168297087 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3242321481 Aug 08 05:39:33 PM PDT 24 Aug 08 05:39:38 PM PDT 24 132827310 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.152731305 Aug 08 05:39:32 PM PDT 24 Aug 08 05:39:39 PM PDT 24 91551735 ps
T98 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3879294503 Aug 08 05:39:44 PM PDT 24 Aug 08 05:39:52 PM PDT 24 94151282 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3884450078 Aug 08 05:39:30 PM PDT 24 Aug 08 05:39:36 PM PDT 24 132163395 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.534687576 Aug 08 05:39:42 PM PDT 24 Aug 08 05:39:46 PM PDT 24 336457222 ps
T413 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3618961301 Aug 08 05:40:00 PM PDT 24 Aug 08 05:40:06 PM PDT 24 274113107 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.802206944 Aug 08 05:40:01 PM PDT 24 Aug 08 05:40:23 PM PDT 24 2087407673 ps
T415 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1730937592 Aug 08 05:39:59 PM PDT 24 Aug 08 05:40:32 PM PDT 24 1579939247 ps
T121 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2703112219 Aug 08 05:39:30 PM PDT 24 Aug 08 05:40:39 PM PDT 24 873419148 ps
T416 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2599994140 Aug 08 05:39:48 PM PDT 24 Aug 08 05:39:58 PM PDT 24 132613386 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3024358180 Aug 08 05:39:31 PM PDT 24 Aug 08 05:39:39 PM PDT 24 131238472 ps
T96 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2365276299 Aug 08 05:39:31 PM PDT 24 Aug 08 05:39:35 PM PDT 24 87661160 ps
T418 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1649578949 Aug 08 05:39:42 PM PDT 24 Aug 08 05:39:48 PM PDT 24 147251373 ps
T99 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2517365262 Aug 08 05:39:44 PM PDT 24 Aug 08 05:40:06 PM PDT 24 1115426199 ps
T419 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1350216630 Aug 08 05:39:41 PM PDT 24 Aug 08 05:39:46 PM PDT 24 416317628 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.651636939 Aug 08 05:39:33 PM PDT 24 Aug 08 05:39:37 PM PDT 24 175322910 ps
T421 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3822676868 Aug 08 05:40:01 PM PDT 24 Aug 08 05:40:07 PM PDT 24 264421712 ps
T422 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2684862508 Aug 08 05:39:50 PM PDT 24 Aug 08 05:40:27 PM PDT 24 171657701 ps
T100 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1877473221 Aug 08 05:39:48 PM PDT 24 Aug 08 05:40:20 PM PDT 24 1625666931 ps
T423 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3800664300 Aug 08 05:40:11 PM PDT 24 Aug 08 05:40:17 PM PDT 24 544119396 ps
T424 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.209951 Aug 08 05:39:49 PM PDT 24 Aug 08 05:39:55 PM PDT 24 252253474 ps
T425 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3565749031 Aug 08 05:39:49 PM PDT 24 Aug 08 05:40:27 PM PDT 24 185895026 ps
T426 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3268556982 Aug 08 05:39:41 PM PDT 24 Aug 08 05:39:46 PM PDT 24 105042122 ps
T427 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3647151554 Aug 08 05:39:43 PM PDT 24 Aug 08 05:40:03 PM PDT 24 373664268 ps
T428 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3766861494 Aug 08 05:39:30 PM PDT 24 Aug 08 05:39:35 PM PDT 24 239861908 ps
T429 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4043559028 Aug 08 05:39:50 PM PDT 24 Aug 08 05:39:58 PM PDT 24 496023825 ps
T430 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1928418647 Aug 08 05:40:02 PM PDT 24 Aug 08 05:40:09 PM PDT 24 142534943 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.410350130 Aug 08 05:39:32 PM PDT 24 Aug 08 05:39:37 PM PDT 24 518855050 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3029572922 Aug 08 05:39:50 PM PDT 24 Aug 08 05:39:56 PM PDT 24 130440950 ps

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2104243510
Short name T10
Test name
Test status
Simulation time 61920956256 ps
CPU time 2663.58 seconds
Started Aug 08 06:08:18 PM PDT 24
Finished Aug 08 06:52:42 PM PDT 24
Peak memory 243216 kb
Host smart-5b12bf1f-febf-4368-8342-761a4894231a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104243510 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2104243510
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2122839840
Short name T3
Test name
Test status
Simulation time 6668710359 ps
CPU time 102.51 seconds
Started Aug 08 06:08:12 PM PDT 24
Finished Aug 08 06:09:55 PM PDT 24
Peak memory 238512 kb
Host smart-96a48ff2-f47f-41d4-93cc-f64d16fac4cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122839840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2122839840
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2265448164
Short name T19
Test name
Test status
Simulation time 3065906587 ps
CPU time 146.23 seconds
Started Aug 08 06:08:12 PM PDT 24
Finished Aug 08 06:10:38 PM PDT 24
Peak memory 214444 kb
Host smart-551cef6d-d44e-4836-a775-a958c60fb68a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265448164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2265448164
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2189903299
Short name T62
Test name
Test status
Simulation time 994066832 ps
CPU time 71.6 seconds
Started Aug 08 05:39:31 PM PDT 24
Finished Aug 08 05:40:43 PM PDT 24
Peak memory 213068 kb
Host smart-38f09935-0332-49cc-a2b5-2f6f38807287
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189903299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2189903299
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1756414192
Short name T52
Test name
Test status
Simulation time 3151872460 ps
CPU time 192.65 seconds
Started Aug 08 06:07:57 PM PDT 24
Finished Aug 08 06:11:10 PM PDT 24
Peak memory 235588 kb
Host smart-dbb34e50-00f9-4b3e-a4b7-1532718ac7cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756414192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1756414192
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3503602777
Short name T11
Test name
Test status
Simulation time 424039992 ps
CPU time 9.03 seconds
Started Aug 08 06:07:36 PM PDT 24
Finished Aug 08 06:07:45 PM PDT 24
Peak memory 212172 kb
Host smart-0d08bca8-8279-4aea-9934-28b663f61afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503602777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3503602777
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1390234530
Short name T21
Test name
Test status
Simulation time 175018630 ps
CPU time 52.59 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 236724 kb
Host smart-98779ec6-166d-4bae-87b3-dafe3c1cff31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390234530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1390234530
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3180559458
Short name T120
Test name
Test status
Simulation time 1329238874 ps
CPU time 70.73 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:41:00 PM PDT 24
Peak memory 213236 kb
Host smart-4285f43b-6bff-41c3-812b-8d019b607bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180559458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3180559458
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1668899306
Short name T75
Test name
Test status
Simulation time 739749994 ps
CPU time 18.05 seconds
Started Aug 08 05:39:24 PM PDT 24
Finished Aug 08 05:39:42 PM PDT 24
Peak memory 211440 kb
Host smart-49d3310f-0a16-4626-910a-a082c4e35494
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668899306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1668899306
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3679598129
Short name T70
Test name
Test status
Simulation time 599366862 ps
CPU time 4.4 seconds
Started Aug 08 06:08:07 PM PDT 24
Finished Aug 08 06:08:12 PM PDT 24
Peak memory 212100 kb
Host smart-c158782e-cf22-4d31-adee-9f8d09161d3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679598129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3679598129
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.710190583
Short name T47
Test name
Test status
Simulation time 31250694139 ps
CPU time 1105.72 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:26:11 PM PDT 24
Peak memory 236648 kb
Host smart-1b2d18e0-d784-4d12-b4af-b4f6b4c7b6ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710190583 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.710190583
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1889663198
Short name T94
Test name
Test status
Simulation time 818877256 ps
CPU time 32.25 seconds
Started Aug 08 05:39:51 PM PDT 24
Finished Aug 08 05:40:23 PM PDT 24
Peak memory 211436 kb
Host smart-f97dcd3a-44eb-451d-b504-5d0875cd5bd7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889663198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1889663198
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4188151572
Short name T54
Test name
Test status
Simulation time 253553234 ps
CPU time 11.43 seconds
Started Aug 08 06:07:42 PM PDT 24
Finished Aug 08 06:07:54 PM PDT 24
Peak memory 212860 kb
Host smart-2b9f876e-1f32-4530-b06f-7ef68aa62753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188151572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4188151572
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.58350224
Short name T25
Test name
Test status
Simulation time 175682866 ps
CPU time 9.55 seconds
Started Aug 08 06:07:53 PM PDT 24
Finished Aug 08 06:08:03 PM PDT 24
Peak memory 213000 kb
Host smart-06294244-44ee-4c65-a50f-bffac9f92a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58350224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.58350224
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3683251434
Short name T122
Test name
Test status
Simulation time 278493924 ps
CPU time 70.89 seconds
Started Aug 08 05:39:30 PM PDT 24
Finished Aug 08 05:40:41 PM PDT 24
Peak memory 213076 kb
Host smart-685696e7-ea77-4019-82f5-7037d9f11b6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683251434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3683251434
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.801644999
Short name T125
Test name
Test status
Simulation time 756023865 ps
CPU time 68.47 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:41:10 PM PDT 24
Peak memory 213064 kb
Host smart-e5a35114-ec31-462a-a1fe-05a3caa39177
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801644999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.801644999
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2547326277
Short name T171
Test name
Test status
Simulation time 2021806390 ps
CPU time 8.72 seconds
Started Aug 08 06:07:46 PM PDT 24
Finished Aug 08 06:07:55 PM PDT 24
Peak memory 212168 kb
Host smart-da0fcfae-e09e-439a-80ed-c7b8abed848d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2547326277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2547326277
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2806408773
Short name T93
Test name
Test status
Simulation time 1037099590 ps
CPU time 4.11 seconds
Started Aug 08 05:39:32 PM PDT 24
Finished Aug 08 05:39:36 PM PDT 24
Peak memory 211296 kb
Host smart-010aa0fd-c454-4e18-876b-4281f79524f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806408773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2806408773
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2397436313
Short name T101
Test name
Test status
Simulation time 313075871 ps
CPU time 6.75 seconds
Started Aug 08 06:08:12 PM PDT 24
Finished Aug 08 06:08:19 PM PDT 24
Peak memory 212172 kb
Host smart-b39556d8-7982-433e-8d01-14ab5dae9554
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397436313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2397436313
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3162060663
Short name T38
Test name
Test status
Simulation time 5132037454 ps
CPU time 97.05 seconds
Started Aug 08 06:07:40 PM PDT 24
Finished Aug 08 06:09:17 PM PDT 24
Peak memory 238532 kb
Host smart-9a4aa5b0-b5ce-40f3-811a-f34b8c80a4b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162060663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3162060663
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.994318856
Short name T46
Test name
Test status
Simulation time 17830766232 ps
CPU time 9662.02 seconds
Started Aug 08 06:07:43 PM PDT 24
Finished Aug 08 08:48:46 PM PDT 24
Peak memory 233612 kb
Host smart-b221bb3b-18b1-4322-8b5f-b3326b5b7bcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994318856 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.994318856
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.410350130
Short name T431
Test name
Test status
Simulation time 518855050 ps
CPU time 5.27 seconds
Started Aug 08 05:39:32 PM PDT 24
Finished Aug 08 05:39:37 PM PDT 24
Peak memory 211240 kb
Host smart-48d1ba08-04e5-4e49-8a9b-e2e3cfd366aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410350130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.410350130
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2108388690
Short name T403
Test name
Test status
Simulation time 321198078 ps
CPU time 4.78 seconds
Started Aug 08 05:39:30 PM PDT 24
Finished Aug 08 05:39:35 PM PDT 24
Peak memory 211260 kb
Host smart-5070a668-f212-4eb7-9473-d17bc95978d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108388690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2108388690
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.152731305
Short name T97
Test name
Test status
Simulation time 91551735 ps
CPU time 7.4 seconds
Started Aug 08 05:39:32 PM PDT 24
Finished Aug 08 05:39:39 PM PDT 24
Peak memory 219236 kb
Host smart-952aa469-8250-4832-8fa3-a739e5b16010
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152731305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.152731305
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2044602785
Short name T407
Test name
Test status
Simulation time 769427344 ps
CPU time 5.14 seconds
Started Aug 08 05:39:31 PM PDT 24
Finished Aug 08 05:39:37 PM PDT 24
Peak memory 219564 kb
Host smart-64d8ba14-ccf5-4d3a-82b9-980d54e6bff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044602785 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2044602785
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3283868792
Short name T348
Test name
Test status
Simulation time 622182592 ps
CPU time 4.97 seconds
Started Aug 08 05:39:31 PM PDT 24
Finished Aug 08 05:39:36 PM PDT 24
Peak memory 211200 kb
Host smart-27f67ffd-be89-43ca-b958-1c6e6e81f7a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283868792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3283868792
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1893497615
Short name T354
Test name
Test status
Simulation time 226077524 ps
CPU time 5.18 seconds
Started Aug 08 05:39:22 PM PDT 24
Finished Aug 08 05:39:27 PM PDT 24
Peak memory 211236 kb
Host smart-76f542c6-e783-4a73-993c-c263f050bc18
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893497615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1893497615
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.368103763
Short name T112
Test name
Test status
Simulation time 300098404 ps
CPU time 4.3 seconds
Started Aug 08 05:39:30 PM PDT 24
Finished Aug 08 05:39:34 PM PDT 24
Peak memory 211384 kb
Host smart-7b2de1c5-a331-4330-8e32-764c435fdfa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368103763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.368103763
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2950221574
Short name T366
Test name
Test status
Simulation time 130912293 ps
CPU time 8.63 seconds
Started Aug 08 05:39:24 PM PDT 24
Finished Aug 08 05:39:33 PM PDT 24
Peak memory 216484 kb
Host smart-7d9db3e1-721d-4871-b3c3-414903580606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950221574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2950221574
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.440496065
Short name T63
Test name
Test status
Simulation time 651650222 ps
CPU time 76.28 seconds
Started Aug 08 05:39:26 PM PDT 24
Finished Aug 08 05:40:43 PM PDT 24
Peak memory 214144 kb
Host smart-b1bd83bd-73cb-40d5-91b2-bba2393ea59a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440496065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.440496065
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3242321481
Short name T95
Test name
Test status
Simulation time 132827310 ps
CPU time 5.02 seconds
Started Aug 08 05:39:33 PM PDT 24
Finished Aug 08 05:39:38 PM PDT 24
Peak memory 218064 kb
Host smart-5255a364-1e91-49f0-b358-bb8e47455899
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242321481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3242321481
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4253211059
Short name T372
Test name
Test status
Simulation time 501468010 ps
CPU time 5.53 seconds
Started Aug 08 05:39:33 PM PDT 24
Finished Aug 08 05:39:38 PM PDT 24
Peak memory 211288 kb
Host smart-03bf7f36-909b-4716-a55f-31f66aaa6f11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253211059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4253211059
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3884450078
Short name T411
Test name
Test status
Simulation time 132163395 ps
CPU time 6.57 seconds
Started Aug 08 05:39:30 PM PDT 24
Finished Aug 08 05:39:36 PM PDT 24
Peak memory 211260 kb
Host smart-59ac3ffb-c5f3-4f50-8dd8-c091154cf5d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884450078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3884450078
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.544467682
Short name T406
Test name
Test status
Simulation time 216058965 ps
CPU time 5.25 seconds
Started Aug 08 05:39:31 PM PDT 24
Finished Aug 08 05:39:36 PM PDT 24
Peak memory 219596 kb
Host smart-8f3b50c5-b108-45cf-899e-47a6e1bd8d8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544467682 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.544467682
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.651636939
Short name T420
Test name
Test status
Simulation time 175322910 ps
CPU time 4.54 seconds
Started Aug 08 05:39:33 PM PDT 24
Finished Aug 08 05:39:37 PM PDT 24
Peak memory 211232 kb
Host smart-d6956927-d43a-430c-890a-57c3a869798b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651636939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.651636939
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2422575632
Short name T365
Test name
Test status
Simulation time 131436815 ps
CPU time 5.19 seconds
Started Aug 08 05:39:31 PM PDT 24
Finished Aug 08 05:39:37 PM PDT 24
Peak memory 211416 kb
Host smart-8fc3a400-4eb5-4394-a447-e46a53789710
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422575632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2422575632
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.916333999
Short name T379
Test name
Test status
Simulation time 252173720 ps
CPU time 4.9 seconds
Started Aug 08 05:39:31 PM PDT 24
Finished Aug 08 05:39:36 PM PDT 24
Peak memory 211180 kb
Host smart-9401d59d-03e7-427a-989b-eb16dabe35de
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916333999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
916333999
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3893866362
Short name T86
Test name
Test status
Simulation time 361507596 ps
CPU time 18.36 seconds
Started Aug 08 05:39:32 PM PDT 24
Finished Aug 08 05:39:50 PM PDT 24
Peak memory 211292 kb
Host smart-f353a30a-6bfa-49ec-8021-492e4c450946
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893866362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3893866362
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.56248777
Short name T65
Test name
Test status
Simulation time 498671787 ps
CPU time 5.29 seconds
Started Aug 08 05:39:30 PM PDT 24
Finished Aug 08 05:39:35 PM PDT 24
Peak memory 211284 kb
Host smart-d07b9bb1-416f-4bcf-97b3-f03535e2f0e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56248777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_same_csr_outstanding.56248777
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1166030662
Short name T394
Test name
Test status
Simulation time 732523726 ps
CPU time 7.56 seconds
Started Aug 08 05:39:30 PM PDT 24
Finished Aug 08 05:39:37 PM PDT 24
Peak memory 216592 kb
Host smart-53eb6aa2-601b-4d1a-aabf-7397a2dc9390
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166030662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1166030662
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1411083506
Short name T346
Test name
Test status
Simulation time 272653068 ps
CPU time 5.68 seconds
Started Aug 08 05:39:50 PM PDT 24
Finished Aug 08 05:39:56 PM PDT 24
Peak memory 219620 kb
Host smart-fa07244d-7602-484e-af61-bf4d7a40c5de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411083506 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1411083506
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3808768877
Short name T395
Test name
Test status
Simulation time 510240804 ps
CPU time 7.73 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:39:57 PM PDT 24
Peak memory 218160 kb
Host smart-a909a2e2-deeb-45e2-ba70-f553b3e1ee76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808768877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3808768877
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.753559111
Short name T396
Test name
Test status
Simulation time 188256037 ps
CPU time 6.01 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:39:55 PM PDT 24
Peak memory 211476 kb
Host smart-ae1ad372-e1a5-4f20-9c91-82c07b77479f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753559111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.753559111
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.250672395
Short name T374
Test name
Test status
Simulation time 138154727 ps
CPU time 9.31 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:39:59 PM PDT 24
Peak memory 216244 kb
Host smart-76917c5c-a582-4819-8a51-ffb19d0ce3a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250672395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.250672395
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3529545256
Short name T123
Test name
Test status
Simulation time 168297087 ps
CPU time 36.32 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:40:26 PM PDT 24
Peak memory 219520 kb
Host smart-dd81029c-dd04-4e43-beba-3c49af6d70ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529545256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3529545256
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2057590001
Short name T342
Test name
Test status
Simulation time 539890543 ps
CPU time 5.42 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:39:55 PM PDT 24
Peak memory 219620 kb
Host smart-341249c3-9365-4833-b994-14ff334d745e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057590001 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2057590001
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2359657827
Short name T357
Test name
Test status
Simulation time 131481963 ps
CPU time 5.02 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:39:54 PM PDT 24
Peak memory 211204 kb
Host smart-ade1e19b-aee7-4957-b876-8b8e896368c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359657827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2359657827
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2393297534
Short name T88
Test name
Test status
Simulation time 2091583365 ps
CPU time 21.55 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:40:11 PM PDT 24
Peak memory 211448 kb
Host smart-ddd37aed-db08-4d45-b27a-4c6986e11302
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393297534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2393297534
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.4240876197
Short name T389
Test name
Test status
Simulation time 518493311 ps
CPU time 5.11 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:39:55 PM PDT 24
Peak memory 219516 kb
Host smart-9ee50c9d-dc15-4e31-bd3f-639e20cc8ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240876197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.4240876197
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2706168875
Short name T377
Test name
Test status
Simulation time 592856547 ps
CPU time 6.92 seconds
Started Aug 08 05:39:48 PM PDT 24
Finished Aug 08 05:39:55 PM PDT 24
Peak memory 216560 kb
Host smart-78190e08-f54f-46eb-8305-83d4eeec88df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706168875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2706168875
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3260757255
Short name T124
Test name
Test status
Simulation time 2366393971 ps
CPU time 38.89 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:40:28 PM PDT 24
Peak memory 211892 kb
Host smart-ca7f64e3-dbcf-4bf7-a568-92b44fdaa3a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260757255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3260757255
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.111514589
Short name T408
Test name
Test status
Simulation time 271323827 ps
CPU time 6 seconds
Started Aug 08 05:39:58 PM PDT 24
Finished Aug 08 05:40:04 PM PDT 24
Peak memory 216380 kb
Host smart-ca23ecaf-7b92-453d-900c-5072e58b8441
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111514589 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.111514589
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.513487521
Short name T345
Test name
Test status
Simulation time 956636428 ps
CPU time 5.02 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:39:54 PM PDT 24
Peak memory 211284 kb
Host smart-849e672f-8185-4451-9d94-2bda73d448f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513487521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.513487521
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2124681931
Short name T363
Test name
Test status
Simulation time 380399949 ps
CPU time 19.22 seconds
Started Aug 08 05:39:50 PM PDT 24
Finished Aug 08 05:40:10 PM PDT 24
Peak memory 211340 kb
Host smart-4be289c2-50db-4440-b98a-b7fbb327668a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124681931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2124681931
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.589834962
Short name T77
Test name
Test status
Simulation time 592197176 ps
CPU time 4.29 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:40:04 PM PDT 24
Peak memory 218632 kb
Host smart-867b2747-602b-48e9-a872-68839cc51602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589834962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.589834962
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2599994140
Short name T416
Test name
Test status
Simulation time 132613386 ps
CPU time 9.08 seconds
Started Aug 08 05:39:48 PM PDT 24
Finished Aug 08 05:39:58 PM PDT 24
Peak memory 219592 kb
Host smart-4cbf8914-6f7f-4743-974a-a920239c1f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599994140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2599994140
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2684862508
Short name T422
Test name
Test status
Simulation time 171657701 ps
CPU time 37.06 seconds
Started Aug 08 05:39:50 PM PDT 24
Finished Aug 08 05:40:27 PM PDT 24
Peak memory 211592 kb
Host smart-0d24db63-c5e2-4950-94ef-8e637e4c22d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684862508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2684862508
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3822676868
Short name T421
Test name
Test status
Simulation time 264421712 ps
CPU time 5.28 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:40:07 PM PDT 24
Peak memory 213348 kb
Host smart-a107f25b-b91e-45d4-87c1-65a0af747eb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822676868 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3822676868
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.921596925
Short name T79
Test name
Test status
Simulation time 500794013 ps
CPU time 5.05 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:40:06 PM PDT 24
Peak memory 211176 kb
Host smart-8789dc78-2b2b-471e-8dd1-9d05307d179b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921596925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.921596925
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.829735829
Short name T113
Test name
Test status
Simulation time 1489280641 ps
CPU time 18.13 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:40:19 PM PDT 24
Peak memory 211384 kb
Host smart-5bda3325-b808-4e20-9ca0-1ee1b30db18d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829735829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.829735829
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3441137166
Short name T391
Test name
Test status
Simulation time 1040259390 ps
CPU time 5.22 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:40:06 PM PDT 24
Peak memory 218696 kb
Host smart-cffce86f-172f-4838-83e4-9a7902abbfc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441137166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3441137166
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2353860367
Short name T369
Test name
Test status
Simulation time 543838966 ps
CPU time 9.53 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:09 PM PDT 24
Peak memory 219592 kb
Host smart-a83a13e4-1c4f-47fd-91b2-1ad1850e0c1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353860367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2353860367
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.505193591
Short name T128
Test name
Test status
Simulation time 287562695 ps
CPU time 70.38 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:41:10 PM PDT 24
Peak memory 213020 kb
Host smart-780cb658-8059-4be6-88ef-46ccf9942d17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505193591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.505193591
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3917779024
Short name T355
Test name
Test status
Simulation time 194170551 ps
CPU time 5.55 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:06 PM PDT 24
Peak memory 219496 kb
Host smart-5a658cb6-f817-4bdb-8241-44758f7f9eb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917779024 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3917779024
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3866009528
Short name T353
Test name
Test status
Simulation time 86326457 ps
CPU time 4.35 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:04 PM PDT 24
Peak memory 211236 kb
Host smart-b8d10144-6c9e-464b-a348-77035eb3cba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866009528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3866009528
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2174301000
Short name T347
Test name
Test status
Simulation time 363066884 ps
CPU time 18.38 seconds
Started Aug 08 05:39:58 PM PDT 24
Finished Aug 08 05:40:17 PM PDT 24
Peak memory 211416 kb
Host smart-e8859455-6877-438e-bae8-8bcdeeee9081
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174301000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2174301000
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.503103791
Short name T397
Test name
Test status
Simulation time 255016975 ps
CPU time 5.24 seconds
Started Aug 08 05:39:57 PM PDT 24
Finished Aug 08 05:40:02 PM PDT 24
Peak memory 211328 kb
Host smart-39629ff9-a204-41d3-a441-00ee2bc56857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503103791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.503103791
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1195489953
Short name T333
Test name
Test status
Simulation time 498312608 ps
CPU time 8.8 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:40:08 PM PDT 24
Peak memory 216564 kb
Host smart-f5771f9e-fb34-4eb8-894e-8881a9c5033e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195489953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1195489953
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4204415913
Short name T405
Test name
Test status
Simulation time 3456040368 ps
CPU time 37.29 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:40:36 PM PDT 24
Peak memory 219492 kb
Host smart-440c3f76-70b3-4378-84b2-29a988b7f6d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204415913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4204415913
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2331359496
Short name T383
Test name
Test status
Simulation time 139772790 ps
CPU time 6.22 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:40:06 PM PDT 24
Peak memory 219648 kb
Host smart-663c5605-adc9-40a5-8ced-00a99fbe1f34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331359496 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2331359496
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3465679951
Short name T87
Test name
Test status
Simulation time 752919582 ps
CPU time 4.43 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:40:06 PM PDT 24
Peak memory 219360 kb
Host smart-1b90142f-9be3-47d8-b68a-3dceb4a1765a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465679951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3465679951
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1001698281
Short name T76
Test name
Test status
Simulation time 378558925 ps
CPU time 18.65 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:40:20 PM PDT 24
Peak memory 211592 kb
Host smart-3fb801fa-7f4c-41e9-8607-e1027cb2a8ca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001698281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1001698281
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1928418647
Short name T430
Test name
Test status
Simulation time 142534943 ps
CPU time 7.12 seconds
Started Aug 08 05:40:02 PM PDT 24
Finished Aug 08 05:40:09 PM PDT 24
Peak memory 211344 kb
Host smart-ba1dd1c8-e490-4684-a886-d5f13553c7fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928418647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1928418647
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1985485646
Short name T340
Test name
Test status
Simulation time 136755115 ps
CPU time 8.85 seconds
Started Aug 08 05:40:03 PM PDT 24
Finished Aug 08 05:40:12 PM PDT 24
Peak memory 219524 kb
Host smart-3c7cccd7-035f-4c48-83ec-25628e74dfcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985485646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1985485646
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1719452133
Short name T388
Test name
Test status
Simulation time 531157531 ps
CPU time 36.41 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:36 PM PDT 24
Peak memory 211884 kb
Host smart-c98ee430-6448-47db-a773-06fefb008665
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719452133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1719452133
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2920943183
Short name T361
Test name
Test status
Simulation time 590749480 ps
CPU time 5.91 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:06 PM PDT 24
Peak memory 219776 kb
Host smart-fd14b552-658d-45e9-9ad3-4f5b5fa2c519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920943183 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2920943183
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3746842898
Short name T349
Test name
Test status
Simulation time 90818323 ps
CPU time 4.29 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:40:04 PM PDT 24
Peak memory 217904 kb
Host smart-5295a605-7801-4e11-8145-3bcbbd5927bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746842898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3746842898
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1730937592
Short name T415
Test name
Test status
Simulation time 1579939247 ps
CPU time 32.6 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:40:32 PM PDT 24
Peak memory 211404 kb
Host smart-8a73690b-12c5-476a-a204-d45a497d6d12
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730937592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1730937592
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3830473615
Short name T66
Test name
Test status
Simulation time 89095675 ps
CPU time 4.33 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:05 PM PDT 24
Peak memory 218664 kb
Host smart-92aa0cc6-aca6-4f9e-a99d-435878c82f40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830473615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3830473615
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.4164214871
Short name T351
Test name
Test status
Simulation time 169557927 ps
CPU time 8.28 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:40:07 PM PDT 24
Peak memory 216500 kb
Host smart-7947bf4f-f9ba-4389-a036-5eba1842313b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164214871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.4164214871
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3097900614
Short name T119
Test name
Test status
Simulation time 551193802 ps
CPU time 70.32 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:41:12 PM PDT 24
Peak memory 212952 kb
Host smart-42c20721-bd04-485f-8d51-72580f4e6e15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097900614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3097900614
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2544626482
Short name T380
Test name
Test status
Simulation time 219065567 ps
CPU time 5.75 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:05 PM PDT 24
Peak memory 219440 kb
Host smart-dcc7ef43-2e46-42ba-affe-669c23448b94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544626482 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2544626482
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1947476154
Short name T343
Test name
Test status
Simulation time 91911631 ps
CPU time 4.34 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:04 PM PDT 24
Peak memory 211204 kb
Host smart-0636f4c2-ac2f-43c6-ad2f-a4183f5fcea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947476154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1947476154
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2296656167
Short name T362
Test name
Test status
Simulation time 1043375457 ps
CPU time 22.33 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:40:22 PM PDT 24
Peak memory 211424 kb
Host smart-e2f25c84-0de1-41d1-97b3-a82d0aee2b3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296656167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2296656167
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1201581052
Short name T399
Test name
Test status
Simulation time 132264612 ps
CPU time 5.14 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:40:04 PM PDT 24
Peak memory 218988 kb
Host smart-cb5b0ee1-c11b-4c1b-a9f2-f59f5d940654
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201581052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1201581052
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2694146977
Short name T375
Test name
Test status
Simulation time 346411405 ps
CPU time 6.4 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:07 PM PDT 24
Peak memory 215232 kb
Host smart-9d62b946-36be-4e98-a792-f75bd9156b22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694146977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2694146977
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.779348107
Short name T378
Test name
Test status
Simulation time 212561760 ps
CPU time 37.84 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:40:39 PM PDT 24
Peak memory 213100 kb
Host smart-738e5db0-077b-4ea1-b3ed-72cad6f680fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779348107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.779348107
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1855261487
Short name T370
Test name
Test status
Simulation time 153695002 ps
CPU time 6.26 seconds
Started Aug 08 05:39:58 PM PDT 24
Finished Aug 08 05:40:04 PM PDT 24
Peak memory 216436 kb
Host smart-10d8a605-0295-4eb4-811a-8aa141c76cde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855261487 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1855261487
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.380850331
Short name T350
Test name
Test status
Simulation time 639067765 ps
CPU time 4.29 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:04 PM PDT 24
Peak memory 211204 kb
Host smart-cec9ffad-5ae1-4b93-b091-f13a2e1f2934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380850331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.380850331
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.802206944
Short name T414
Test name
Test status
Simulation time 2087407673 ps
CPU time 21.84 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:40:23 PM PDT 24
Peak memory 211420 kb
Host smart-d001af23-f08d-48a9-94f4-e4f495a80183
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802206944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_pa
ssthru_mem_tl_intg_err.802206944
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1060650124
Short name T358
Test name
Test status
Simulation time 380833050 ps
CPU time 4.21 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:05 PM PDT 24
Peak memory 211380 kb
Host smart-3374ba7c-79b7-49dd-9170-f887e4eeec43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060650124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1060650124
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1064863074
Short name T337
Test name
Test status
Simulation time 559213979 ps
CPU time 7.64 seconds
Started Aug 08 05:39:59 PM PDT 24
Finished Aug 08 05:40:07 PM PDT 24
Peak memory 219644 kb
Host smart-244d3665-274d-4934-acec-3ff6ac0a0f97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064863074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1064863074
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2521346961
Short name T61
Test name
Test status
Simulation time 578182381 ps
CPU time 36.51 seconds
Started Aug 08 05:39:58 PM PDT 24
Finished Aug 08 05:40:35 PM PDT 24
Peak memory 212080 kb
Host smart-f424d736-8c34-4b3d-8fa7-97445cf267db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521346961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2521346961
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.478975417
Short name T341
Test name
Test status
Simulation time 135921660 ps
CPU time 5.6 seconds
Started Aug 08 05:40:13 PM PDT 24
Finished Aug 08 05:40:19 PM PDT 24
Peak memory 214244 kb
Host smart-ab928da6-61eb-421e-bcd1-5897e7392584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478975417 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.478975417
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3618961301
Short name T413
Test name
Test status
Simulation time 274113107 ps
CPU time 5.05 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:06 PM PDT 24
Peak memory 218340 kb
Host smart-cb099199-7fbc-4fae-9307-f73e35936678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618961301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3618961301
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4115223813
Short name T385
Test name
Test status
Simulation time 1103048259 ps
CPU time 27.02 seconds
Started Aug 08 05:40:01 PM PDT 24
Finished Aug 08 05:40:28 PM PDT 24
Peak memory 211300 kb
Host smart-007dd7de-43ec-4e1f-8a6c-0c1666936328
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115223813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4115223813
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3800664300
Short name T423
Test name
Test status
Simulation time 544119396 ps
CPU time 5.24 seconds
Started Aug 08 05:40:11 PM PDT 24
Finished Aug 08 05:40:17 PM PDT 24
Peak memory 218948 kb
Host smart-3439c967-dd23-4596-a5f1-73b5c9c6f26c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800664300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3800664300
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4112128981
Short name T364
Test name
Test status
Simulation time 155463377 ps
CPU time 10.48 seconds
Started Aug 08 05:40:00 PM PDT 24
Finished Aug 08 05:40:11 PM PDT 24
Peak memory 216556 kb
Host smart-56ad4014-fddb-4874-909f-f6c8efaf78c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112128981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4112128981
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3820103787
Short name T115
Test name
Test status
Simulation time 335405636 ps
CPU time 4.42 seconds
Started Aug 08 05:39:32 PM PDT 24
Finished Aug 08 05:39:36 PM PDT 24
Peak memory 211500 kb
Host smart-366cdf78-ee82-4d5b-8287-1b1f7c788c7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820103787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3820103787
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2412922909
Short name T384
Test name
Test status
Simulation time 538354781 ps
CPU time 5.19 seconds
Started Aug 08 05:39:30 PM PDT 24
Finished Aug 08 05:39:35 PM PDT 24
Peak memory 211236 kb
Host smart-fb085269-46cd-4794-be17-72d05e9f0f37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412922909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2412922909
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3024358180
Short name T417
Test name
Test status
Simulation time 131238472 ps
CPU time 8.24 seconds
Started Aug 08 05:39:31 PM PDT 24
Finished Aug 08 05:39:39 PM PDT 24
Peak memory 219364 kb
Host smart-25c41044-f5f7-436a-a4e1-523917383799
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024358180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3024358180
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1743784292
Short name T360
Test name
Test status
Simulation time 362220201 ps
CPU time 5.02 seconds
Started Aug 08 05:39:29 PM PDT 24
Finished Aug 08 05:39:34 PM PDT 24
Peak memory 215872 kb
Host smart-473a1c48-8695-47ad-be0c-2043f55fecf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743784292 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1743784292
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2365276299
Short name T96
Test name
Test status
Simulation time 87661160 ps
CPU time 4.19 seconds
Started Aug 08 05:39:31 PM PDT 24
Finished Aug 08 05:39:35 PM PDT 24
Peak memory 211160 kb
Host smart-6c04af69-12c4-4e8b-b8bb-96e49a054cc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365276299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2365276299
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1914504153
Short name T402
Test name
Test status
Simulation time 88119351 ps
CPU time 4.13 seconds
Started Aug 08 05:39:29 PM PDT 24
Finished Aug 08 05:39:34 PM PDT 24
Peak memory 211244 kb
Host smart-86c491d9-5c58-4c61-90ad-078ccd3a583f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914504153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1914504153
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3766861494
Short name T428
Test name
Test status
Simulation time 239861908 ps
CPU time 4.93 seconds
Started Aug 08 05:39:30 PM PDT 24
Finished Aug 08 05:39:35 PM PDT 24
Peak memory 211116 kb
Host smart-56bc32e7-16ca-4e49-8094-dffadb602ee7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766861494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3766861494
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.298220371
Short name T387
Test name
Test status
Simulation time 374533064 ps
CPU time 19.37 seconds
Started Aug 08 05:39:30 PM PDT 24
Finished Aug 08 05:39:50 PM PDT 24
Peak memory 211424 kb
Host smart-33068e2f-f286-4870-aede-18cc5cc56e97
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298220371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pas
sthru_mem_tl_intg_err.298220371
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.658729581
Short name T111
Test name
Test status
Simulation time 173147205 ps
CPU time 4.32 seconds
Started Aug 08 05:39:31 PM PDT 24
Finished Aug 08 05:39:36 PM PDT 24
Peak memory 211292 kb
Host smart-8e627334-2f03-4546-bed3-f2337c67f110
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658729581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ct
rl_same_csr_outstanding.658729581
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2778399870
Short name T382
Test name
Test status
Simulation time 474418993 ps
CPU time 9.32 seconds
Started Aug 08 05:39:32 PM PDT 24
Finished Aug 08 05:39:41 PM PDT 24
Peak memory 219560 kb
Host smart-64e3e944-655a-45e4-95a0-1a619417abbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778399870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2778399870
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2703112219
Short name T121
Test name
Test status
Simulation time 873419148 ps
CPU time 68.54 seconds
Started Aug 08 05:39:30 PM PDT 24
Finished Aug 08 05:40:39 PM PDT 24
Peak memory 213016 kb
Host smart-a3f5f110-903f-48aa-a8ce-a91072aee653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703112219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2703112219
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.483119931
Short name T381
Test name
Test status
Simulation time 1771302112 ps
CPU time 5.11 seconds
Started Aug 08 05:39:40 PM PDT 24
Finished Aug 08 05:39:45 PM PDT 24
Peak memory 218292 kb
Host smart-1e1246fc-c015-4e1f-bacb-0f6902568d7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483119931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alias
ing.483119931
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1650825536
Short name T367
Test name
Test status
Simulation time 350178888 ps
CPU time 4.36 seconds
Started Aug 08 05:39:42 PM PDT 24
Finished Aug 08 05:39:47 PM PDT 24
Peak memory 219432 kb
Host smart-84da021f-498f-4c2b-a67c-2091558c6fe4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650825536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1650825536
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.4140877371
Short name T85
Test name
Test status
Simulation time 94912304 ps
CPU time 5.83 seconds
Started Aug 08 05:39:40 PM PDT 24
Finished Aug 08 05:39:46 PM PDT 24
Peak memory 211296 kb
Host smart-2e5e5b4a-5101-4048-b2f2-ea080238043f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140877371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.4140877371
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3268556982
Short name T426
Test name
Test status
Simulation time 105042122 ps
CPU time 5.09 seconds
Started Aug 08 05:39:41 PM PDT 24
Finished Aug 08 05:39:46 PM PDT 24
Peak memory 215776 kb
Host smart-86a79ce6-5a66-4349-bebb-6e2600b6bd7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268556982 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3268556982
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3592330311
Short name T398
Test name
Test status
Simulation time 963732511 ps
CPU time 4.94 seconds
Started Aug 08 05:39:42 PM PDT 24
Finished Aug 08 05:39:47 PM PDT 24
Peak memory 211084 kb
Host smart-08ee7a65-d9c5-47df-9765-a4de9c82488f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592330311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3592330311
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4265843089
Short name T339
Test name
Test status
Simulation time 332864276 ps
CPU time 4.12 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:39:48 PM PDT 24
Peak memory 211240 kb
Host smart-16e02a93-7b6e-4eb0-af09-70cbed28171d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265843089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4265843089
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1509057749
Short name T332
Test name
Test status
Simulation time 127535771 ps
CPU time 4.94 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:39:49 PM PDT 24
Peak memory 211208 kb
Host smart-17eb4ed9-b62a-4390-b726-bd860661674b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509057749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1509057749
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.393703643
Short name T92
Test name
Test status
Simulation time 814504532 ps
CPU time 32.56 seconds
Started Aug 08 05:39:31 PM PDT 24
Finished Aug 08 05:40:03 PM PDT 24
Peak memory 211388 kb
Host smart-2fd98c57-659b-4a5a-a17f-ee6a16e98226
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393703643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.393703643
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1234206225
Short name T64
Test name
Test status
Simulation time 137754870 ps
CPU time 6.75 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:39:51 PM PDT 24
Peak memory 211568 kb
Host smart-1e27e759-8ea9-4b50-9341-fd347858ac8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234206225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1234206225
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1284853177
Short name T390
Test name
Test status
Simulation time 1135528562 ps
CPU time 7.22 seconds
Started Aug 08 05:39:32 PM PDT 24
Finished Aug 08 05:39:39 PM PDT 24
Peak memory 219544 kb
Host smart-c666fd70-54f5-4a17-a546-06db16210d77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284853177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1284853177
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2419923323
Short name T91
Test name
Test status
Simulation time 248755072 ps
CPU time 5.12 seconds
Started Aug 08 05:39:40 PM PDT 24
Finished Aug 08 05:39:45 PM PDT 24
Peak memory 218220 kb
Host smart-41f85d01-8731-4779-bf50-20402bf7f62f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419923323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2419923323
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1350216630
Short name T419
Test name
Test status
Simulation time 416317628 ps
CPU time 5.3 seconds
Started Aug 08 05:39:41 PM PDT 24
Finished Aug 08 05:39:46 PM PDT 24
Peak memory 211284 kb
Host smart-58a17c5c-c340-4412-9142-ecf3ae6015e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350216630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1350216630
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3879294503
Short name T98
Test name
Test status
Simulation time 94151282 ps
CPU time 7.44 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:39:52 PM PDT 24
Peak memory 219176 kb
Host smart-ca9ea0bf-be4f-4707-a097-a1184d1f82ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879294503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3879294503
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2456737875
Short name T336
Test name
Test status
Simulation time 204091762 ps
CPU time 4.76 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:39:49 PM PDT 24
Peak memory 215936 kb
Host smart-3616081f-b2e8-4515-8b5c-6d7407c03115
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456737875 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2456737875
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.534687576
Short name T412
Test name
Test status
Simulation time 336457222 ps
CPU time 4.1 seconds
Started Aug 08 05:39:42 PM PDT 24
Finished Aug 08 05:39:46 PM PDT 24
Peak memory 210976 kb
Host smart-c9b915ca-9f31-4298-b5a4-63dcaa4fe011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534687576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.534687576
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3009183847
Short name T373
Test name
Test status
Simulation time 290868432 ps
CPU time 4.95 seconds
Started Aug 08 05:39:39 PM PDT 24
Finished Aug 08 05:39:44 PM PDT 24
Peak memory 211168 kb
Host smart-716cac21-d4ba-4eca-b8e6-04ba41b2ebd3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009183847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3009183847
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2532830517
Short name T409
Test name
Test status
Simulation time 116133810 ps
CPU time 4.04 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:39:49 PM PDT 24
Peak memory 211248 kb
Host smart-6329e5b9-abf6-48a7-87bb-7eaddfe1b26f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532830517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2532830517
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3647151554
Short name T427
Test name
Test status
Simulation time 373664268 ps
CPU time 19.74 seconds
Started Aug 08 05:39:43 PM PDT 24
Finished Aug 08 05:40:03 PM PDT 24
Peak memory 211452 kb
Host smart-30e657db-8ef0-4b58-a586-d25f797cb427
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647151554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3647151554
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3780207862
Short name T344
Test name
Test status
Simulation time 132622103 ps
CPU time 5.31 seconds
Started Aug 08 05:39:41 PM PDT 24
Finished Aug 08 05:39:46 PM PDT 24
Peak memory 211332 kb
Host smart-2bdb34a3-b06a-49e6-a422-811109769f2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780207862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3780207862
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.62193577
Short name T371
Test name
Test status
Simulation time 438798049 ps
CPU time 7.17 seconds
Started Aug 08 05:39:39 PM PDT 24
Finished Aug 08 05:39:47 PM PDT 24
Peak memory 215252 kb
Host smart-5f055630-3775-4e45-98a5-05ff06f2c896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62193577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.62193577
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1215486956
Short name T376
Test name
Test status
Simulation time 596213042 ps
CPU time 36.59 seconds
Started Aug 08 05:39:42 PM PDT 24
Finished Aug 08 05:40:19 PM PDT 24
Peak memory 212996 kb
Host smart-159d179f-c8c2-4f66-99a8-85b8133da348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215486956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1215486956
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1649578949
Short name T418
Test name
Test status
Simulation time 147251373 ps
CPU time 5.93 seconds
Started Aug 08 05:39:42 PM PDT 24
Finished Aug 08 05:39:48 PM PDT 24
Peak memory 215828 kb
Host smart-0713ab77-a434-4563-95e0-3923f8802aee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649578949 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1649578949
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1882651060
Short name T74
Test name
Test status
Simulation time 85858290 ps
CPU time 4.28 seconds
Started Aug 08 05:39:41 PM PDT 24
Finished Aug 08 05:39:45 PM PDT 24
Peak memory 210820 kb
Host smart-14508aef-f56c-4c61-8c0f-6c6e25368a05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882651060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1882651060
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3329475092
Short name T90
Test name
Test status
Simulation time 797585988 ps
CPU time 32.67 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:40:17 PM PDT 24
Peak memory 212448 kb
Host smart-8b6b864a-bad6-4703-b19f-53a74ecba1ba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329475092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3329475092
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2530856844
Short name T114
Test name
Test status
Simulation time 85851372 ps
CPU time 4.24 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:39:48 PM PDT 24
Peak memory 211368 kb
Host smart-1c2df64a-9002-4f03-814b-0bbc6921e3c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530856844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2530856844
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1107008033
Short name T401
Test name
Test status
Simulation time 128200158 ps
CPU time 9.08 seconds
Started Aug 08 05:39:40 PM PDT 24
Finished Aug 08 05:39:49 PM PDT 24
Peak memory 216580 kb
Host smart-2e3f6f3b-0b6e-478f-8581-7bc7d5804a60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107008033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1107008033
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1617436353
Short name T410
Test name
Test status
Simulation time 155947614 ps
CPU time 36.99 seconds
Started Aug 08 05:39:43 PM PDT 24
Finished Aug 08 05:40:20 PM PDT 24
Peak memory 211912 kb
Host smart-223edfb7-86df-480a-8453-c01ce9eec4df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617436353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1617436353
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1598328349
Short name T334
Test name
Test status
Simulation time 511399513 ps
CPU time 5.98 seconds
Started Aug 08 05:39:42 PM PDT 24
Finished Aug 08 05:39:48 PM PDT 24
Peak memory 219568 kb
Host smart-149d7616-f00f-4de8-8a47-4e6ee3709f81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598328349 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1598328349
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3857469119
Short name T89
Test name
Test status
Simulation time 86172999 ps
CPU time 4.22 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:39:48 PM PDT 24
Peak memory 219452 kb
Host smart-410dea40-41c1-431a-bcf4-f14aebac6432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857469119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3857469119
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.47721515
Short name T359
Test name
Test status
Simulation time 1866049372 ps
CPU time 22.18 seconds
Started Aug 08 05:39:41 PM PDT 24
Finished Aug 08 05:40:03 PM PDT 24
Peak memory 211356 kb
Host smart-7af1b71a-c8b9-4f4c-89f6-a6c089818c3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47721515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pass
thru_mem_tl_intg_err.47721515
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1935823753
Short name T78
Test name
Test status
Simulation time 2640958866 ps
CPU time 6.93 seconds
Started Aug 08 05:39:43 PM PDT 24
Finished Aug 08 05:39:50 PM PDT 24
Peak memory 218768 kb
Host smart-929808af-07c3-493f-b576-a5e8f4e2b6df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935823753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1935823753
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1657550446
Short name T404
Test name
Test status
Simulation time 85462798 ps
CPU time 8.04 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:39:53 PM PDT 24
Peak memory 219592 kb
Host smart-b3d8bf22-6249-40b1-91df-854f83695819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657550446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1657550446
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2250787525
Short name T126
Test name
Test status
Simulation time 168934937 ps
CPU time 36.87 seconds
Started Aug 08 05:39:39 PM PDT 24
Finished Aug 08 05:40:16 PM PDT 24
Peak memory 211976 kb
Host smart-c4eb3dc5-9670-45e7-b8fb-dd6733385bda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250787525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2250787525
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2489032800
Short name T386
Test name
Test status
Simulation time 482363834 ps
CPU time 5.38 seconds
Started Aug 08 05:39:40 PM PDT 24
Finished Aug 08 05:39:46 PM PDT 24
Peak memory 219584 kb
Host smart-ee8c8d51-1b88-49dd-9317-dbaa24a33ad6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489032800 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2489032800
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.4082870203
Short name T392
Test name
Test status
Simulation time 250164985 ps
CPU time 5.03 seconds
Started Aug 08 05:39:41 PM PDT 24
Finished Aug 08 05:39:46 PM PDT 24
Peak memory 211356 kb
Host smart-4bf98a7e-1288-4f55-8031-ab0f4f0f317a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082870203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.4082870203
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2517365262
Short name T99
Test name
Test status
Simulation time 1115426199 ps
CPU time 21.64 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:40:06 PM PDT 24
Peak memory 211348 kb
Host smart-c22d974b-e32d-410c-b694-0d88cabb2b2a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517365262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2517365262
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2626976189
Short name T356
Test name
Test status
Simulation time 126335055 ps
CPU time 5.01 seconds
Started Aug 08 05:39:44 PM PDT 24
Finished Aug 08 05:39:49 PM PDT 24
Peak memory 218124 kb
Host smart-15c9f96c-9efa-4732-94eb-364c4ef298a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626976189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2626976189
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1882205122
Short name T368
Test name
Test status
Simulation time 2033551110 ps
CPU time 10.01 seconds
Started Aug 08 05:39:41 PM PDT 24
Finished Aug 08 05:39:51 PM PDT 24
Peak memory 219652 kb
Host smart-2fddc17e-69c3-4bac-bf8c-04b26070f21f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882205122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1882205122
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1935800917
Short name T127
Test name
Test status
Simulation time 248014341 ps
CPU time 71.19 seconds
Started Aug 08 05:39:43 PM PDT 24
Finished Aug 08 05:40:54 PM PDT 24
Peak memory 213000 kb
Host smart-b6937859-0592-4b75-9f99-20e70a5de8f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935800917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1935800917
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.621848280
Short name T352
Test name
Test status
Simulation time 422999512 ps
CPU time 5.6 seconds
Started Aug 08 05:39:50 PM PDT 24
Finished Aug 08 05:39:56 PM PDT 24
Peak memory 216480 kb
Host smart-9a9bf684-95bf-47d4-8819-35e2a8ea6d3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621848280 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.621848280
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.4043559028
Short name T429
Test name
Test status
Simulation time 496023825 ps
CPU time 7.38 seconds
Started Aug 08 05:39:50 PM PDT 24
Finished Aug 08 05:39:58 PM PDT 24
Peak memory 211212 kb
Host smart-c75cfcde-a11a-4aee-98a2-469c5d1d1934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043559028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.4043559028
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.786756135
Short name T73
Test name
Test status
Simulation time 1072677339 ps
CPU time 27.68 seconds
Started Aug 08 05:39:40 PM PDT 24
Finished Aug 08 05:40:08 PM PDT 24
Peak memory 211376 kb
Host smart-a2153bc6-430e-49bf-9433-4b46642fb472
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786756135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.786756135
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1281739748
Short name T393
Test name
Test status
Simulation time 96724767 ps
CPU time 6.21 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:39:56 PM PDT 24
Peak memory 211284 kb
Host smart-c66b97c8-e73b-4fb1-957d-475ef3e13729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281739748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1281739748
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.429867472
Short name T335
Test name
Test status
Simulation time 135131921 ps
CPU time 6.11 seconds
Started Aug 08 05:39:41 PM PDT 24
Finished Aug 08 05:39:47 PM PDT 24
Peak memory 216232 kb
Host smart-eb2ecbec-1f14-4fe0-9bb9-1492e93cde44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429867472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.429867472
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3565749031
Short name T425
Test name
Test status
Simulation time 185895026 ps
CPU time 37.37 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:40:27 PM PDT 24
Peak memory 219416 kb
Host smart-93061588-2edd-4d62-8a91-02db46e89321
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565749031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3565749031
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.209951
Short name T424
Test name
Test status
Simulation time 252253474 ps
CPU time 5.49 seconds
Started Aug 08 05:39:49 PM PDT 24
Finished Aug 08 05:39:55 PM PDT 24
Peak memory 215448 kb
Host smart-58ab1d7a-b860-4196-934d-2433ac0602ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209951 -assert nopostproc +UVM_TESTNAME=rom
_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.209951
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.694114437
Short name T338
Test name
Test status
Simulation time 520890430 ps
CPU time 4.94 seconds
Started Aug 08 05:39:50 PM PDT 24
Finished Aug 08 05:39:56 PM PDT 24
Peak memory 218216 kb
Host smart-a93399e6-87be-4c68-ae0a-bffa6274e620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694114437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.694114437
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1877473221
Short name T100
Test name
Test status
Simulation time 1625666931 ps
CPU time 31.68 seconds
Started Aug 08 05:39:48 PM PDT 24
Finished Aug 08 05:40:20 PM PDT 24
Peak memory 211436 kb
Host smart-e16aab90-e454-402f-9590-c2ba484905dc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877473221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1877473221
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3029572922
Short name T432
Test name
Test status
Simulation time 130440950 ps
CPU time 5.34 seconds
Started Aug 08 05:39:50 PM PDT 24
Finished Aug 08 05:39:56 PM PDT 24
Peak memory 211424 kb
Host smart-e5fa8886-ee86-4fa2-9088-404a3ccae071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029572922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3029572922
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1813873241
Short name T400
Test name
Test status
Simulation time 499050250 ps
CPU time 9.76 seconds
Started Aug 08 05:39:50 PM PDT 24
Finished Aug 08 05:40:00 PM PDT 24
Peak memory 216720 kb
Host smart-d962dfc4-5488-487f-976b-593ecdc93e46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813873241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1813873241
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1602375027
Short name T327
Test name
Test status
Simulation time 132261624 ps
CPU time 5.15 seconds
Started Aug 08 06:07:30 PM PDT 24
Finished Aug 08 06:07:36 PM PDT 24
Peak memory 212264 kb
Host smart-5f415171-4050-4f02-9553-07963aba1695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602375027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1602375027
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3593991887
Short name T237
Test name
Test status
Simulation time 5963833804 ps
CPU time 82.83 seconds
Started Aug 08 06:07:40 PM PDT 24
Finished Aug 08 06:09:03 PM PDT 24
Peak memory 227940 kb
Host smart-5b428e7c-bd99-482e-af13-7bc81513291d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593991887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3593991887
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.729431548
Short name T173
Test name
Test status
Simulation time 176472238 ps
CPU time 9.53 seconds
Started Aug 08 06:07:46 PM PDT 24
Finished Aug 08 06:07:56 PM PDT 24
Peak memory 212972 kb
Host smart-957ba8d1-4d0a-43d9-bd24-da34ca7348a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729431548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.729431548
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1672447763
Short name T314
Test name
Test status
Simulation time 500338426 ps
CPU time 8.56 seconds
Started Aug 08 06:07:31 PM PDT 24
Finished Aug 08 06:07:40 PM PDT 24
Peak memory 212184 kb
Host smart-e4702e1c-78cf-44a9-ade6-e785c4d8fc73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672447763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1672447763
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1118935026
Short name T27
Test name
Test status
Simulation time 329239442 ps
CPU time 103.84 seconds
Started Aug 08 06:07:51 PM PDT 24
Finished Aug 08 06:09:35 PM PDT 24
Peak memory 236952 kb
Host smart-429fdb10-9e43-495f-8d53-286003891c4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118935026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1118935026
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2017164748
Short name T222
Test name
Test status
Simulation time 1013990248 ps
CPU time 6.24 seconds
Started Aug 08 06:07:39 PM PDT 24
Finished Aug 08 06:07:45 PM PDT 24
Peak memory 212188 kb
Host smart-f012bd41-ee3d-4333-ae36-de1fb6184d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017164748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2017164748
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4081051669
Short name T134
Test name
Test status
Simulation time 811588095 ps
CPU time 10.35 seconds
Started Aug 08 06:07:39 PM PDT 24
Finished Aug 08 06:07:50 PM PDT 24
Peak memory 215312 kb
Host smart-094f4497-c160-4ede-8599-3c3077df1b4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081051669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4081051669
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1618054463
Short name T274
Test name
Test status
Simulation time 519693927 ps
CPU time 5.12 seconds
Started Aug 08 06:07:40 PM PDT 24
Finished Aug 08 06:07:46 PM PDT 24
Peak memory 212068 kb
Host smart-e39d1fa6-b44f-441d-98a8-6c69c5784f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618054463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1618054463
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3972012004
Short name T7
Test name
Test status
Simulation time 532542925 ps
CPU time 6.14 seconds
Started Aug 08 06:07:43 PM PDT 24
Finished Aug 08 06:07:49 PM PDT 24
Peak memory 212232 kb
Host smart-a13b76c7-c129-4273-8bca-5fb24d566769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972012004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3972012004
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.967051516
Short name T208
Test name
Test status
Simulation time 102069429 ps
CPU time 5.43 seconds
Started Aug 08 06:07:37 PM PDT 24
Finished Aug 08 06:07:43 PM PDT 24
Peak memory 212284 kb
Host smart-4a965a10-2147-4539-a535-3171f430f436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967051516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.967051516
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1144653534
Short name T213
Test name
Test status
Simulation time 795233631 ps
CPU time 8.26 seconds
Started Aug 08 06:07:44 PM PDT 24
Finished Aug 08 06:07:52 PM PDT 24
Peak memory 213312 kb
Host smart-297a60dd-59ac-438e-85b3-babbb8d9c7d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144653534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1144653534
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.1640086184
Short name T12
Test name
Test status
Simulation time 51684931586 ps
CPU time 902.83 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:22:48 PM PDT 24
Peak memory 236692 kb
Host smart-50819fae-ab64-4bae-92a8-36aaa0501a38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640086184 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.1640086184
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.992738150
Short name T193
Test name
Test status
Simulation time 86136680 ps
CPU time 4.42 seconds
Started Aug 08 06:07:41 PM PDT 24
Finished Aug 08 06:07:46 PM PDT 24
Peak memory 212052 kb
Host smart-17365b25-cca3-409d-99e4-8630f86d290a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992738150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.992738150
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3682242318
Short name T293
Test name
Test status
Simulation time 10663057323 ps
CPU time 143.05 seconds
Started Aug 08 06:07:38 PM PDT 24
Finished Aug 08 06:10:01 PM PDT 24
Peak memory 237624 kb
Host smart-bc622e08-748e-4813-a281-bb3c037f265a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682242318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3682242318
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2497844471
Short name T163
Test name
Test status
Simulation time 254674011 ps
CPU time 10.89 seconds
Started Aug 08 06:07:42 PM PDT 24
Finished Aug 08 06:07:53 PM PDT 24
Peak memory 212976 kb
Host smart-f5db89c5-907c-4169-a91c-6ed74fcd0efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497844471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2497844471
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1280096559
Short name T180
Test name
Test status
Simulation time 618068242 ps
CPU time 13.43 seconds
Started Aug 08 06:07:40 PM PDT 24
Finished Aug 08 06:07:53 PM PDT 24
Peak memory 214736 kb
Host smart-3f21a96b-7de6-4470-96d3-de3bd3a5e9b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280096559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1280096559
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4034347938
Short name T331
Test name
Test status
Simulation time 518239750 ps
CPU time 4.95 seconds
Started Aug 08 06:08:09 PM PDT 24
Finished Aug 08 06:08:14 PM PDT 24
Peak memory 212080 kb
Host smart-a6345b84-e108-42e2-94eb-f9d3428b71e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034347938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4034347938
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1568169240
Short name T209
Test name
Test status
Simulation time 1879569580 ps
CPU time 97.51 seconds
Started Aug 08 06:07:46 PM PDT 24
Finished Aug 08 06:09:24 PM PDT 24
Peak memory 213320 kb
Host smart-4e482f7b-a252-4a30-a9cd-8bede1c2e4dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568169240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1568169240
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.975833147
Short name T320
Test name
Test status
Simulation time 645834413 ps
CPU time 9.46 seconds
Started Aug 08 06:08:06 PM PDT 24
Finished Aug 08 06:08:16 PM PDT 24
Peak memory 212960 kb
Host smart-a0956941-7bef-4a36-9b69-ef6e25edf19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975833147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.975833147
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.159039503
Short name T326
Test name
Test status
Simulation time 369519360 ps
CPU time 5.58 seconds
Started Aug 08 06:07:49 PM PDT 24
Finished Aug 08 06:07:54 PM PDT 24
Peak memory 212240 kb
Host smart-fca8c2fc-a8be-47d5-98df-cbd3c31b614b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159039503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.159039503
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3759627381
Short name T165
Test name
Test status
Simulation time 816037419 ps
CPU time 13.33 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:07:58 PM PDT 24
Peak memory 214384 kb
Host smart-8510814f-c93d-4640-98c0-ff9d44389bdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759627381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3759627381
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.628653859
Short name T151
Test name
Test status
Simulation time 518634058 ps
CPU time 4.09 seconds
Started Aug 08 06:07:43 PM PDT 24
Finished Aug 08 06:07:47 PM PDT 24
Peak memory 212076 kb
Host smart-75e4d133-04d2-4728-adf2-74c3affee236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628653859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.628653859
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2929111821
Short name T55
Test name
Test status
Simulation time 6497790151 ps
CPU time 85.61 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:09:14 PM PDT 24
Peak memory 229044 kb
Host smart-918d9bae-08e6-4581-af3c-5aa39bd59e3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929111821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2929111821
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3496658884
Short name T312
Test name
Test status
Simulation time 531800482 ps
CPU time 8.75 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:07:57 PM PDT 24
Peak memory 212212 kb
Host smart-0dc4da04-c4e8-48f1-bb44-847e4bd89e29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496658884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3496658884
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.875255583
Short name T295
Test name
Test status
Simulation time 146798200 ps
CPU time 9.32 seconds
Started Aug 08 06:07:46 PM PDT 24
Finished Aug 08 06:07:56 PM PDT 24
Peak memory 212076 kb
Host smart-fd5a4a9c-2d8d-4d5e-9195-983ad20a1ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875255583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.875255583
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1090322328
Short name T118
Test name
Test status
Simulation time 24299051808 ps
CPU time 10321.9 seconds
Started Aug 08 06:07:46 PM PDT 24
Finished Aug 08 08:59:49 PM PDT 24
Peak memory 231740 kb
Host smart-848b2e72-8338-4edd-8480-e360bccbe2d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090322328 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1090322328
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1049659582
Short name T308
Test name
Test status
Simulation time 779053953 ps
CPU time 5.22 seconds
Started Aug 08 06:08:00 PM PDT 24
Finished Aug 08 06:08:05 PM PDT 24
Peak memory 212028 kb
Host smart-ae75609a-226c-44af-b49b-cac532f823ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049659582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1049659582
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3651091621
Short name T192
Test name
Test status
Simulation time 6619884487 ps
CPU time 92.49 seconds
Started Aug 08 06:07:43 PM PDT 24
Finished Aug 08 06:09:15 PM PDT 24
Peak memory 225712 kb
Host smart-d288ec83-088f-4139-8239-f0be84aed831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651091621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3651091621
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1235628600
Short name T270
Test name
Test status
Simulation time 2482326983 ps
CPU time 11.21 seconds
Started Aug 08 06:07:44 PM PDT 24
Finished Aug 08 06:07:55 PM PDT 24
Peak memory 213052 kb
Host smart-6d94790f-8566-43e5-b3de-50714b920098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235628600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1235628600
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.476051505
Short name T6
Test name
Test status
Simulation time 555018090 ps
CPU time 6.2 seconds
Started Aug 08 06:07:53 PM PDT 24
Finished Aug 08 06:08:00 PM PDT 24
Peak memory 212192 kb
Host smart-8be151f8-711e-4f32-a582-18f21087f9a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476051505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.476051505
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1286322157
Short name T84
Test name
Test status
Simulation time 386108475 ps
CPU time 15.74 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:08:04 PM PDT 24
Peak memory 214544 kb
Host smart-69f45a7f-fb3c-4108-afd5-d1ca577cb4f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286322157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1286322157
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3863744203
Short name T186
Test name
Test status
Simulation time 130850045 ps
CPU time 5.1 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:07:53 PM PDT 24
Peak memory 212096 kb
Host smart-aa820c57-e0c6-4183-b8c7-796e3c2b31bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863744203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3863744203
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4245103973
Short name T229
Test name
Test status
Simulation time 2694738108 ps
CPU time 139.85 seconds
Started Aug 08 06:07:49 PM PDT 24
Finished Aug 08 06:10:08 PM PDT 24
Peak memory 238552 kb
Host smart-fc355d03-3373-472a-b19b-1df92a14629a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245103973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4245103973
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.954453939
Short name T218
Test name
Test status
Simulation time 533418790 ps
CPU time 11.1 seconds
Started Aug 08 06:07:50 PM PDT 24
Finished Aug 08 06:08:01 PM PDT 24
Peak memory 213068 kb
Host smart-5844a4b9-d0a3-41a9-baeb-8c2edec0d8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954453939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.954453939
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2199835067
Short name T243
Test name
Test status
Simulation time 98942876 ps
CPU time 5.62 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:07:53 PM PDT 24
Peak memory 212188 kb
Host smart-f2dda2d6-8902-4538-bcdf-efed451c7bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199835067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2199835067
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2652412876
Short name T217
Test name
Test status
Simulation time 204320358 ps
CPU time 11.92 seconds
Started Aug 08 06:07:49 PM PDT 24
Finished Aug 08 06:08:01 PM PDT 24
Peak memory 214040 kb
Host smart-a6725aad-dfb2-44fe-a233-ab76451d9851
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652412876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2652412876
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2305475908
Short name T140
Test name
Test status
Simulation time 126116500 ps
CPU time 5.19 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:07:54 PM PDT 24
Peak memory 212048 kb
Host smart-beb4a661-8954-4b8e-b1ea-6da30bfaa72e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305475908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2305475908
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2925580019
Short name T233
Test name
Test status
Simulation time 2079495271 ps
CPU time 103.38 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:09:29 PM PDT 24
Peak memory 229108 kb
Host smart-6cd61c65-c90b-47af-9343-99588e1efae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925580019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2925580019
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3642289078
Short name T317
Test name
Test status
Simulation time 994203974 ps
CPU time 11.14 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:07:57 PM PDT 24
Peak memory 212944 kb
Host smart-61c5055c-e356-4166-979a-2d6bb6d9da9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642289078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3642289078
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.402754697
Short name T132
Test name
Test status
Simulation time 195599916 ps
CPU time 5.8 seconds
Started Aug 08 06:07:40 PM PDT 24
Finished Aug 08 06:07:46 PM PDT 24
Peak memory 212152 kb
Host smart-4e6521f0-f8db-4cab-af3b-c1af0a6eab99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402754697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.402754697
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1814256264
Short name T302
Test name
Test status
Simulation time 316886667 ps
CPU time 13.37 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:08:00 PM PDT 24
Peak memory 216112 kb
Host smart-a3681c41-4059-46bb-9bb8-d7a0c4f58dc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814256264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1814256264
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1103842815
Short name T223
Test name
Test status
Simulation time 261871595 ps
CPU time 5.15 seconds
Started Aug 08 06:07:52 PM PDT 24
Finished Aug 08 06:07:57 PM PDT 24
Peak memory 212060 kb
Host smart-d7ad70d2-fa37-4194-8396-f97bb46cafb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103842815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1103842815
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.734316904
Short name T129
Test name
Test status
Simulation time 2019027762 ps
CPU time 94.14 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:09:21 PM PDT 24
Peak memory 237800 kb
Host smart-eca0a76a-a5d2-44ef-83e1-fa16d89a616c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734316904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.734316904
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.960358842
Short name T153
Test name
Test status
Simulation time 542480738 ps
CPU time 11.18 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:08:00 PM PDT 24
Peak memory 212784 kb
Host smart-f8b522b0-1443-4c46-91d3-09159f58e2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960358842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.960358842
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2477905545
Short name T8
Test name
Test status
Simulation time 140685699 ps
CPU time 6.54 seconds
Started Aug 08 06:07:53 PM PDT 24
Finished Aug 08 06:07:59 PM PDT 24
Peak memory 212172 kb
Host smart-b7145b46-46c3-4c3a-8cc8-f5cf84bd0a60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477905545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2477905545
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3277253758
Short name T299
Test name
Test status
Simulation time 609845198 ps
CPU time 13.41 seconds
Started Aug 08 06:07:55 PM PDT 24
Finished Aug 08 06:08:08 PM PDT 24
Peak memory 214552 kb
Host smart-2c609238-187a-480f-b459-4d9623e2adfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277253758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3277253758
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1683608310
Short name T231
Test name
Test status
Simulation time 565748999 ps
CPU time 5.03 seconds
Started Aug 08 06:07:50 PM PDT 24
Finished Aug 08 06:07:55 PM PDT 24
Peak memory 212048 kb
Host smart-f63f3cea-accc-4646-abb3-5f244a5ef36a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683608310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1683608310
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3971422269
Short name T142
Test name
Test status
Simulation time 3548582905 ps
CPU time 10.92 seconds
Started Aug 08 06:07:42 PM PDT 24
Finished Aug 08 06:07:53 PM PDT 24
Peak memory 213524 kb
Host smart-4e741b06-1de5-4e9a-8e95-8a39002a2b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971422269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3971422269
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3193448859
Short name T138
Test name
Test status
Simulation time 389460233 ps
CPU time 5.78 seconds
Started Aug 08 06:07:54 PM PDT 24
Finished Aug 08 06:08:05 PM PDT 24
Peak memory 212132 kb
Host smart-895320b1-6340-434e-b203-ef1a197dc75b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193448859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3193448859
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.732414559
Short name T179
Test name
Test status
Simulation time 1566635608 ps
CPU time 22.81 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:08:10 PM PDT 24
Peak memory 217580 kb
Host smart-0b07d813-8f84-4adb-adec-55b7f0c52d52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732414559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.732414559
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.704390447
Short name T230
Test name
Test status
Simulation time 19380241070 ps
CPU time 392.57 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:14:20 PM PDT 24
Peak memory 224560 kb
Host smart-06555071-e713-497f-bfe9-99a19e5b32e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704390447 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.704390447
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2364324765
Short name T313
Test name
Test status
Simulation time 176752179 ps
CPU time 4.29 seconds
Started Aug 08 06:07:44 PM PDT 24
Finished Aug 08 06:07:49 PM PDT 24
Peak memory 212096 kb
Host smart-a6841291-3ee0-4856-a398-e331a2b384c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364324765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2364324765
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.4106848127
Short name T131
Test name
Test status
Simulation time 5094217462 ps
CPU time 113.39 seconds
Started Aug 08 06:07:42 PM PDT 24
Finished Aug 08 06:09:36 PM PDT 24
Peak memory 238424 kb
Host smart-caab9ef1-84e1-41f0-a3d0-270700a52656
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106848127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.4106848127
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2022811259
Short name T102
Test name
Test status
Simulation time 522110854 ps
CPU time 11.43 seconds
Started Aug 08 06:07:46 PM PDT 24
Finished Aug 08 06:07:58 PM PDT 24
Peak memory 212816 kb
Host smart-ceef9495-9ae9-46ba-80e8-63566cbc3ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022811259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2022811259
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3349583517
Short name T250
Test name
Test status
Simulation time 566123817 ps
CPU time 6.59 seconds
Started Aug 08 06:07:51 PM PDT 24
Finished Aug 08 06:07:57 PM PDT 24
Peak memory 212192 kb
Host smart-06969db6-4150-4439-ae3c-9eee60a604fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349583517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3349583517
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.498803867
Short name T107
Test name
Test status
Simulation time 1737188029 ps
CPU time 17.73 seconds
Started Aug 08 06:08:04 PM PDT 24
Finished Aug 08 06:08:22 PM PDT 24
Peak memory 216936 kb
Host smart-6d6cbe4f-70da-4850-a060-1c225d7a79c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498803867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.498803867
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.322104711
Short name T51
Test name
Test status
Simulation time 16408620689 ps
CPU time 682.11 seconds
Started Aug 08 06:07:46 PM PDT 24
Finished Aug 08 06:19:08 PM PDT 24
Peak memory 236328 kb
Host smart-2139c8ce-10bd-4967-b7dd-c9fe1e1f041a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322104711 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.322104711
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.832383339
Short name T211
Test name
Test status
Simulation time 165766056 ps
CPU time 4.88 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:07:53 PM PDT 24
Peak memory 212108 kb
Host smart-62c458d1-cffd-4541-8a96-5000f505fd68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832383339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.832383339
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.346268626
Short name T39
Test name
Test status
Simulation time 11306836900 ps
CPU time 139.41 seconds
Started Aug 08 06:07:41 PM PDT 24
Finished Aug 08 06:10:01 PM PDT 24
Peak memory 226392 kb
Host smart-85469b29-a282-4b9c-8e21-7bf641625db8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346268626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.346268626
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1385835501
Short name T33
Test name
Test status
Simulation time 521451356 ps
CPU time 11.44 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:07:59 PM PDT 24
Peak memory 212828 kb
Host smart-07f72349-5581-41c1-bc02-e4ad8c69c11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385835501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1385835501
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4178713477
Short name T177
Test name
Test status
Simulation time 146838034 ps
CPU time 6.85 seconds
Started Aug 08 06:07:41 PM PDT 24
Finished Aug 08 06:07:48 PM PDT 24
Peak memory 212160 kb
Host smart-02ebd462-78eb-4a79-ab82-849f5f978324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178713477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4178713477
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3311134140
Short name T13
Test name
Test status
Simulation time 288327911 ps
CPU time 12.37 seconds
Started Aug 08 06:07:54 PM PDT 24
Finished Aug 08 06:08:07 PM PDT 24
Peak memory 213932 kb
Host smart-47da5197-25b2-43ea-9c48-f53cf45efa15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311134140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3311134140
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3729523223
Short name T172
Test name
Test status
Simulation time 833650027 ps
CPU time 5.24 seconds
Started Aug 08 06:07:37 PM PDT 24
Finished Aug 08 06:07:43 PM PDT 24
Peak memory 212024 kb
Host smart-03cf0af8-754a-459e-9f93-831779a49f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729523223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3729523223
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1781275515
Short name T40
Test name
Test status
Simulation time 4908748366 ps
CPU time 78.65 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:09:04 PM PDT 24
Peak memory 238524 kb
Host smart-470b7c69-0e9b-45d3-b2dd-bae0f95e3c5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781275515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1781275515
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3396228608
Short name T249
Test name
Test status
Simulation time 497255671 ps
CPU time 11.03 seconds
Started Aug 08 06:07:40 PM PDT 24
Finished Aug 08 06:07:52 PM PDT 24
Peak memory 212996 kb
Host smart-b3903680-0999-4ca5-95e2-625c6e940bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396228608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3396228608
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3428981766
Short name T265
Test name
Test status
Simulation time 533444095 ps
CPU time 6.32 seconds
Started Aug 08 06:07:44 PM PDT 24
Finished Aug 08 06:07:50 PM PDT 24
Peak memory 212088 kb
Host smart-c81b6f82-71ee-4299-aaa9-dcbd7eaea5cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428981766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3428981766
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3042586914
Short name T22
Test name
Test status
Simulation time 352943748 ps
CPU time 54.47 seconds
Started Aug 08 06:07:42 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 239756 kb
Host smart-e7fee488-bde0-49be-a0a7-318c662dbde5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042586914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3042586914
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1039294984
Short name T245
Test name
Test status
Simulation time 138289820 ps
CPU time 6.41 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:07:52 PM PDT 24
Peak memory 212196 kb
Host smart-26431926-2a8e-45e2-ba74-28243400bcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039294984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1039294984
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3608696477
Short name T155
Test name
Test status
Simulation time 301071813 ps
CPU time 14.37 seconds
Started Aug 08 06:07:44 PM PDT 24
Finished Aug 08 06:07:59 PM PDT 24
Peak memory 215252 kb
Host smart-6d784f52-176f-4a54-a142-250a38a3706d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608696477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3608696477
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3080219566
Short name T5
Test name
Test status
Simulation time 621709373 ps
CPU time 4.94 seconds
Started Aug 08 06:08:02 PM PDT 24
Finished Aug 08 06:08:07 PM PDT 24
Peak memory 212104 kb
Host smart-4fe307e6-6ffb-48e0-ba47-3163f4233de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080219566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3080219566
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3706513922
Short name T234
Test name
Test status
Simulation time 1182100083 ps
CPU time 70.02 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:08:57 PM PDT 24
Peak memory 213376 kb
Host smart-87e40f83-5967-4b31-94f6-b59b5944d10c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706513922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3706513922
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1384143589
Short name T167
Test name
Test status
Simulation time 169786110 ps
CPU time 9.41 seconds
Started Aug 08 06:07:51 PM PDT 24
Finished Aug 08 06:08:01 PM PDT 24
Peak memory 212968 kb
Host smart-4d0c748d-cfbd-4279-97d8-7570cb886e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384143589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1384143589
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1982885155
Short name T262
Test name
Test status
Simulation time 208080005 ps
CPU time 6.64 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:07:54 PM PDT 24
Peak memory 212160 kb
Host smart-5744c12f-889c-4c0f-a51a-402751f5858f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982885155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1982885155
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4149658083
Short name T256
Test name
Test status
Simulation time 304006879 ps
CPU time 15.9 seconds
Started Aug 08 06:07:44 PM PDT 24
Finished Aug 08 06:08:00 PM PDT 24
Peak memory 214704 kb
Host smart-7dabfd45-12c3-48ec-8649-d15b4072bb15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149658083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4149658083
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2138753500
Short name T296
Test name
Test status
Simulation time 87625936 ps
CPU time 4.33 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:07:52 PM PDT 24
Peak memory 212100 kb
Host smart-e91c8a07-f9b4-4d3e-a73c-cf0dcac66b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138753500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2138753500
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3136793674
Short name T174
Test name
Test status
Simulation time 10580873781 ps
CPU time 112.01 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:09:40 PM PDT 24
Peak memory 235028 kb
Host smart-7a12985d-54e1-4bcb-b998-645707e4e2cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136793674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3136793674
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4156622821
Short name T287
Test name
Test status
Simulation time 348009079 ps
CPU time 9.55 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:07:58 PM PDT 24
Peak memory 212924 kb
Host smart-429352d1-f144-47b8-add1-5f995ac6f404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156622821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4156622821
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3171590676
Short name T32
Test name
Test status
Simulation time 571800293 ps
CPU time 6.38 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:07:54 PM PDT 24
Peak memory 212196 kb
Host smart-bfba79fc-8ac0-437d-9d3f-bbd0524a10d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171590676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3171590676
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3890640655
Short name T1
Test name
Test status
Simulation time 86351822 ps
CPU time 5.03 seconds
Started Aug 08 06:07:52 PM PDT 24
Finished Aug 08 06:07:57 PM PDT 24
Peak memory 212164 kb
Host smart-3c21727c-bdd6-48d6-8d1c-f5a212f37f5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890640655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3890640655
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3809898771
Short name T160
Test name
Test status
Simulation time 335647528 ps
CPU time 4.3 seconds
Started Aug 08 06:08:04 PM PDT 24
Finished Aug 08 06:08:08 PM PDT 24
Peak memory 212100 kb
Host smart-e7b98b3a-a6fb-4cc4-9fdd-ca1938cb4d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809898771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3809898771
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2486654282
Short name T241
Test name
Test status
Simulation time 19923310699 ps
CPU time 101.29 seconds
Started Aug 08 06:07:48 PM PDT 24
Finished Aug 08 06:09:29 PM PDT 24
Peak memory 234428 kb
Host smart-5fee7e29-d353-4faf-86eb-8a8e131b9e3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486654282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2486654282
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1442399946
Short name T291
Test name
Test status
Simulation time 1916102949 ps
CPU time 11.39 seconds
Started Aug 08 06:07:49 PM PDT 24
Finished Aug 08 06:08:01 PM PDT 24
Peak memory 212988 kb
Host smart-2944eb03-f35c-46f7-b8bc-304b21159d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442399946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1442399946
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1937741559
Short name T298
Test name
Test status
Simulation time 842907771 ps
CPU time 5.65 seconds
Started Aug 08 06:08:04 PM PDT 24
Finished Aug 08 06:08:10 PM PDT 24
Peak memory 212204 kb
Host smart-7e33f8d5-5959-48d5-9e1c-7dbb782e8b0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937741559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1937741559
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1753370692
Short name T16
Test name
Test status
Simulation time 814310344 ps
CPU time 9.27 seconds
Started Aug 08 06:07:50 PM PDT 24
Finished Aug 08 06:08:00 PM PDT 24
Peak memory 212104 kb
Host smart-43c5ba72-f4e6-485a-a56b-cab574de4917
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753370692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1753370692
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.294410468
Short name T307
Test name
Test status
Simulation time 2842973836 ps
CPU time 157.48 seconds
Started Aug 08 06:07:44 PM PDT 24
Finished Aug 08 06:10:21 PM PDT 24
Peak memory 238560 kb
Host smart-c29a647d-1d6c-4e0f-b88d-980907ae29aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294410468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.294410468
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3849884874
Short name T279
Test name
Test status
Simulation time 2060691648 ps
CPU time 16.27 seconds
Started Aug 08 06:08:03 PM PDT 24
Finished Aug 08 06:08:20 PM PDT 24
Peak memory 213468 kb
Host smart-547c80a7-19d6-419d-bf6e-4101ffb30777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849884874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3849884874
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2754180066
Short name T329
Test name
Test status
Simulation time 533502900 ps
CPU time 6.38 seconds
Started Aug 08 06:08:06 PM PDT 24
Finished Aug 08 06:08:12 PM PDT 24
Peak memory 212204 kb
Host smart-2e6e49dd-2bf7-4f64-8804-4e1a1926596f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754180066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2754180066
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.726870526
Short name T14
Test name
Test status
Simulation time 1943119381 ps
CPU time 7.8 seconds
Started Aug 08 06:07:55 PM PDT 24
Finished Aug 08 06:08:03 PM PDT 24
Peak memory 212480 kb
Host smart-d1347acd-0a72-4c7f-a51e-abad56fac415
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726870526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.726870526
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2875690741
Short name T23
Test name
Test status
Simulation time 62128659511 ps
CPU time 1213.29 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:28:01 PM PDT 24
Peak memory 236688 kb
Host smart-653507b9-b949-40c7-aaf4-bfb414a5f151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875690741 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2875690741
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1655452753
Short name T319
Test name
Test status
Simulation time 127118696 ps
CPU time 5.21 seconds
Started Aug 08 06:08:12 PM PDT 24
Finished Aug 08 06:08:17 PM PDT 24
Peak memory 212024 kb
Host smart-b80466fa-3cb9-4038-96b2-22375f0b71d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655452753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1655452753
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3123895767
Short name T260
Test name
Test status
Simulation time 2393099452 ps
CPU time 71.24 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:08:58 PM PDT 24
Peak memory 213476 kb
Host smart-bede126b-1b09-4f2b-a63b-5e62bb4c7934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123895767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3123895767
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.819910954
Short name T239
Test name
Test status
Simulation time 172157861 ps
CPU time 9.49 seconds
Started Aug 08 06:07:51 PM PDT 24
Finished Aug 08 06:08:01 PM PDT 24
Peak memory 212956 kb
Host smart-afdd537e-2c9a-41be-a522-3249f66a9974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819910954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.819910954
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1454612899
Short name T117
Test name
Test status
Simulation time 602091752 ps
CPU time 6.33 seconds
Started Aug 08 06:08:07 PM PDT 24
Finished Aug 08 06:08:14 PM PDT 24
Peak memory 212180 kb
Host smart-acfffd06-f2d5-439c-be9b-d850b7ca19fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1454612899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1454612899
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.657302199
Short name T136
Test name
Test status
Simulation time 413019763 ps
CPU time 18.82 seconds
Started Aug 08 06:07:52 PM PDT 24
Finished Aug 08 06:08:11 PM PDT 24
Peak memory 216340 kb
Host smart-c41940fe-2c11-4e60-ae4b-83484bb2c7d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657302199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.657302199
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1990386237
Short name T56
Test name
Test status
Simulation time 76405876125 ps
CPU time 730.99 seconds
Started Aug 08 06:07:46 PM PDT 24
Finished Aug 08 06:19:57 PM PDT 24
Peak memory 236688 kb
Host smart-91c864c4-8d5d-4750-badb-9f264d8f5220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990386237 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1990386237
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2618068921
Short name T17
Test name
Test status
Simulation time 232041822 ps
CPU time 4.18 seconds
Started Aug 08 06:08:08 PM PDT 24
Finished Aug 08 06:08:13 PM PDT 24
Peak memory 212080 kb
Host smart-59b3deee-4191-40b7-853e-1ac20b3f3ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618068921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2618068921
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3971874609
Short name T30
Test name
Test status
Simulation time 11751581091 ps
CPU time 127.66 seconds
Started Aug 08 06:08:07 PM PDT 24
Finished Aug 08 06:10:15 PM PDT 24
Peak memory 226288 kb
Host smart-5b7225c1-607e-4064-b64e-382d12fdd26c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971874609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3971874609
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1889634703
Short name T178
Test name
Test status
Simulation time 347102016 ps
CPU time 9.77 seconds
Started Aug 08 06:08:04 PM PDT 24
Finished Aug 08 06:08:14 PM PDT 24
Peak memory 212856 kb
Host smart-807f7c65-63d8-4226-b4f9-05d91e147346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889634703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1889634703
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2173364069
Short name T244
Test name
Test status
Simulation time 391678680 ps
CPU time 5.79 seconds
Started Aug 08 06:08:05 PM PDT 24
Finished Aug 08 06:08:11 PM PDT 24
Peak memory 212168 kb
Host smart-a2a5c50e-9915-40a5-b2d2-045cd72df58d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173364069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2173364069
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3105899000
Short name T278
Test name
Test status
Simulation time 2232005941 ps
CPU time 25.22 seconds
Started Aug 08 06:07:54 PM PDT 24
Finished Aug 08 06:08:19 PM PDT 24
Peak memory 217320 kb
Host smart-9c15cb34-5f29-4ec4-b373-696d1a236c01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105899000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3105899000
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2902157753
Short name T311
Test name
Test status
Simulation time 82146957081 ps
CPU time 847.58 seconds
Started Aug 08 06:08:01 PM PDT 24
Finished Aug 08 06:22:09 PM PDT 24
Peak memory 232644 kb
Host smart-ca0ff7d8-9e5e-44c5-8fd0-56bcc2a9b8bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902157753 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2902157753
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.555245115
Short name T253
Test name
Test status
Simulation time 519845522 ps
CPU time 5.01 seconds
Started Aug 08 06:07:50 PM PDT 24
Finished Aug 08 06:07:56 PM PDT 24
Peak memory 212080 kb
Host smart-fa540291-b2ee-432a-8888-58c4903f908a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555245115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.555245115
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1149875242
Short name T191
Test name
Test status
Simulation time 3114445351 ps
CPU time 85.33 seconds
Started Aug 08 06:07:49 PM PDT 24
Finished Aug 08 06:09:15 PM PDT 24
Peak memory 214640 kb
Host smart-fc60e9fc-3641-474f-933f-2f20240e901a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149875242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1149875242
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4177565199
Short name T2
Test name
Test status
Simulation time 169393209 ps
CPU time 9.53 seconds
Started Aug 08 06:08:15 PM PDT 24
Finished Aug 08 06:08:24 PM PDT 24
Peak memory 212956 kb
Host smart-3be41be9-000b-4ba0-93d2-e12aed152bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177565199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4177565199
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.889691731
Short name T81
Test name
Test status
Simulation time 849065136 ps
CPU time 19.44 seconds
Started Aug 08 06:07:49 PM PDT 24
Finished Aug 08 06:08:08 PM PDT 24
Peak memory 216360 kb
Host smart-09f81c1a-7753-4b3b-b66c-ba698cf5c7fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889691731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.889691731
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3247216938
Short name T58
Test name
Test status
Simulation time 132485369415 ps
CPU time 1417.07 seconds
Started Aug 08 06:08:07 PM PDT 24
Finished Aug 08 06:31:45 PM PDT 24
Peak memory 244900 kb
Host smart-b55f9b39-b2cf-4649-9bf2-4fbf457e2400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247216938 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3247216938
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.66389156
Short name T210
Test name
Test status
Simulation time 129021350 ps
CPU time 5.18 seconds
Started Aug 08 06:07:49 PM PDT 24
Finished Aug 08 06:07:54 PM PDT 24
Peak memory 212016 kb
Host smart-c008b575-8d5a-4db4-aa11-1629b28154c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66389156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.66389156
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1108020981
Short name T130
Test name
Test status
Simulation time 5594018548 ps
CPU time 68.21 seconds
Started Aug 08 06:08:01 PM PDT 24
Finished Aug 08 06:09:09 PM PDT 24
Peak memory 229252 kb
Host smart-19085b18-1ed9-482a-aae0-cc6e739b82ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108020981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1108020981
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3776912532
Short name T257
Test name
Test status
Simulation time 640992161 ps
CPU time 10.69 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:28 PM PDT 24
Peak memory 213084 kb
Host smart-867cba67-c6f8-4490-9e92-c852bec009c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776912532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3776912532
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2587467752
Short name T185
Test name
Test status
Simulation time 100068875 ps
CPU time 5.65 seconds
Started Aug 08 06:07:51 PM PDT 24
Finished Aug 08 06:07:57 PM PDT 24
Peak memory 212172 kb
Host smart-78e01f7d-0018-4a3b-acb7-59d4286ddbaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587467752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2587467752
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.341155091
Short name T316
Test name
Test status
Simulation time 559084370 ps
CPU time 9.15 seconds
Started Aug 08 06:07:52 PM PDT 24
Finished Aug 08 06:08:01 PM PDT 24
Peak memory 212104 kb
Host smart-f57a48bc-988b-482c-97d1-265291f76d32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341155091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.341155091
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1192967216
Short name T57
Test name
Test status
Simulation time 6830185476 ps
CPU time 87.22 seconds
Started Aug 08 06:08:00 PM PDT 24
Finished Aug 08 06:09:27 PM PDT 24
Peak memory 223000 kb
Host smart-57a8061f-fea8-4309-bfcc-51994976eca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192967216 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1192967216
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2033845600
Short name T309
Test name
Test status
Simulation time 172057812 ps
CPU time 4.27 seconds
Started Aug 08 06:07:50 PM PDT 24
Finished Aug 08 06:07:54 PM PDT 24
Peak memory 212028 kb
Host smart-fae83669-bb37-45e9-8d73-c1e8565ef3ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033845600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2033845600
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.583629819
Short name T37
Test name
Test status
Simulation time 12757429941 ps
CPU time 81.94 seconds
Started Aug 08 06:08:07 PM PDT 24
Finished Aug 08 06:09:30 PM PDT 24
Peak memory 213492 kb
Host smart-174b7348-55e2-42ec-9d8a-e861d41a948a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583629819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.583629819
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1796657920
Short name T240
Test name
Test status
Simulation time 962329142 ps
CPU time 11.28 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:08:26 PM PDT 24
Peak memory 212920 kb
Host smart-b1978d8b-e599-4014-9f93-2b505139dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796657920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1796657920
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1794901940
Short name T194
Test name
Test status
Simulation time 143486480 ps
CPU time 6.65 seconds
Started Aug 08 06:07:58 PM PDT 24
Finished Aug 08 06:08:04 PM PDT 24
Peak memory 212196 kb
Host smart-afb6be05-a93e-4009-bd48-825e08dc3117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794901940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1794901940
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1859429692
Short name T67
Test name
Test status
Simulation time 570400432 ps
CPU time 12.54 seconds
Started Aug 08 06:08:07 PM PDT 24
Finished Aug 08 06:08:20 PM PDT 24
Peak memory 212460 kb
Host smart-b0e48793-b0db-4b9a-b0bb-67e496e0ec98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859429692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1859429692
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.503214281
Short name T4
Test name
Test status
Simulation time 251277839 ps
CPU time 5.25 seconds
Started Aug 08 06:08:05 PM PDT 24
Finished Aug 08 06:08:10 PM PDT 24
Peak memory 212036 kb
Host smart-6987e18c-87a1-4a91-95b9-2a2547bf990c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503214281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.503214281
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3581189688
Short name T275
Test name
Test status
Simulation time 3096445556 ps
CPU time 195.62 seconds
Started Aug 08 06:07:58 PM PDT 24
Finished Aug 08 06:11:13 PM PDT 24
Peak memory 229360 kb
Host smart-fd29f73b-4caa-4ea1-86b7-22b86eb2b966
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581189688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3581189688
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.718098539
Short name T196
Test name
Test status
Simulation time 990641397 ps
CPU time 11.18 seconds
Started Aug 08 06:07:52 PM PDT 24
Finished Aug 08 06:08:03 PM PDT 24
Peak memory 212180 kb
Host smart-bcce791e-8819-4a2b-83d2-68f04542465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718098539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.718098539
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.825743923
Short name T224
Test name
Test status
Simulation time 471275183 ps
CPU time 6.31 seconds
Started Aug 08 06:07:50 PM PDT 24
Finished Aug 08 06:07:57 PM PDT 24
Peak memory 212176 kb
Host smart-2e9942c0-17e3-4738-b54c-5ea46ed94ddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825743923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.825743923
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1718275288
Short name T170
Test name
Test status
Simulation time 622074994 ps
CPU time 17.65 seconds
Started Aug 08 06:07:50 PM PDT 24
Finished Aug 08 06:08:07 PM PDT 24
Peak memory 216580 kb
Host smart-ff9b1fb3-76d9-4d43-8246-f4cb84fc125e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718275288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1718275288
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3169619394
Short name T149
Test name
Test status
Simulation time 1957574857 ps
CPU time 7.37 seconds
Started Aug 08 06:07:37 PM PDT 24
Finished Aug 08 06:07:44 PM PDT 24
Peak memory 212052 kb
Host smart-00ee7014-8760-40ba-89be-74f83fef1575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169619394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3169619394
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.4158735350
Short name T106
Test name
Test status
Simulation time 10119354175 ps
CPU time 154.48 seconds
Started Aug 08 06:07:39 PM PDT 24
Finished Aug 08 06:10:14 PM PDT 24
Peak memory 239420 kb
Host smart-27dea73a-f0e7-48e1-a1f3-ba8c51a5b9e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158735350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.4158735350
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.697565935
Short name T147
Test name
Test status
Simulation time 2075212765 ps
CPU time 9.23 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:07:55 PM PDT 24
Peak memory 212968 kb
Host smart-c93e048e-cf60-47e4-9988-7e65fea81001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697565935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.697565935
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2610597187
Short name T321
Test name
Test status
Simulation time 139141330 ps
CPU time 6.68 seconds
Started Aug 08 06:07:34 PM PDT 24
Finished Aug 08 06:07:41 PM PDT 24
Peak memory 212136 kb
Host smart-6f45f798-18bb-423e-b21a-d8396824b733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2610597187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2610597187
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.142668066
Short name T20
Test name
Test status
Simulation time 874196880 ps
CPU time 53.81 seconds
Started Aug 08 06:07:38 PM PDT 24
Finished Aug 08 06:08:32 PM PDT 24
Peak memory 237404 kb
Host smart-c2734d72-409a-441e-bd85-a1314b45b1c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142668066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.142668066
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3785318942
Short name T104
Test name
Test status
Simulation time 102282652 ps
CPU time 5.53 seconds
Started Aug 08 06:07:41 PM PDT 24
Finished Aug 08 06:07:46 PM PDT 24
Peak memory 212240 kb
Host smart-f599ab75-11a1-4722-91bc-6860da96da19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785318942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3785318942
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2807752654
Short name T188
Test name
Test status
Simulation time 281441114 ps
CPU time 12.16 seconds
Started Aug 08 06:07:38 PM PDT 24
Finished Aug 08 06:07:51 PM PDT 24
Peak memory 214424 kb
Host smart-524f7238-5d49-4ec7-b8a8-bff6f7b28073
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807752654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2807752654
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.176605445
Short name T292
Test name
Test status
Simulation time 48069182619 ps
CPU time 1834.34 seconds
Started Aug 08 06:07:41 PM PDT 24
Finished Aug 08 06:38:15 PM PDT 24
Peak memory 233748 kb
Host smart-21e52329-da96-4f7d-809e-5f4d8f8c7cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176605445 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.176605445
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3328962265
Short name T324
Test name
Test status
Simulation time 521138816 ps
CPU time 5.19 seconds
Started Aug 08 06:07:58 PM PDT 24
Finished Aug 08 06:08:03 PM PDT 24
Peak memory 212088 kb
Host smart-08f39740-ab0c-49f4-926a-64b13d4856d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328962265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3328962265
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.258262584
Short name T41
Test name
Test status
Simulation time 4895763254 ps
CPU time 126.76 seconds
Started Aug 08 06:07:58 PM PDT 24
Finished Aug 08 06:10:05 PM PDT 24
Peak memory 238456 kb
Host smart-c0f6db30-f42a-4ba0-8d69-7f70e46aec72
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258262584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.258262584
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3167027942
Short name T154
Test name
Test status
Simulation time 1844580842 ps
CPU time 9.47 seconds
Started Aug 08 06:07:50 PM PDT 24
Finished Aug 08 06:08:00 PM PDT 24
Peak memory 212940 kb
Host smart-7c346706-88fe-42ab-9b4a-cd0102f86987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167027942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3167027942
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.9330300
Short name T141
Test name
Test status
Simulation time 197581169 ps
CPU time 5.72 seconds
Started Aug 08 06:07:58 PM PDT 24
Finished Aug 08 06:08:03 PM PDT 24
Peak memory 212156 kb
Host smart-f741d637-506a-489b-858f-f6ccea6bc805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9330300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.9330300
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2243323965
Short name T175
Test name
Test status
Simulation time 299330870 ps
CPU time 16.43 seconds
Started Aug 08 06:08:07 PM PDT 24
Finished Aug 08 06:08:23 PM PDT 24
Peak memory 214424 kb
Host smart-57201942-3f01-40a1-bc08-b814e146f6bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243323965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2243323965
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1041085721
Short name T45
Test name
Test status
Simulation time 80343395812 ps
CPU time 1420.03 seconds
Started Aug 08 06:07:54 PM PDT 24
Finished Aug 08 06:31:35 PM PDT 24
Peak memory 236696 kb
Host smart-2345e710-b629-4802-8e61-b2af4e152163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041085721 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1041085721
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2471877784
Short name T300
Test name
Test status
Simulation time 88853435 ps
CPU time 4.25 seconds
Started Aug 08 06:08:03 PM PDT 24
Finished Aug 08 06:08:08 PM PDT 24
Peak memory 212092 kb
Host smart-ffa2f737-ea44-4dbf-aa85-1ade4d584a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471877784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2471877784
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.782390261
Short name T28
Test name
Test status
Simulation time 5932952382 ps
CPU time 74.19 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:09:29 PM PDT 24
Peak memory 234512 kb
Host smart-744e0e71-3513-4f69-8e6d-1cce38a16cab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782390261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.782390261
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3154894003
Short name T199
Test name
Test status
Simulation time 252101179 ps
CPU time 10.8 seconds
Started Aug 08 06:08:12 PM PDT 24
Finished Aug 08 06:08:23 PM PDT 24
Peak memory 212852 kb
Host smart-6ff54779-03fc-43f7-a2be-5c94fc874e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154894003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3154894003
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2444784339
Short name T303
Test name
Test status
Simulation time 206025923 ps
CPU time 5.36 seconds
Started Aug 08 06:08:06 PM PDT 24
Finished Aug 08 06:08:11 PM PDT 24
Peak memory 212168 kb
Host smart-b73f9457-9ec4-426e-a7ec-79653a6622a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444784339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2444784339
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3945715999
Short name T272
Test name
Test status
Simulation time 1666236722 ps
CPU time 20.6 seconds
Started Aug 08 06:08:13 PM PDT 24
Finished Aug 08 06:08:34 PM PDT 24
Peak memory 217244 kb
Host smart-52de6014-919c-4c79-932d-bcfe6f09b61a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945715999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3945715999
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2841941552
Short name T139
Test name
Test status
Simulation time 251787480 ps
CPU time 5.18 seconds
Started Aug 08 06:08:07 PM PDT 24
Finished Aug 08 06:08:12 PM PDT 24
Peak memory 212264 kb
Host smart-96f66975-f976-43f4-81b1-02cfdaf13e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841941552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2841941552
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.950647536
Short name T42
Test name
Test status
Simulation time 6078325378 ps
CPU time 126.87 seconds
Started Aug 08 06:08:04 PM PDT 24
Finished Aug 08 06:10:11 PM PDT 24
Peak memory 238324 kb
Host smart-4afec793-8e75-4ff5-b6b5-8a0a85885112
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950647536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.950647536
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2234774215
Short name T205
Test name
Test status
Simulation time 666080796 ps
CPU time 9.58 seconds
Started Aug 08 06:08:02 PM PDT 24
Finished Aug 08 06:08:11 PM PDT 24
Peak memory 212940 kb
Host smart-40b64c51-8ae4-4cc1-89b7-8dbca3dea463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234774215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2234774215
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1621158442
Short name T252
Test name
Test status
Simulation time 285847787 ps
CPU time 6.41 seconds
Started Aug 08 06:08:07 PM PDT 24
Finished Aug 08 06:08:14 PM PDT 24
Peak memory 212188 kb
Host smart-808f3861-6aa8-412a-9000-c67f471d7276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621158442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1621158442
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4203694029
Short name T277
Test name
Test status
Simulation time 1006905157 ps
CPU time 19.87 seconds
Started Aug 08 06:08:04 PM PDT 24
Finished Aug 08 06:08:23 PM PDT 24
Peak memory 214236 kb
Host smart-04541300-19ef-4e5c-a2df-4473eb60b365
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203694029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4203694029
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.144407873
Short name T109
Test name
Test status
Simulation time 13686434985 ps
CPU time 3783.41 seconds
Started Aug 08 06:08:00 PM PDT 24
Finished Aug 08 07:11:04 PM PDT 24
Peak memory 225660 kb
Host smart-cd2dcc55-d1d0-4835-81b4-5e110c605218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144407873 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.144407873
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4027790865
Short name T282
Test name
Test status
Simulation time 416808909 ps
CPU time 4.34 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:08:19 PM PDT 24
Peak memory 212112 kb
Host smart-aae05017-6ffe-477f-a8fc-f2dad8080ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027790865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4027790865
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1713346778
Short name T187
Test name
Test status
Simulation time 6867974052 ps
CPU time 86.96 seconds
Started Aug 08 06:08:00 PM PDT 24
Finished Aug 08 06:09:27 PM PDT 24
Peak memory 229168 kb
Host smart-d14f556d-2dc5-4fc0-9947-600209e2a49d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713346778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1713346778
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3011133775
Short name T202
Test name
Test status
Simulation time 678028869 ps
CPU time 9.81 seconds
Started Aug 08 06:08:11 PM PDT 24
Finished Aug 08 06:08:21 PM PDT 24
Peak memory 214912 kb
Host smart-df560b6b-f1f9-4ff0-983b-6207468feccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011133775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3011133775
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2685965490
Short name T72
Test name
Test status
Simulation time 422133480 ps
CPU time 5.46 seconds
Started Aug 08 06:08:11 PM PDT 24
Finished Aug 08 06:08:17 PM PDT 24
Peak memory 212236 kb
Host smart-139ea893-ff4f-47e3-a5b6-e5f60b96b40b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685965490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2685965490
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.289328633
Short name T158
Test name
Test status
Simulation time 186525060 ps
CPU time 11.45 seconds
Started Aug 08 06:07:59 PM PDT 24
Finished Aug 08 06:08:11 PM PDT 24
Peak memory 213472 kb
Host smart-396684a2-660b-4adf-bae3-8094b486c945
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289328633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.289328633
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2091894696
Short name T305
Test name
Test status
Simulation time 89296157 ps
CPU time 4.37 seconds
Started Aug 08 06:07:59 PM PDT 24
Finished Aug 08 06:08:04 PM PDT 24
Peak memory 211968 kb
Host smart-6d42f743-344f-44f2-854a-4bcf58170395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091894696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2091894696
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1402797750
Short name T184
Test name
Test status
Simulation time 6956810248 ps
CPU time 104.58 seconds
Started Aug 08 06:08:03 PM PDT 24
Finished Aug 08 06:09:48 PM PDT 24
Peak memory 238504 kb
Host smart-1a3e0bc8-9b78-4e70-a41b-82a61435496f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402797750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1402797750
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2783625423
Short name T24
Test name
Test status
Simulation time 497177577 ps
CPU time 11.15 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:08:26 PM PDT 24
Peak memory 212896 kb
Host smart-8c129d54-2318-46a2-bce5-9fd0a354481e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783625423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2783625423
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.345317023
Short name T103
Test name
Test status
Simulation time 1050255055 ps
CPU time 9.12 seconds
Started Aug 08 06:08:01 PM PDT 24
Finished Aug 08 06:08:10 PM PDT 24
Peak memory 212080 kb
Host smart-d47f0f01-8730-4143-a148-b242a71ce4c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=345317023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.345317023
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2514256014
Short name T82
Test name
Test status
Simulation time 579344757 ps
CPU time 17.99 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:08:32 PM PDT 24
Peak memory 216792 kb
Host smart-008b0501-2cab-47f8-b3e7-16a12de159a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514256014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2514256014
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1751403998
Short name T68
Test name
Test status
Simulation time 128510876 ps
CPU time 5.12 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:08:20 PM PDT 24
Peak memory 212064 kb
Host smart-b039c19f-ddf7-481f-b226-f893aab7741e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751403998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1751403998
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2477026917
Short name T220
Test name
Test status
Simulation time 11543227964 ps
CPU time 151.34 seconds
Started Aug 08 06:08:00 PM PDT 24
Finished Aug 08 06:10:31 PM PDT 24
Peak memory 226352 kb
Host smart-181dca6d-deab-4e5f-8bfe-f4d118fc9142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477026917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2477026917
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.506664303
Short name T183
Test name
Test status
Simulation time 175307441 ps
CPU time 9.48 seconds
Started Aug 08 06:07:58 PM PDT 24
Finished Aug 08 06:08:08 PM PDT 24
Peak memory 212864 kb
Host smart-9930b242-7027-4ac1-a29e-3213c3133b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506664303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.506664303
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.4092908965
Short name T9
Test name
Test status
Simulation time 124355171 ps
CPU time 5.52 seconds
Started Aug 08 06:08:03 PM PDT 24
Finished Aug 08 06:08:08 PM PDT 24
Peak memory 212144 kb
Host smart-28f3b610-be48-40e6-8946-e1521cfabaf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092908965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.4092908965
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3630001918
Short name T148
Test name
Test status
Simulation time 411173910 ps
CPU time 12.16 seconds
Started Aug 08 06:08:03 PM PDT 24
Finished Aug 08 06:08:15 PM PDT 24
Peak memory 214752 kb
Host smart-e3b136b8-b747-4a93-9b38-64c2534cef6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630001918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3630001918
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2834934857
Short name T108
Test name
Test status
Simulation time 7134167121 ps
CPU time 144.6 seconds
Started Aug 08 06:08:05 PM PDT 24
Finished Aug 08 06:10:29 PM PDT 24
Peak memory 223344 kb
Host smart-90e4482c-b5f2-4528-83d9-fcd0d501f875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834934857 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2834934857
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.2998984183
Short name T69
Test name
Test status
Simulation time 230083056 ps
CPU time 5.2 seconds
Started Aug 08 06:08:08 PM PDT 24
Finished Aug 08 06:08:13 PM PDT 24
Peak memory 212024 kb
Host smart-471c104b-4ae3-4abc-89ee-d16681cae761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998984183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.2998984183
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.2615011613
Short name T318
Test name
Test status
Simulation time 3186007215 ps
CPU time 152.3 seconds
Started Aug 08 06:08:00 PM PDT 24
Finished Aug 08 06:10:32 PM PDT 24
Peak memory 238540 kb
Host smart-317cabaa-02cc-4261-ae51-8e4c960821ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615011613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.2615011613
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1629887556
Short name T325
Test name
Test status
Simulation time 5191701194 ps
CPU time 15.41 seconds
Started Aug 08 06:08:13 PM PDT 24
Finished Aug 08 06:08:29 PM PDT 24
Peak memory 213464 kb
Host smart-988f3788-4796-4c13-a8e2-6f2173034bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629887556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1629887556
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.986234918
Short name T267
Test name
Test status
Simulation time 253387507 ps
CPU time 6.42 seconds
Started Aug 08 06:08:13 PM PDT 24
Finished Aug 08 06:08:19 PM PDT 24
Peak memory 212184 kb
Host smart-7fbfb132-b984-40a1-9dda-0e19a8402b32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=986234918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.986234918
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1037917628
Short name T259
Test name
Test status
Simulation time 602636408 ps
CPU time 12.74 seconds
Started Aug 08 06:08:13 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 215212 kb
Host smart-e455d02c-6e3c-48a7-a541-61623f5ffcd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037917628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1037917628
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3442391003
Short name T34
Test name
Test status
Simulation time 260062567 ps
CPU time 4.98 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:22 PM PDT 24
Peak memory 212088 kb
Host smart-fc5b9e7a-6926-46a4-a7cd-0ad62cfc9fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442391003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3442391003
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1071147564
Short name T18
Test name
Test status
Simulation time 1252958989 ps
CPU time 91 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:09:46 PM PDT 24
Peak memory 229140 kb
Host smart-8ca93c77-1f99-4f2c-aab5-0fbb3ed0e811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071147564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1071147564
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.1856098664
Short name T133
Test name
Test status
Simulation time 257306817 ps
CPU time 11.43 seconds
Started Aug 08 06:08:00 PM PDT 24
Finished Aug 08 06:08:11 PM PDT 24
Peak memory 213032 kb
Host smart-9ea4e839-3f46-4959-a296-e13741156dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856098664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.1856098664
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2792904746
Short name T157
Test name
Test status
Simulation time 103105528 ps
CPU time 5.65 seconds
Started Aug 08 06:08:08 PM PDT 24
Finished Aug 08 06:08:14 PM PDT 24
Peak memory 212120 kb
Host smart-f36e500e-5710-4571-969c-8e38e8cfad76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792904746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2792904746
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1677610354
Short name T284
Test name
Test status
Simulation time 301414946 ps
CPU time 9.04 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:08:24 PM PDT 24
Peak memory 212116 kb
Host smart-3216a999-317a-4e0c-8c48-7bd62801b1fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677610354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1677610354
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2284559683
Short name T266
Test name
Test status
Simulation time 182994042 ps
CPU time 4.29 seconds
Started Aug 08 06:08:20 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 212024 kb
Host smart-f573d4b9-a54d-4635-aac9-beb05bc91f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284559683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2284559683
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1544446878
Short name T258
Test name
Test status
Simulation time 8502394177 ps
CPU time 129.22 seconds
Started Aug 08 06:08:15 PM PDT 24
Finished Aug 08 06:10:24 PM PDT 24
Peak memory 238500 kb
Host smart-a24ad0bf-d155-4c72-90fb-78473b3aeae9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544446878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1544446878
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.614073767
Short name T49
Test name
Test status
Simulation time 177272356 ps
CPU time 9.41 seconds
Started Aug 08 06:08:16 PM PDT 24
Finished Aug 08 06:08:26 PM PDT 24
Peak memory 212860 kb
Host smart-8501ad97-8fe3-4455-865e-1641c10db5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614073767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.614073767
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1335832732
Short name T105
Test name
Test status
Simulation time 188033193 ps
CPU time 5.4 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:22 PM PDT 24
Peak memory 212104 kb
Host smart-076d2d7d-285e-43e9-86af-74bb3adba2f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335832732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1335832732
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1709329666
Short name T246
Test name
Test status
Simulation time 1231719127 ps
CPU time 12.69 seconds
Started Aug 08 06:08:19 PM PDT 24
Finished Aug 08 06:08:32 PM PDT 24
Peak memory 213292 kb
Host smart-5a252361-aad0-41f9-a72f-1fba2a17db1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709329666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1709329666
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1688658615
Short name T166
Test name
Test status
Simulation time 298920821 ps
CPU time 4.38 seconds
Started Aug 08 06:08:20 PM PDT 24
Finished Aug 08 06:08:24 PM PDT 24
Peak memory 212056 kb
Host smart-84748b8c-2c06-4eaf-9b98-6945983eeab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688658615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1688658615
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2267716430
Short name T204
Test name
Test status
Simulation time 953900603 ps
CPU time 11.09 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 212968 kb
Host smart-d96c2653-af15-4577-9e19-3edcb8eb2ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267716430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2267716430
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2296948648
Short name T181
Test name
Test status
Simulation time 144203788 ps
CPU time 6.53 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:24 PM PDT 24
Peak memory 212072 kb
Host smart-f4a712bf-50f0-4f97-b693-e84cb9d905a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296948648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2296948648
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3077347690
Short name T242
Test name
Test status
Simulation time 304391532 ps
CPU time 15.54 seconds
Started Aug 08 06:08:11 PM PDT 24
Finished Aug 08 06:08:27 PM PDT 24
Peak memory 215804 kb
Host smart-9fadb61c-7e43-449f-80a4-857f9b23632f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077347690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3077347690
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3328116897
Short name T221
Test name
Test status
Simulation time 685966934 ps
CPU time 5.02 seconds
Started Aug 08 06:07:40 PM PDT 24
Finished Aug 08 06:07:45 PM PDT 24
Peak memory 212072 kb
Host smart-8463d9b9-8099-483b-9c11-c35fb3524c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328116897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3328116897
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3181877877
Short name T190
Test name
Test status
Simulation time 33510593854 ps
CPU time 166.25 seconds
Started Aug 08 06:07:37 PM PDT 24
Finished Aug 08 06:10:23 PM PDT 24
Peak memory 239480 kb
Host smart-4b711af8-fc92-437f-8712-2428464e6a01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181877877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3181877877
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1611706855
Short name T35
Test name
Test status
Simulation time 1305984634 ps
CPU time 11.14 seconds
Started Aug 08 06:07:39 PM PDT 24
Finished Aug 08 06:07:50 PM PDT 24
Peak memory 212972 kb
Host smart-e79cc6e5-77c7-4eae-93dc-d8708ec53923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611706855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1611706855
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2301519808
Short name T330
Test name
Test status
Simulation time 197644911 ps
CPU time 5.6 seconds
Started Aug 08 06:07:39 PM PDT 24
Finished Aug 08 06:07:44 PM PDT 24
Peak memory 212168 kb
Host smart-72d099f8-a194-4e23-8192-0f9206d73540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301519808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2301519808
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.498663821
Short name T26
Test name
Test status
Simulation time 746122173 ps
CPU time 98.18 seconds
Started Aug 08 06:07:39 PM PDT 24
Finished Aug 08 06:09:17 PM PDT 24
Peak memory 237792 kb
Host smart-c2efc1fe-2211-411d-a4a2-2e0d724282be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498663821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.498663821
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3020686048
Short name T268
Test name
Test status
Simulation time 546994155 ps
CPU time 6.33 seconds
Started Aug 08 06:07:34 PM PDT 24
Finished Aug 08 06:07:41 PM PDT 24
Peak memory 212064 kb
Host smart-91de79b3-33ea-4183-811d-a9b0a75dc39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020686048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3020686048
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.835052350
Short name T247
Test name
Test status
Simulation time 404748460 ps
CPU time 11.2 seconds
Started Aug 08 06:07:32 PM PDT 24
Finished Aug 08 06:07:44 PM PDT 24
Peak memory 214728 kb
Host smart-fa9b2f47-437a-4331-ac0b-d60f871a2af8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835052350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.835052350
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2190780444
Short name T146
Test name
Test status
Simulation time 497927391 ps
CPU time 5.2 seconds
Started Aug 08 06:08:15 PM PDT 24
Finished Aug 08 06:08:20 PM PDT 24
Peak memory 212044 kb
Host smart-f85bac42-37d9-4a06-8ecd-ee113f725d96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190780444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2190780444
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3914322488
Short name T236
Test name
Test status
Simulation time 1823801683 ps
CPU time 54.44 seconds
Started Aug 08 06:08:25 PM PDT 24
Finished Aug 08 06:09:20 PM PDT 24
Peak memory 228280 kb
Host smart-821e5abd-b245-404a-97da-dec251711697
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914322488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3914322488
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1825857763
Short name T283
Test name
Test status
Simulation time 262350623 ps
CPU time 10.92 seconds
Started Aug 08 06:08:19 PM PDT 24
Finished Aug 08 06:08:30 PM PDT 24
Peak memory 212804 kb
Host smart-944ec526-4d34-4df9-a598-72b594a7fb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825857763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1825857763
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.487476203
Short name T116
Test name
Test status
Simulation time 967085823 ps
CPU time 6.72 seconds
Started Aug 08 06:08:11 PM PDT 24
Finished Aug 08 06:08:18 PM PDT 24
Peak memory 212192 kb
Host smart-acb957db-ad82-415d-b0e0-c5a0d9552629
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487476203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.487476203
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3504475892
Short name T71
Test name
Test status
Simulation time 3080695161 ps
CPU time 27.01 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:08:41 PM PDT 24
Peak memory 215828 kb
Host smart-6da63f80-9a32-4dba-9494-4cb213408224
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504475892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3504475892
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1349348228
Short name T216
Test name
Test status
Simulation time 1383604352 ps
CPU time 5 seconds
Started Aug 08 06:08:23 PM PDT 24
Finished Aug 08 06:08:28 PM PDT 24
Peak memory 212120 kb
Host smart-eb1051e1-d9c6-4060-9c7f-43dea39baed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349348228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1349348228
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.282623629
Short name T286
Test name
Test status
Simulation time 6144922281 ps
CPU time 91.3 seconds
Started Aug 08 06:08:11 PM PDT 24
Finished Aug 08 06:09:43 PM PDT 24
Peak memory 213348 kb
Host smart-48b7f02b-be70-4ef9-90b1-cecdf0c93476
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282623629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.282623629
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1669462696
Short name T150
Test name
Test status
Simulation time 175721416 ps
CPU time 9.53 seconds
Started Aug 08 06:08:11 PM PDT 24
Finished Aug 08 06:08:21 PM PDT 24
Peak memory 213000 kb
Host smart-78d4c071-f991-492b-a393-d657afe8e41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669462696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1669462696
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2369778969
Short name T228
Test name
Test status
Simulation time 277911019 ps
CPU time 6.22 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:08:21 PM PDT 24
Peak memory 212164 kb
Host smart-090aa7ab-3cd9-42c3-99dd-bd4e78906570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369778969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2369778969
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.4054549381
Short name T289
Test name
Test status
Simulation time 296710087 ps
CPU time 14.01 seconds
Started Aug 08 06:08:16 PM PDT 24
Finished Aug 08 06:08:30 PM PDT 24
Peak memory 214352 kb
Host smart-51e66bc6-37de-4ccb-b38a-47ec1b73334b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054549381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.4054549381
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3440756001
Short name T145
Test name
Test status
Simulation time 297596849 ps
CPU time 4.34 seconds
Started Aug 08 06:08:14 PM PDT 24
Finished Aug 08 06:08:18 PM PDT 24
Peak memory 212048 kb
Host smart-c7bcd52a-4b2f-4aa4-9c90-521bb1248e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440756001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3440756001
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3170600395
Short name T197
Test name
Test status
Simulation time 1080776922 ps
CPU time 73.78 seconds
Started Aug 08 06:08:16 PM PDT 24
Finished Aug 08 06:09:30 PM PDT 24
Peak memory 228852 kb
Host smart-d73ba0b8-fb4f-4227-a3b8-958d0334290c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170600395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3170600395
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2524942217
Short name T156
Test name
Test status
Simulation time 371849360 ps
CPU time 9.64 seconds
Started Aug 08 06:08:27 PM PDT 24
Finished Aug 08 06:08:37 PM PDT 24
Peak memory 212904 kb
Host smart-00804d82-d10b-49f9-874f-7412ca0f5238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524942217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2524942217
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2532741979
Short name T144
Test name
Test status
Simulation time 541302892 ps
CPU time 6.4 seconds
Started Aug 08 06:08:33 PM PDT 24
Finished Aug 08 06:08:40 PM PDT 24
Peak memory 212108 kb
Host smart-7c8924e6-dab7-4d78-b581-d5776574557d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532741979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2532741979
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.4119527132
Short name T328
Test name
Test status
Simulation time 489159498 ps
CPU time 9.53 seconds
Started Aug 08 06:08:19 PM PDT 24
Finished Aug 08 06:08:29 PM PDT 24
Peak memory 212424 kb
Host smart-b9bad149-19c5-43cd-ac10-3a983f093ec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119527132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.4119527132
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.680788256
Short name T301
Test name
Test status
Simulation time 321483464 ps
CPU time 4.16 seconds
Started Aug 08 06:08:11 PM PDT 24
Finished Aug 08 06:08:15 PM PDT 24
Peak memory 212028 kb
Host smart-0e62ca6d-3046-4dc8-bac3-b023651b0629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680788256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.680788256
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1178358341
Short name T152
Test name
Test status
Simulation time 347928601 ps
CPU time 9.59 seconds
Started Aug 08 06:08:10 PM PDT 24
Finished Aug 08 06:08:20 PM PDT 24
Peak memory 213020 kb
Host smart-44dc39c1-05bc-4d3d-90c9-dfaa9ff32ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178358341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1178358341
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1863183334
Short name T44
Test name
Test status
Simulation time 1422186999 ps
CPU time 8.48 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:26 PM PDT 24
Peak memory 212168 kb
Host smart-409181d0-5dbf-43e0-acc8-4e84145854e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863183334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1863183334
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.3647940710
Short name T269
Test name
Test status
Simulation time 297817639 ps
CPU time 12.73 seconds
Started Aug 08 06:08:15 PM PDT 24
Finished Aug 08 06:08:28 PM PDT 24
Peak memory 215556 kb
Host smart-6983b603-471d-4668-9bcc-cd14e5fe902e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647940710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.3647940710
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3576350385
Short name T214
Test name
Test status
Simulation time 149099030663 ps
CPU time 3033.77 seconds
Started Aug 08 06:08:21 PM PDT 24
Finished Aug 08 06:58:55 PM PDT 24
Peak memory 248820 kb
Host smart-cc4b572c-cf31-46ba-ac76-dc93aafb02cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576350385 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3576350385
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.4019702269
Short name T263
Test name
Test status
Simulation time 826247074 ps
CPU time 5.07 seconds
Started Aug 08 06:08:12 PM PDT 24
Finished Aug 08 06:08:17 PM PDT 24
Peak memory 212092 kb
Host smart-72cfb332-7925-4218-a949-3e4b8019126a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019702269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4019702269
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3925701883
Short name T294
Test name
Test status
Simulation time 4811188447 ps
CPU time 83.47 seconds
Started Aug 08 06:08:15 PM PDT 24
Finished Aug 08 06:09:39 PM PDT 24
Peak memory 238376 kb
Host smart-b5b39872-cd19-4022-871e-54673e798a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925701883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3925701883
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3601609721
Short name T323
Test name
Test status
Simulation time 520234744 ps
CPU time 11.46 seconds
Started Aug 08 06:08:12 PM PDT 24
Finished Aug 08 06:08:24 PM PDT 24
Peak memory 212800 kb
Host smart-9e6b6463-5f2e-4ed5-bae9-1c92fa5789d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601609721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3601609721
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1326670602
Short name T162
Test name
Test status
Simulation time 192015027 ps
CPU time 5.64 seconds
Started Aug 08 06:08:10 PM PDT 24
Finished Aug 08 06:08:16 PM PDT 24
Peak memory 212172 kb
Host smart-ac3b57a3-ff5b-4f2b-91a5-c6794b3d47bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326670602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1326670602
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.2431974336
Short name T248
Test name
Test status
Simulation time 122692313 ps
CPU time 7.87 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 211960 kb
Host smart-48401180-de20-42cb-9db5-a76760880a0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431974336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.2431974336
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3947884969
Short name T59
Test name
Test status
Simulation time 114663488631 ps
CPU time 728.14 seconds
Started Aug 08 06:08:15 PM PDT 24
Finished Aug 08 06:20:24 PM PDT 24
Peak memory 236632 kb
Host smart-fe2048cb-08fb-4ef2-a299-36a88a3bcf84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947884969 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3947884969
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3608487790
Short name T254
Test name
Test status
Simulation time 2064959086 ps
CPU time 5.06 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:23 PM PDT 24
Peak memory 212032 kb
Host smart-f53a415f-f73e-4263-ada3-7190d1056a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608487790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3608487790
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.24392684
Short name T203
Test name
Test status
Simulation time 15222246368 ps
CPU time 56.56 seconds
Started Aug 08 06:08:20 PM PDT 24
Finished Aug 08 06:09:17 PM PDT 24
Peak memory 229296 kb
Host smart-9b3aea4e-cb22-48d9-8ee9-17d28d3fb008
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24392684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_co
rrupt_sig_fatal_chk.24392684
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.598917345
Short name T290
Test name
Test status
Simulation time 497883673 ps
CPU time 11.39 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:29 PM PDT 24
Peak memory 212940 kb
Host smart-3eac4e03-aee4-4330-8790-8e70b7659589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598917345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.598917345
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.736268943
Short name T137
Test name
Test status
Simulation time 1216294388 ps
CPU time 6.06 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:23 PM PDT 24
Peak memory 212108 kb
Host smart-4ef540ef-d146-4c14-bbc9-972f7937af10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=736268943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.736268943
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.614078696
Short name T110
Test name
Test status
Simulation time 301375142 ps
CPU time 12.29 seconds
Started Aug 08 06:08:10 PM PDT 24
Finished Aug 08 06:08:22 PM PDT 24
Peak memory 215064 kb
Host smart-6bf84b4f-2789-4460-ac92-4c3266d5c135
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614078696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.614078696
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2715360096
Short name T200
Test name
Test status
Simulation time 437400110 ps
CPU time 4.37 seconds
Started Aug 08 06:08:19 PM PDT 24
Finished Aug 08 06:08:23 PM PDT 24
Peak memory 212084 kb
Host smart-5e82c0b9-e92f-41b9-816c-7a27fd681f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715360096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2715360096
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1438401930
Short name T235
Test name
Test status
Simulation time 10900247713 ps
CPU time 95.57 seconds
Started Aug 08 06:08:21 PM PDT 24
Finished Aug 08 06:09:57 PM PDT 24
Peak memory 238420 kb
Host smart-2c4c7854-9866-4c4e-b153-37265249eed4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438401930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1438401930
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3503919027
Short name T232
Test name
Test status
Simulation time 1383899951 ps
CPU time 11.64 seconds
Started Aug 08 06:08:21 PM PDT 24
Finished Aug 08 06:08:32 PM PDT 24
Peak memory 212932 kb
Host smart-83658941-99f0-4385-a22b-6f9d00021502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503919027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3503919027
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2813143409
Short name T195
Test name
Test status
Simulation time 269565484 ps
CPU time 6.33 seconds
Started Aug 08 06:08:18 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 212128 kb
Host smart-97b2e852-be51-49a7-9789-d7393a10174b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813143409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2813143409
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1821172237
Short name T15
Test name
Test status
Simulation time 1498466807 ps
CPU time 15 seconds
Started Aug 08 06:08:16 PM PDT 24
Finished Aug 08 06:08:31 PM PDT 24
Peak memory 215192 kb
Host smart-2e816516-6731-442e-88cb-92ee32770c94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821172237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1821172237
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1667776031
Short name T53
Test name
Test status
Simulation time 28661989612 ps
CPU time 1200.36 seconds
Started Aug 08 06:08:18 PM PDT 24
Finished Aug 08 06:28:19 PM PDT 24
Peak memory 236592 kb
Host smart-232b7fb5-d56a-48b9-815d-306f1dcd7221
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667776031 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1667776031
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2245566886
Short name T285
Test name
Test status
Simulation time 97849998 ps
CPU time 4.22 seconds
Started Aug 08 06:08:21 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 212092 kb
Host smart-b998611a-8797-423d-bd99-7a1557a39113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245566886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2245566886
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1448361889
Short name T315
Test name
Test status
Simulation time 16425322378 ps
CPU time 139.26 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:10:36 PM PDT 24
Peak memory 234828 kb
Host smart-48b21f2b-6d34-40a7-b1d6-7554eb55c70b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448361889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1448361889
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1740590077
Short name T273
Test name
Test status
Simulation time 1040088613 ps
CPU time 11.05 seconds
Started Aug 08 06:08:17 PM PDT 24
Finished Aug 08 06:08:28 PM PDT 24
Peak memory 212864 kb
Host smart-d3244eac-9440-490e-aeb9-e47bd2350809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740590077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1740590077
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1422944711
Short name T264
Test name
Test status
Simulation time 99488661 ps
CPU time 5.62 seconds
Started Aug 08 06:08:25 PM PDT 24
Finished Aug 08 06:08:31 PM PDT 24
Peak memory 212144 kb
Host smart-495c5502-27d6-4855-8fc0-ce0a2beebf09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422944711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1422944711
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.108382428
Short name T169
Test name
Test status
Simulation time 430602890 ps
CPU time 19.8 seconds
Started Aug 08 06:08:15 PM PDT 24
Finished Aug 08 06:08:35 PM PDT 24
Peak memory 216368 kb
Host smart-e4fcd762-05f1-48a6-a732-33e2a09137f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108382428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.108382428
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3568956017
Short name T212
Test name
Test status
Simulation time 78508508021 ps
CPU time 3133.38 seconds
Started Aug 08 06:08:21 PM PDT 24
Finished Aug 08 07:00:35 PM PDT 24
Peak memory 230436 kb
Host smart-f63a13eb-a3bf-44ca-8d8a-0d18f8bc70e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568956017 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3568956017
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2817043967
Short name T143
Test name
Test status
Simulation time 128078731 ps
CPU time 5.03 seconds
Started Aug 08 06:08:20 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 212084 kb
Host smart-b54af9b0-a66e-4d59-812d-eb2683c4f8d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817043967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2817043967
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3318321519
Short name T261
Test name
Test status
Simulation time 4987104500 ps
CPU time 126.66 seconds
Started Aug 08 06:08:21 PM PDT 24
Finished Aug 08 06:10:27 PM PDT 24
Peak memory 238464 kb
Host smart-8831a2c8-a9ed-414c-84d8-2fc53adb7284
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318321519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3318321519
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3396971012
Short name T50
Test name
Test status
Simulation time 1511945464 ps
CPU time 9.64 seconds
Started Aug 08 06:08:15 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 212180 kb
Host smart-7920ba51-9065-4149-8fb6-a72b6416ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396971012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3396971012
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2872329161
Short name T182
Test name
Test status
Simulation time 376910094 ps
CPU time 5.76 seconds
Started Aug 08 06:08:16 PM PDT 24
Finished Aug 08 06:08:22 PM PDT 24
Peak memory 212104 kb
Host smart-a892deb5-499b-4bd1-98a2-576f53efad37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872329161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2872329161
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2972678091
Short name T161
Test name
Test status
Simulation time 1361804391 ps
CPU time 8.48 seconds
Started Aug 08 06:08:21 PM PDT 24
Finished Aug 08 06:08:29 PM PDT 24
Peak memory 213152 kb
Host smart-48f46f3b-9604-46c9-847b-332678939fb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972678091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2972678091
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.391526388
Short name T176
Test name
Test status
Simulation time 379126459 ps
CPU time 4.19 seconds
Started Aug 08 06:08:21 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 212028 kb
Host smart-9051d1b9-c9b8-4a0f-8f3c-9a49821c444c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391526388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.391526388
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.474679000
Short name T310
Test name
Test status
Simulation time 2569330581 ps
CPU time 86.42 seconds
Started Aug 08 06:08:23 PM PDT 24
Finished Aug 08 06:09:50 PM PDT 24
Peak memory 237856 kb
Host smart-e4754455-f235-4039-8d83-ce91093d3ac7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474679000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.474679000
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2148366544
Short name T159
Test name
Test status
Simulation time 501331420 ps
CPU time 11.16 seconds
Started Aug 08 06:08:21 PM PDT 24
Finished Aug 08 06:08:32 PM PDT 24
Peak memory 214172 kb
Host smart-09785810-33b7-49a6-baf5-0d148445f7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148366544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2148366544
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.995823228
Short name T207
Test name
Test status
Simulation time 280959017 ps
CPU time 5.9 seconds
Started Aug 08 06:08:19 PM PDT 24
Finished Aug 08 06:08:25 PM PDT 24
Peak memory 212192 kb
Host smart-b0e0f865-0204-4164-8658-940c05ec2f68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995823228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.995823228
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1721782838
Short name T288
Test name
Test status
Simulation time 362189596 ps
CPU time 20.11 seconds
Started Aug 08 06:08:26 PM PDT 24
Finished Aug 08 06:08:46 PM PDT 24
Peak memory 215012 kb
Host smart-f893a7a0-5f1d-4581-845a-7de2dd4451df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721782838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1721782838
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3257316973
Short name T255
Test name
Test status
Simulation time 357429877 ps
CPU time 5.12 seconds
Started Aug 08 06:07:44 PM PDT 24
Finished Aug 08 06:07:50 PM PDT 24
Peak memory 212084 kb
Host smart-c38f8afe-29f3-4e72-8a1c-eb90db1b4002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257316973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3257316973
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3666130417
Short name T238
Test name
Test status
Simulation time 2796093554 ps
CPU time 139.55 seconds
Started Aug 08 06:07:42 PM PDT 24
Finished Aug 08 06:10:01 PM PDT 24
Peak memory 241344 kb
Host smart-694c3f67-1d37-4c2f-80b2-15691df4a962
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666130417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3666130417
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1614135139
Short name T164
Test name
Test status
Simulation time 173406440 ps
CPU time 9.39 seconds
Started Aug 08 06:07:38 PM PDT 24
Finished Aug 08 06:07:47 PM PDT 24
Peak memory 213464 kb
Host smart-a1f8eba4-3f9a-4af2-af1a-b590ec8237ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614135139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1614135139
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2561000986
Short name T227
Test name
Test status
Simulation time 1305542946 ps
CPU time 5.65 seconds
Started Aug 08 06:07:39 PM PDT 24
Finished Aug 08 06:07:45 PM PDT 24
Peak memory 212196 kb
Host smart-e89015fd-60ac-4d26-af84-01fa1ea367f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561000986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2561000986
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.808264727
Short name T215
Test name
Test status
Simulation time 568136495 ps
CPU time 6.13 seconds
Started Aug 08 06:07:41 PM PDT 24
Finished Aug 08 06:07:47 PM PDT 24
Peak memory 212204 kb
Host smart-ad5c8380-f404-47fd-91c5-8a54a7726355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808264727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.808264727
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2412211632
Short name T276
Test name
Test status
Simulation time 135862694 ps
CPU time 5.13 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:07:50 PM PDT 24
Peak memory 212108 kb
Host smart-f5eaff69-2411-4853-be7f-e4931f1884b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412211632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2412211632
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1843140082
Short name T43
Test name
Test status
Simulation time 11956225834 ps
CPU time 193.91 seconds
Started Aug 08 06:07:43 PM PDT 24
Finished Aug 08 06:10:58 PM PDT 24
Peak memory 238580 kb
Host smart-c4822108-5787-4d41-950e-28512437555d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843140082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1843140082
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.519751220
Short name T280
Test name
Test status
Simulation time 969414987 ps
CPU time 11.42 seconds
Started Aug 08 06:07:36 PM PDT 24
Finished Aug 08 06:07:47 PM PDT 24
Peak memory 216048 kb
Host smart-1c008579-2732-4128-b4d1-b22b9a5af391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519751220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.519751220
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2051907827
Short name T48
Test name
Test status
Simulation time 138297241 ps
CPU time 6.41 seconds
Started Aug 08 06:07:39 PM PDT 24
Finished Aug 08 06:07:46 PM PDT 24
Peak memory 212196 kb
Host smart-72b81299-e912-4140-af11-ff5c267dd2a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051907827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2051907827
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3298250414
Short name T168
Test name
Test status
Simulation time 102739240 ps
CPU time 5.64 seconds
Started Aug 08 06:07:41 PM PDT 24
Finished Aug 08 06:07:47 PM PDT 24
Peak memory 212096 kb
Host smart-5a31d31d-68dc-46be-b1cc-d1c98c88ce41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298250414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3298250414
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1569065678
Short name T29
Test name
Test status
Simulation time 238278900 ps
CPU time 12.82 seconds
Started Aug 08 06:07:43 PM PDT 24
Finished Aug 08 06:07:56 PM PDT 24
Peak memory 214244 kb
Host smart-2a38effd-632c-4d70-be3e-9fa995f178e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569065678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1569065678
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2452740669
Short name T297
Test name
Test status
Simulation time 51606333370 ps
CPU time 2123.8 seconds
Started Aug 08 06:07:44 PM PDT 24
Finished Aug 08 06:43:08 PM PDT 24
Peak memory 236704 kb
Host smart-4d0f7bc2-2fb6-40c4-9389-32525fc609c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452740669 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2452740669
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1139881285
Short name T251
Test name
Test status
Simulation time 127539357 ps
CPU time 5.04 seconds
Started Aug 08 06:07:41 PM PDT 24
Finished Aug 08 06:07:46 PM PDT 24
Peak memory 212064 kb
Host smart-86d5826d-95d0-4a14-824b-114ad2a3ec2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139881285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1139881285
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.355874061
Short name T189
Test name
Test status
Simulation time 17488260086 ps
CPU time 140.98 seconds
Started Aug 08 06:07:40 PM PDT 24
Finished Aug 08 06:10:01 PM PDT 24
Peak memory 235548 kb
Host smart-979729c6-b7e8-4675-8dd5-128b301d35d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355874061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.355874061
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.618724992
Short name T198
Test name
Test status
Simulation time 255215766 ps
CPU time 11.48 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:07:57 PM PDT 24
Peak memory 212892 kb
Host smart-ab5963ea-372e-412c-9d96-18b61e92e352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618724992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.618724992
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1676990448
Short name T271
Test name
Test status
Simulation time 1219367513 ps
CPU time 6.44 seconds
Started Aug 08 06:07:38 PM PDT 24
Finished Aug 08 06:07:49 PM PDT 24
Peak memory 212184 kb
Host smart-99d8e69f-b704-4c02-8eee-dc7fbfcb1b2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1676990448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1676990448
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2745212552
Short name T80
Test name
Test status
Simulation time 349966406 ps
CPU time 5.52 seconds
Started Aug 08 06:07:40 PM PDT 24
Finished Aug 08 06:07:46 PM PDT 24
Peak memory 212148 kb
Host smart-a5c9504d-699e-448b-966f-284fe129e588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745212552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2745212552
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1909428621
Short name T322
Test name
Test status
Simulation time 1184549659 ps
CPU time 16.29 seconds
Started Aug 08 06:07:43 PM PDT 24
Finished Aug 08 06:07:59 PM PDT 24
Peak memory 215060 kb
Host smart-b66c27f0-eb8c-4a7c-a043-e89f5f20fac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909428621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1909428621
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.599192060
Short name T225
Test name
Test status
Simulation time 40640695253 ps
CPU time 863.34 seconds
Started Aug 08 06:07:53 PM PDT 24
Finished Aug 08 06:22:17 PM PDT 24
Peak memory 236436 kb
Host smart-1b70ba6d-72f7-4390-97dd-094e2853eab4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599192060 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.599192060
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1693980603
Short name T36
Test name
Test status
Simulation time 1238749216 ps
CPU time 5.25 seconds
Started Aug 08 06:07:43 PM PDT 24
Finished Aug 08 06:07:49 PM PDT 24
Peak memory 212056 kb
Host smart-4c77978c-bc89-4794-9f8b-63518d45ac11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693980603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1693980603
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.641233399
Short name T306
Test name
Test status
Simulation time 9563846267 ps
CPU time 118.51 seconds
Started Aug 08 06:07:40 PM PDT 24
Finished Aug 08 06:09:39 PM PDT 24
Peak memory 238556 kb
Host smart-3bc046b3-7627-4adc-990f-eaa81f995c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641233399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_co
rrupt_sig_fatal_chk.641233399
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2149275904
Short name T206
Test name
Test status
Simulation time 1521626022 ps
CPU time 9.38 seconds
Started Aug 08 06:07:49 PM PDT 24
Finished Aug 08 06:07:58 PM PDT 24
Peak memory 212976 kb
Host smart-0121bc17-d98d-48e7-9fcb-33a66cf3105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149275904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2149275904
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2572837614
Short name T304
Test name
Test status
Simulation time 406728291 ps
CPU time 5.43 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:07:50 PM PDT 24
Peak memory 212192 kb
Host smart-d77c4d62-501d-4971-a9bc-63a6fb822856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2572837614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2572837614
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3544386343
Short name T226
Test name
Test status
Simulation time 100937058 ps
CPU time 5.54 seconds
Started Aug 08 06:07:45 PM PDT 24
Finished Aug 08 06:07:51 PM PDT 24
Peak memory 212180 kb
Host smart-1ac31874-3142-42df-957f-3aabed719bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544386343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3544386343
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3480816202
Short name T281
Test name
Test status
Simulation time 388314838 ps
CPU time 21.91 seconds
Started Aug 08 06:07:42 PM PDT 24
Finished Aug 08 06:08:04 PM PDT 24
Peak memory 216196 kb
Host smart-b0b2791e-5fa5-4a63-8408-c72c50971047
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480816202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3480816202
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.37968165
Short name T60
Test name
Test status
Simulation time 2057774676 ps
CPU time 5.06 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:07:52 PM PDT 24
Peak memory 212116 kb
Host smart-21be3565-844c-488d-bea1-a965f14d9326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37968165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.37968165
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.251849913
Short name T31
Test name
Test status
Simulation time 2886145845 ps
CPU time 79.72 seconds
Started Aug 08 06:07:41 PM PDT 24
Finished Aug 08 06:09:01 PM PDT 24
Peak memory 212752 kb
Host smart-fbf9ec1b-0fc1-4f1c-8ed9-dd3d4411dd1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251849913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.251849913
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4042511484
Short name T219
Test name
Test status
Simulation time 254977877 ps
CPU time 11.28 seconds
Started Aug 08 06:07:51 PM PDT 24
Finished Aug 08 06:08:02 PM PDT 24
Peak memory 212908 kb
Host smart-43024fad-2069-4372-bf2d-f37dace1c907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042511484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4042511484
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1938136230
Short name T135
Test name
Test status
Simulation time 137423345 ps
CPU time 6.11 seconds
Started Aug 08 06:07:38 PM PDT 24
Finished Aug 08 06:07:45 PM PDT 24
Peak memory 212200 kb
Host smart-5e163140-749c-47e9-b6f9-8967ce6f91f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938136230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1938136230
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3034983466
Short name T83
Test name
Test status
Simulation time 537205867 ps
CPU time 6.56 seconds
Started Aug 08 06:07:41 PM PDT 24
Finished Aug 08 06:07:48 PM PDT 24
Peak memory 212168 kb
Host smart-753f04f1-2f5e-4059-8461-2a3c09600b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034983466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3034983466
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3550085635
Short name T201
Test name
Test status
Simulation time 693594718 ps
CPU time 9.67 seconds
Started Aug 08 06:07:47 PM PDT 24
Finished Aug 08 06:07:57 PM PDT 24
Peak memory 213180 kb
Host smart-115d267f-7c71-4aa8-9171-f5b5fb6c14ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550085635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3550085635
Directory /workspace/9.rom_ctrl_stress_all/latest
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