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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 96.89 91.99 97.67 100.00 98.28 97.30 98.37


Total test records in report: 428
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T303 /workspace/coverage/default/25.rom_ctrl_stress_all.895990928 Aug 09 07:26:28 PM PDT 24 Aug 09 07:26:45 PM PDT 24 631208264 ps
T304 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.751482616 Aug 09 07:26:58 PM PDT 24 Aug 09 07:40:27 PM PDT 24 49576981606 ps
T305 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2162744546 Aug 09 07:25:39 PM PDT 24 Aug 09 07:26:51 PM PDT 24 1695832183 ps
T306 /workspace/coverage/default/28.rom_ctrl_stress_all.3474218776 Aug 09 07:26:37 PM PDT 24 Aug 09 07:26:50 PM PDT 24 200646444 ps
T307 /workspace/coverage/default/19.rom_ctrl_stress_all.93750526 Aug 09 07:26:12 PM PDT 24 Aug 09 07:26:26 PM PDT 24 229913471 ps
T308 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.811324756 Aug 09 07:25:40 PM PDT 24 Aug 09 07:25:47 PM PDT 24 149006494 ps
T309 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1460802003 Aug 09 07:26:14 PM PDT 24 Aug 09 07:26:26 PM PDT 24 2768771628 ps
T310 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.405553122 Aug 09 07:26:51 PM PDT 24 Aug 09 07:26:57 PM PDT 24 101112623 ps
T26 /workspace/coverage/default/3.rom_ctrl_sec_cm.4014586999 Aug 09 07:25:39 PM PDT 24 Aug 09 07:27:32 PM PDT 24 861347853 ps
T311 /workspace/coverage/default/16.rom_ctrl_alert_test.1827227120 Aug 09 07:26:12 PM PDT 24 Aug 09 07:26:18 PM PDT 24 244995749 ps
T312 /workspace/coverage/default/8.rom_ctrl_stress_all.3787822688 Aug 09 07:25:51 PM PDT 24 Aug 09 07:26:04 PM PDT 24 373228947 ps
T313 /workspace/coverage/default/13.rom_ctrl_stress_all.2707403597 Aug 09 07:26:02 PM PDT 24 Aug 09 07:26:14 PM PDT 24 315805443 ps
T314 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2515986288 Aug 09 07:26:12 PM PDT 24 Aug 09 07:26:18 PM PDT 24 140030494 ps
T30 /workspace/coverage/default/0.rom_ctrl_sec_cm.3237568933 Aug 09 07:25:20 PM PDT 24 Aug 09 07:26:13 PM PDT 24 207371139 ps
T315 /workspace/coverage/default/35.rom_ctrl_alert_test.4040172282 Aug 09 07:26:44 PM PDT 24 Aug 09 07:26:48 PM PDT 24 87519688 ps
T316 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.772734131 Aug 09 07:26:19 PM PDT 24 Aug 09 07:26:29 PM PDT 24 665886937 ps
T317 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3526903904 Aug 09 07:27:11 PM PDT 24 Aug 09 07:28:48 PM PDT 24 21920517984 ps
T31 /workspace/coverage/default/4.rom_ctrl_sec_cm.3560054698 Aug 09 07:25:40 PM PDT 24 Aug 09 07:26:34 PM PDT 24 204900648 ps
T318 /workspace/coverage/default/35.rom_ctrl_stress_all.3532289167 Aug 09 07:26:57 PM PDT 24 Aug 09 07:27:10 PM PDT 24 273665609 ps
T319 /workspace/coverage/default/38.rom_ctrl_stress_all.1286808699 Aug 09 07:26:54 PM PDT 24 Aug 09 07:27:03 PM PDT 24 172146651 ps
T320 /workspace/coverage/default/2.rom_ctrl_alert_test.2516649149 Aug 09 07:25:26 PM PDT 24 Aug 09 07:25:30 PM PDT 24 168520345 ps
T321 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2620941177 Aug 09 07:26:51 PM PDT 24 Aug 09 07:26:58 PM PDT 24 553178248 ps
T322 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3470432091 Aug 09 07:26:58 PM PDT 24 Aug 09 07:27:49 PM PDT 24 3432033410 ps
T323 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2691011598 Aug 09 07:26:27 PM PDT 24 Aug 09 07:27:44 PM PDT 24 4132766522 ps
T324 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1226105230 Aug 09 07:25:18 PM PDT 24 Aug 09 07:25:29 PM PDT 24 251982386 ps
T325 /workspace/coverage/default/47.rom_ctrl_stress_all.3885718192 Aug 09 07:27:09 PM PDT 24 Aug 09 07:27:21 PM PDT 24 350852527 ps
T326 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1272685689 Aug 09 07:26:10 PM PDT 24 Aug 09 07:26:16 PM PDT 24 463335304 ps
T327 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.861319571 Aug 09 07:27:11 PM PDT 24 Aug 09 07:27:18 PM PDT 24 143606750 ps
T328 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1332900662 Aug 09 07:25:50 PM PDT 24 Aug 09 07:46:42 PM PDT 24 28011858454 ps
T329 /workspace/coverage/default/31.rom_ctrl_stress_all.2627585736 Aug 09 07:26:38 PM PDT 24 Aug 09 07:26:55 PM PDT 24 286229603 ps
T330 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1659693110 Aug 09 07:25:52 PM PDT 24 Aug 09 07:26:45 PM PDT 24 2047849127 ps
T331 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2788961618 Aug 09 07:26:35 PM PDT 24 Aug 09 07:26:42 PM PDT 24 141870298 ps
T332 /workspace/coverage/default/21.rom_ctrl_alert_test.1691055469 Aug 09 07:26:19 PM PDT 24 Aug 09 07:26:24 PM PDT 24 496680194 ps
T61 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1392622106 Aug 09 05:16:48 PM PDT 24 Aug 09 05:16:53 PM PDT 24 519107894 ps
T62 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2745103950 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:27 PM PDT 24 168704253 ps
T63 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3197425180 Aug 09 05:16:42 PM PDT 24 Aug 09 05:16:47 PM PDT 24 196460661 ps
T104 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.416839896 Aug 09 05:16:24 PM PDT 24 Aug 09 05:16:29 PM PDT 24 127096698 ps
T57 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4140109752 Aug 09 05:16:32 PM PDT 24 Aug 09 05:17:41 PM PDT 24 485330938 ps
T71 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4060006947 Aug 09 05:16:44 PM PDT 24 Aug 09 05:17:17 PM PDT 24 3934039699 ps
T72 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1083435132 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:27 PM PDT 24 87043154 ps
T333 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.118172518 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:36 PM PDT 24 1185430071 ps
T334 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1931188459 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:31 PM PDT 24 90443076 ps
T73 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2723432968 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:41 PM PDT 24 733333805 ps
T74 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.301091832 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:36 PM PDT 24 483151168 ps
T335 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2616006607 Aug 09 05:16:44 PM PDT 24 Aug 09 05:16:49 PM PDT 24 103431133 ps
T75 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3461600502 Aug 09 05:16:42 PM PDT 24 Aug 09 05:16:48 PM PDT 24 495751929 ps
T102 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.767469324 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:28 PM PDT 24 174987722 ps
T58 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3354099494 Aug 09 05:16:20 PM PDT 24 Aug 09 05:17:28 PM PDT 24 248263110 ps
T105 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.547308847 Aug 09 05:16:19 PM PDT 24 Aug 09 05:16:23 PM PDT 24 178853870 ps
T336 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2471806195 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:27 PM PDT 24 697320290 ps
T76 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2037624592 Aug 09 05:16:40 PM PDT 24 Aug 09 05:16:44 PM PDT 24 336429104 ps
T337 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4074661700 Aug 09 05:16:12 PM PDT 24 Aug 09 05:16:16 PM PDT 24 379740129 ps
T338 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3261191770 Aug 09 05:16:24 PM PDT 24 Aug 09 05:16:32 PM PDT 24 93386954 ps
T339 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2449289376 Aug 09 05:16:43 PM PDT 24 Aug 09 05:16:49 PM PDT 24 602741369 ps
T59 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4114999272 Aug 09 05:16:34 PM PDT 24 Aug 09 05:17:11 PM PDT 24 316648814 ps
T77 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3726134084 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:28 PM PDT 24 85446828 ps
T340 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3188647851 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:35 PM PDT 24 372628743 ps
T78 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1803011200 Aug 09 05:16:12 PM PDT 24 Aug 09 05:16:17 PM PDT 24 336410804 ps
T341 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.619575654 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:37 PM PDT 24 315755831 ps
T79 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1666955654 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:35 PM PDT 24 85504401 ps
T342 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1336873481 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:38 PM PDT 24 512346905 ps
T80 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1545104095 Aug 09 05:16:34 PM PDT 24 Aug 09 05:16:38 PM PDT 24 269385949 ps
T111 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.667901225 Aug 09 05:16:31 PM PDT 24 Aug 09 05:17:41 PM PDT 24 494118868 ps
T87 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.375999436 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:59 PM PDT 24 575903673 ps
T112 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3170771047 Aug 09 05:16:41 PM PDT 24 Aug 09 05:17:51 PM PDT 24 2527944540 ps
T109 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.357681951 Aug 09 05:16:42 PM PDT 24 Aug 09 05:17:51 PM PDT 24 1067867009 ps
T343 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1342837773 Aug 09 05:16:28 PM PDT 24 Aug 09 05:16:34 PM PDT 24 134257562 ps
T344 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.990619292 Aug 09 05:16:24 PM PDT 24 Aug 09 05:16:34 PM PDT 24 533935935 ps
T103 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3718703185 Aug 09 05:16:22 PM PDT 24 Aug 09 05:16:29 PM PDT 24 140538519 ps
T107 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3601870012 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:51 PM PDT 24 616669967 ps
T345 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.29941265 Aug 09 05:16:40 PM PDT 24 Aug 09 05:16:44 PM PDT 24 380710258 ps
T346 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1035328592 Aug 09 05:16:22 PM PDT 24 Aug 09 05:16:27 PM PDT 24 134424906 ps
T347 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2419957201 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:35 PM PDT 24 168461025 ps
T348 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2488854981 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:33 PM PDT 24 1716852097 ps
T349 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.458422913 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:36 PM PDT 24 87002365 ps
T88 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2202755100 Aug 09 05:16:12 PM PDT 24 Aug 09 05:16:40 PM PDT 24 1879024697 ps
T89 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3241370960 Aug 09 05:16:24 PM PDT 24 Aug 09 05:16:46 PM PDT 24 1091110109 ps
T350 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3788674736 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:30 PM PDT 24 152582495 ps
T351 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2911251539 Aug 09 05:16:29 PM PDT 24 Aug 09 05:16:35 PM PDT 24 147991610 ps
T352 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2769121319 Aug 09 05:16:12 PM PDT 24 Aug 09 05:16:17 PM PDT 24 727656361 ps
T353 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2469128599 Aug 09 05:16:39 PM PDT 24 Aug 09 05:16:46 PM PDT 24 144666282 ps
T90 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.795283422 Aug 09 05:16:40 PM PDT 24 Aug 09 05:16:59 PM PDT 24 3956993377 ps
T354 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1795711901 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:41 PM PDT 24 521524530 ps
T355 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2705793802 Aug 09 05:16:12 PM PDT 24 Aug 09 05:16:21 PM PDT 24 378756827 ps
T117 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1017871523 Aug 09 05:16:11 PM PDT 24 Aug 09 05:16:48 PM PDT 24 400750502 ps
T113 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.659852459 Aug 09 05:16:25 PM PDT 24 Aug 09 05:17:37 PM PDT 24 665352439 ps
T356 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1240967446 Aug 09 05:16:21 PM PDT 24 Aug 09 05:16:30 PM PDT 24 539251281 ps
T357 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.617223900 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:38 PM PDT 24 650411093 ps
T118 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1932694770 Aug 09 05:16:42 PM PDT 24 Aug 09 05:17:19 PM PDT 24 201052360 ps
T114 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3334180945 Aug 09 05:16:43 PM PDT 24 Aug 09 05:17:53 PM PDT 24 205592384 ps
T358 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3214292320 Aug 09 05:16:19 PM PDT 24 Aug 09 05:16:24 PM PDT 24 926132302 ps
T359 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3976908911 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:36 PM PDT 24 142425981 ps
T91 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.382142792 Aug 09 05:16:13 PM PDT 24 Aug 09 05:16:18 PM PDT 24 775049434 ps
T360 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1582350615 Aug 09 05:16:34 PM PDT 24 Aug 09 05:16:38 PM PDT 24 85846115 ps
T92 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2610342867 Aug 09 05:16:32 PM PDT 24 Aug 09 05:16:52 PM PDT 24 746519356 ps
T361 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2606147684 Aug 09 05:16:12 PM PDT 24 Aug 09 05:16:20 PM PDT 24 2537678490 ps
T93 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3006990608 Aug 09 05:16:31 PM PDT 24 Aug 09 05:17:04 PM PDT 24 4098957153 ps
T362 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.583751897 Aug 09 05:16:29 PM PDT 24 Aug 09 05:17:02 PM PDT 24 1712203725 ps
T119 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1391897159 Aug 09 05:16:22 PM PDT 24 Aug 09 05:17:31 PM PDT 24 929388574 ps
T363 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3442451552 Aug 09 05:16:32 PM PDT 24 Aug 09 05:17:43 PM PDT 24 2478010271 ps
T364 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1792407735 Aug 09 05:16:21 PM PDT 24 Aug 09 05:16:26 PM PDT 24 126297258 ps
T365 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3465303498 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:36 PM PDT 24 89298037 ps
T100 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3571130448 Aug 09 05:16:48 PM PDT 24 Aug 09 05:16:53 PM PDT 24 126667686 ps
T366 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3754127210 Aug 09 05:16:24 PM PDT 24 Aug 09 05:16:32 PM PDT 24 90216502 ps
T367 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3841698181 Aug 09 05:16:32 PM PDT 24 Aug 09 05:16:42 PM PDT 24 180973655 ps
T101 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3921196531 Aug 09 05:16:20 PM PDT 24 Aug 09 05:16:47 PM PDT 24 1915729674 ps
T368 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2227481535 Aug 09 05:16:21 PM PDT 24 Aug 09 05:16:25 PM PDT 24 87153551 ps
T369 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2285142964 Aug 09 05:16:21 PM PDT 24 Aug 09 05:16:25 PM PDT 24 169445494 ps
T370 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3223237839 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:38 PM PDT 24 379357264 ps
T371 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.182068725 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:37 PM PDT 24 496505849 ps
T372 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3035159746 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:29 PM PDT 24 608647318 ps
T373 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2695338751 Aug 09 05:16:20 PM PDT 24 Aug 09 05:16:25 PM PDT 24 93780385 ps
T374 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3722539114 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:35 PM PDT 24 361248011 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2388810048 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:29 PM PDT 24 561679101 ps
T98 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3779058050 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:45 PM PDT 24 531609502 ps
T376 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2855034742 Aug 09 05:16:20 PM PDT 24 Aug 09 05:16:26 PM PDT 24 1092386905 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1938759223 Aug 09 05:16:12 PM PDT 24 Aug 09 05:16:16 PM PDT 24 336706707 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.620341726 Aug 09 05:16:34 PM PDT 24 Aug 09 05:16:39 PM PDT 24 516567655 ps
T115 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2208230555 Aug 09 05:16:22 PM PDT 24 Aug 09 05:17:30 PM PDT 24 251606314 ps
T120 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1558212243 Aug 09 05:16:30 PM PDT 24 Aug 09 05:17:41 PM PDT 24 1932899500 ps
T379 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1251563713 Aug 09 05:16:31 PM PDT 24 Aug 09 05:17:00 PM PDT 24 574745600 ps
T380 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2172873825 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:40 PM PDT 24 143539301 ps
T381 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3254254736 Aug 09 05:16:42 PM PDT 24 Aug 09 05:16:53 PM PDT 24 344557912 ps
T382 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4092068275 Aug 09 05:16:22 PM PDT 24 Aug 09 05:16:27 PM PDT 24 85692958 ps
T383 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3640446581 Aug 09 05:16:24 PM PDT 24 Aug 09 05:16:30 PM PDT 24 533818449 ps
T384 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.215857064 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:36 PM PDT 24 145197981 ps
T385 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1944678287 Aug 09 05:16:29 PM PDT 24 Aug 09 05:16:35 PM PDT 24 554955511 ps
T116 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3471597957 Aug 09 05:16:19 PM PDT 24 Aug 09 05:17:29 PM PDT 24 353700323 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.648169133 Aug 09 05:16:22 PM PDT 24 Aug 09 05:16:33 PM PDT 24 174492987 ps
T387 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.770127875 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:38 PM PDT 24 499402058 ps
T388 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1375275764 Aug 09 05:16:40 PM PDT 24 Aug 09 05:16:45 PM PDT 24 322832072 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3451003635 Aug 09 05:16:22 PM PDT 24 Aug 09 05:17:32 PM PDT 24 1104878761 ps
T390 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1807916882 Aug 09 05:16:19 PM PDT 24 Aug 09 05:16:24 PM PDT 24 520376541 ps
T108 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.62064112 Aug 09 05:16:10 PM PDT 24 Aug 09 05:16:37 PM PDT 24 569862493 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4173826210 Aug 09 05:16:10 PM PDT 24 Aug 09 05:16:15 PM PDT 24 463065246 ps
T392 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1805899735 Aug 09 05:16:31 PM PDT 24 Aug 09 05:17:40 PM PDT 24 523851632 ps
T393 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.6493418 Aug 09 05:16:15 PM PDT 24 Aug 09 05:16:22 PM PDT 24 127507176 ps
T394 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.11834661 Aug 09 05:16:29 PM PDT 24 Aug 09 05:16:33 PM PDT 24 365394490 ps
T94 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1364925170 Aug 09 05:16:19 PM PDT 24 Aug 09 05:16:23 PM PDT 24 171982236 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.119213381 Aug 09 05:16:11 PM PDT 24 Aug 09 05:16:17 PM PDT 24 277269535 ps
T95 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1717651203 Aug 09 05:16:32 PM PDT 24 Aug 09 05:17:05 PM PDT 24 3263959101 ps
T396 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2054866860 Aug 09 05:16:33 PM PDT 24 Aug 09 05:16:55 PM PDT 24 1052493098 ps
T397 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2133888770 Aug 09 05:16:24 PM PDT 24 Aug 09 05:16:30 PM PDT 24 154226233 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1051583573 Aug 09 05:16:19 PM PDT 24 Aug 09 05:16:38 PM PDT 24 393149530 ps
T398 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3672315435 Aug 09 05:16:19 PM PDT 24 Aug 09 05:16:52 PM PDT 24 980049661 ps
T399 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2046889073 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:36 PM PDT 24 588186708 ps
T400 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1030052036 Aug 09 05:16:29 PM PDT 24 Aug 09 05:16:33 PM PDT 24 171382215 ps
T401 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2551726142 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:37 PM PDT 24 127075257 ps
T402 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4020342806 Aug 09 05:16:25 PM PDT 24 Aug 09 05:16:29 PM PDT 24 334352948 ps
T403 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1386935662 Aug 09 05:16:23 PM PDT 24 Aug 09 05:16:31 PM PDT 24 466822203 ps
T404 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.22662391 Aug 09 05:16:41 PM PDT 24 Aug 09 05:16:51 PM PDT 24 299373372 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1379755798 Aug 09 05:16:22 PM PDT 24 Aug 09 05:16:28 PM PDT 24 193483317 ps
T406 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1652906620 Aug 09 05:16:11 PM PDT 24 Aug 09 05:16:48 PM PDT 24 376875901 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1505490587 Aug 09 05:16:12 PM PDT 24 Aug 09 05:16:17 PM PDT 24 739913301 ps
T408 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3164465544 Aug 09 05:16:48 PM PDT 24 Aug 09 05:16:53 PM PDT 24 97923367 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2329898472 Aug 09 05:16:21 PM PDT 24 Aug 09 05:16:27 PM PDT 24 134053181 ps
T410 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2506943737 Aug 09 05:16:20 PM PDT 24 Aug 09 05:16:24 PM PDT 24 85641803 ps
T411 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1136207982 Aug 09 05:16:19 PM PDT 24 Aug 09 05:16:24 PM PDT 24 85728785 ps
T412 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4074645499 Aug 09 05:16:20 PM PDT 24 Aug 09 05:16:27 PM PDT 24 506677377 ps
T413 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3668039107 Aug 09 05:16:18 PM PDT 24 Aug 09 05:16:24 PM PDT 24 256139984 ps
T414 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.472644538 Aug 09 05:16:29 PM PDT 24 Aug 09 05:16:34 PM PDT 24 132769431 ps
T415 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.390169806 Aug 09 05:16:21 PM PDT 24 Aug 09 05:16:25 PM PDT 24 1193891462 ps
T416 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3576106639 Aug 09 05:16:41 PM PDT 24 Aug 09 05:16:47 PM PDT 24 366473601 ps
T417 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1530456530 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:37 PM PDT 24 292980730 ps
T418 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2927394270 Aug 09 05:16:44 PM PDT 24 Aug 09 05:16:50 PM PDT 24 131683611 ps
T419 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4134322548 Aug 09 05:16:29 PM PDT 24 Aug 09 05:16:35 PM PDT 24 297700167 ps
T96 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3118757604 Aug 09 05:16:21 PM PDT 24 Aug 09 05:16:26 PM PDT 24 255447411 ps
T420 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4233008320 Aug 09 05:16:33 PM PDT 24 Aug 09 05:16:38 PM PDT 24 132104138 ps
T421 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4082335104 Aug 09 05:16:19 PM PDT 24 Aug 09 05:16:25 PM PDT 24 94076251 ps
T422 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3543612955 Aug 09 05:16:40 PM PDT 24 Aug 09 05:16:59 PM PDT 24 3603721043 ps
T423 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2543719572 Aug 09 05:16:12 PM PDT 24 Aug 09 05:16:16 PM PDT 24 85825711 ps
T424 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.578620155 Aug 09 05:16:31 PM PDT 24 Aug 09 05:16:58 PM PDT 24 7634604601 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.595577033 Aug 09 05:16:09 PM PDT 24 Aug 09 05:16:16 PM PDT 24 90451847 ps
T110 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1028946284 Aug 09 05:16:32 PM PDT 24 Aug 09 05:17:11 PM PDT 24 243060577 ps
T426 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1427244211 Aug 09 05:16:30 PM PDT 24 Aug 09 05:17:08 PM PDT 24 738593512 ps
T97 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3921497718 Aug 09 05:16:22 PM PDT 24 Aug 09 05:16:27 PM PDT 24 132538630 ps
T427 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3586825762 Aug 09 05:16:30 PM PDT 24 Aug 09 05:16:39 PM PDT 24 264470866 ps
T428 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.384614403 Aug 09 05:16:20 PM PDT 24 Aug 09 05:16:26 PM PDT 24 132587525 ps

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1778272389
Short name T9
Test name
Test status
Simulation time 3639474679 ps
CPU time 129.04 seconds
Started Aug 09 07:26:10 PM PDT 24
Finished Aug 09 07:28:19 PM PDT 24
Peak memory 234408 kb
Host smart-ca88d080-dace-4c53-886c-c375888da909
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778272389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1778272389
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2190630247
Short name T13
Test name
Test status
Simulation time 33828957894 ps
CPU time 724.34 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:39:07 PM PDT 24
Peak memory 228468 kb
Host smart-6e485021-0dc5-4621-8708-16dd1bd7de3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190630247 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2190630247
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3073644306
Short name T42
Test name
Test status
Simulation time 2214084381 ps
CPU time 151.31 seconds
Started Aug 09 07:26:45 PM PDT 24
Finished Aug 09 07:29:16 PM PDT 24
Peak memory 233448 kb
Host smart-d98313c3-4efb-491b-8530-31f7b4b885c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073644306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3073644306
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.30983425
Short name T2
Test name
Test status
Simulation time 997442684 ps
CPU time 70.26 seconds
Started Aug 09 07:26:12 PM PDT 24
Finished Aug 09 07:27:22 PM PDT 24
Peak memory 234288 kb
Host smart-a3eae03f-41e2-4283-8e7c-c9cdb0beb2dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30983425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_co
rrupt_sig_fatal_chk.30983425
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.667901225
Short name T111
Test name
Test status
Simulation time 494118868 ps
CPU time 69.37 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:17:41 PM PDT 24
Peak memory 219464 kb
Host smart-630917cb-0e3c-4835-85ae-285ad5a2bf5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667901225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.667901225
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3346391494
Short name T84
Test name
Test status
Simulation time 299210479 ps
CPU time 13.39 seconds
Started Aug 09 07:26:29 PM PDT 24
Finished Aug 09 07:26:43 PM PDT 24
Peak memory 212156 kb
Host smart-b119a1a0-8b70-42fe-8735-fd2e9d39b3fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346391494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3346391494
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.144207709
Short name T25
Test name
Test status
Simulation time 292694862 ps
CPU time 101.71 seconds
Started Aug 09 07:25:26 PM PDT 24
Finished Aug 09 07:27:08 PM PDT 24
Peak memory 237160 kb
Host smart-7e62e6d3-e661-4992-b5b5-389522dd1f48
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144207709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.144207709
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.301091832
Short name T74
Test name
Test status
Simulation time 483151168 ps
CPU time 5.04 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:36 PM PDT 24
Peak memory 218528 kb
Host smart-5ad92524-a0fa-441a-9b33-32d53cc56d80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301091832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.301091832
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1558212243
Short name T120
Test name
Test status
Simulation time 1932899500 ps
CPU time 70.72 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:17:41 PM PDT 24
Peak memory 214080 kb
Host smart-4b2457cb-2a5f-43e6-b900-07e63cd1ef8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558212243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1558212243
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2424834460
Short name T28
Test name
Test status
Simulation time 126835072 ps
CPU time 5.26 seconds
Started Aug 09 07:26:03 PM PDT 24
Finished Aug 09 07:26:09 PM PDT 24
Peak memory 212068 kb
Host smart-732c06a8-76e9-4e87-ba53-c7d552c9a256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424834460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2424834460
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2202755100
Short name T88
Test name
Test status
Simulation time 1879024697 ps
CPU time 27.77 seconds
Started Aug 09 05:16:12 PM PDT 24
Finished Aug 09 05:16:40 PM PDT 24
Peak memory 211252 kb
Host smart-af78de2c-c59d-4fdd-95dc-c3d3509f348f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202755100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2202755100
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3267996398
Short name T53
Test name
Test status
Simulation time 543974688 ps
CPU time 11.36 seconds
Started Aug 09 07:26:01 PM PDT 24
Finished Aug 09 07:26:13 PM PDT 24
Peak memory 212852 kb
Host smart-8a85a46e-7821-4dba-9d61-12061bda6f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267996398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3267996398
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.91250368
Short name T165
Test name
Test status
Simulation time 173522373 ps
CPU time 9.55 seconds
Started Aug 09 07:26:13 PM PDT 24
Finished Aug 09 07:26:22 PM PDT 24
Peak memory 213084 kb
Host smart-19b45792-ae76-4f05-ae56-8fca4cc3c4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91250368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.91250368
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3170771047
Short name T112
Test name
Test status
Simulation time 2527944540 ps
CPU time 69.85 seconds
Started Aug 09 05:16:41 PM PDT 24
Finished Aug 09 05:17:51 PM PDT 24
Peak memory 213960 kb
Host smart-4750527e-f7d7-4ee9-9e5f-b9a91e0222d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170771047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3170771047
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3068628660
Short name T3
Test name
Test status
Simulation time 2537144823 ps
CPU time 87.13 seconds
Started Aug 09 07:25:19 PM PDT 24
Finished Aug 09 07:26:46 PM PDT 24
Peak memory 213476 kb
Host smart-4160e098-bd42-4d87-a7e5-fa070908da48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068628660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.3068628660
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2441280568
Short name T70
Test name
Test status
Simulation time 135160050 ps
CPU time 6.51 seconds
Started Aug 09 07:26:14 PM PDT 24
Finished Aug 09 07:26:21 PM PDT 24
Peak memory 212128 kb
Host smart-de7c47df-0f9a-4d98-97c9-7f0cf9917d78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2441280568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2441280568
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.62064112
Short name T108
Test name
Test status
Simulation time 569862493 ps
CPU time 27.54 seconds
Started Aug 09 05:16:10 PM PDT 24
Finished Aug 09 05:16:37 PM PDT 24
Peak memory 211264 kb
Host smart-ce51416f-cc31-4584-b880-83083acdb7d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62064112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pass
thru_mem_tl_intg_err.62064112
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4114999272
Short name T59
Test name
Test status
Simulation time 316648814 ps
CPU time 37.31 seconds
Started Aug 09 05:16:34 PM PDT 24
Finished Aug 09 05:17:11 PM PDT 24
Peak memory 211836 kb
Host smart-1c54b893-e711-4514-9c06-9b7a1d42c870
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114999272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4114999272
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.1884413085
Short name T124
Test name
Test status
Simulation time 984461270 ps
CPU time 16.21 seconds
Started Aug 09 07:25:26 PM PDT 24
Finished Aug 09 07:25:43 PM PDT 24
Peak memory 213136 kb
Host smart-aee6def1-f989-4d1d-be58-c3b946b4c8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884413085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.1884413085
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3293341110
Short name T16
Test name
Test status
Simulation time 248819475106 ps
CPU time 715.93 seconds
Started Aug 09 07:26:44 PM PDT 24
Finished Aug 09 07:38:40 PM PDT 24
Peak memory 229376 kb
Host smart-23175a62-18c2-4008-b77a-7d66e17de4d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293341110 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3293341110
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1505490587
Short name T407
Test name
Test status
Simulation time 739913301 ps
CPU time 4.96 seconds
Started Aug 09 05:16:12 PM PDT 24
Finished Aug 09 05:16:17 PM PDT 24
Peak memory 218000 kb
Host smart-ea1c43c2-e36f-4f74-a860-9815952b29a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505490587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1505490587
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2769121319
Short name T352
Test name
Test status
Simulation time 727656361 ps
CPU time 5.24 seconds
Started Aug 09 05:16:12 PM PDT 24
Finished Aug 09 05:16:17 PM PDT 24
Peak memory 211164 kb
Host smart-583a1b3d-03ee-4a96-a6f1-91cb841abf69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769121319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2769121319
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2606147684
Short name T361
Test name
Test status
Simulation time 2537678490 ps
CPU time 8.15 seconds
Started Aug 09 05:16:12 PM PDT 24
Finished Aug 09 05:16:20 PM PDT 24
Peak memory 211336 kb
Host smart-b7a11737-ce4d-4cbf-a90f-d7425a40e5e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606147684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.2606147684
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.119213381
Short name T395
Test name
Test status
Simulation time 277269535 ps
CPU time 5.74 seconds
Started Aug 09 05:16:11 PM PDT 24
Finished Aug 09 05:16:17 PM PDT 24
Peak memory 214896 kb
Host smart-e21a5560-9717-4eb4-af32-46db729feca9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119213381 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.119213381
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.382142792
Short name T91
Test name
Test status
Simulation time 775049434 ps
CPU time 5.19 seconds
Started Aug 09 05:16:13 PM PDT 24
Finished Aug 09 05:16:18 PM PDT 24
Peak memory 211176 kb
Host smart-78cca898-0194-4cad-955d-d907f10a9c36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382142792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.382142792
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1938759223
Short name T377
Test name
Test status
Simulation time 336706707 ps
CPU time 4.06 seconds
Started Aug 09 05:16:12 PM PDT 24
Finished Aug 09 05:16:16 PM PDT 24
Peak memory 211064 kb
Host smart-80515f2b-c169-43b6-ad8f-6e48029cd872
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938759223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1938759223
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.4074661700
Short name T337
Test name
Test status
Simulation time 379740129 ps
CPU time 4.27 seconds
Started Aug 09 05:16:12 PM PDT 24
Finished Aug 09 05:16:16 PM PDT 24
Peak memory 211044 kb
Host smart-e7cb8612-3cba-469d-820e-8b16788488a9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074661700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.4074661700
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1803011200
Short name T78
Test name
Test status
Simulation time 336410804 ps
CPU time 4.31 seconds
Started Aug 09 05:16:12 PM PDT 24
Finished Aug 09 05:16:17 PM PDT 24
Peak memory 211212 kb
Host smart-e4168e99-1879-420b-a869-1fe0dd26ffe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803011200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1803011200
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.6493418
Short name T393
Test name
Test status
Simulation time 127507176 ps
CPU time 6.73 seconds
Started Aug 09 05:16:15 PM PDT 24
Finished Aug 09 05:16:22 PM PDT 24
Peak memory 219504 kb
Host smart-14dd411b-6892-4d2f-b10d-c7af892a1053
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6493418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.6493418
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1652906620
Short name T406
Test name
Test status
Simulation time 376875901 ps
CPU time 35.99 seconds
Started Aug 09 05:16:11 PM PDT 24
Finished Aug 09 05:16:48 PM PDT 24
Peak memory 211792 kb
Host smart-e5937d91-62a3-4324-9ed4-05f38ba4d370
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652906620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1652906620
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1364925170
Short name T94
Test name
Test status
Simulation time 171982236 ps
CPU time 4.26 seconds
Started Aug 09 05:16:19 PM PDT 24
Finished Aug 09 05:16:23 PM PDT 24
Peak memory 219244 kb
Host smart-fcb37593-2f5e-4c02-b13d-d064b0e2bdd3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364925170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1364925170
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1807916882
Short name T390
Test name
Test status
Simulation time 520376541 ps
CPU time 5.47 seconds
Started Aug 09 05:16:19 PM PDT 24
Finished Aug 09 05:16:24 PM PDT 24
Peak memory 217848 kb
Host smart-5a022d0b-f25e-4607-b398-2470cf765093
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807916882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1807916882
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.595577033
Short name T425
Test name
Test status
Simulation time 90451847 ps
CPU time 7.24 seconds
Started Aug 09 05:16:09 PM PDT 24
Finished Aug 09 05:16:16 PM PDT 24
Peak memory 219308 kb
Host smart-d86cb7f4-7c3e-41c0-9f7c-96fd898d1f9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595577033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.595577033
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2855034742
Short name T376
Test name
Test status
Simulation time 1092386905 ps
CPU time 5.5 seconds
Started Aug 09 05:16:20 PM PDT 24
Finished Aug 09 05:16:26 PM PDT 24
Peak memory 214636 kb
Host smart-f5c39a50-7997-4060-a3b6-27c1ab5b3a45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855034742 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2855034742
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3726134084
Short name T77
Test name
Test status
Simulation time 85446828 ps
CPU time 4.08 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:28 PM PDT 24
Peak memory 218156 kb
Host smart-f598ae38-fc3d-44cc-a5e2-a83ede20503b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726134084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3726134084
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4173826210
Short name T391
Test name
Test status
Simulation time 463065246 ps
CPU time 4.36 seconds
Started Aug 09 05:16:10 PM PDT 24
Finished Aug 09 05:16:15 PM PDT 24
Peak memory 211060 kb
Host smart-0c5070fa-7349-40fa-b152-108ee51552fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173826210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.4173826210
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2543719572
Short name T423
Test name
Test status
Simulation time 85825711 ps
CPU time 4.32 seconds
Started Aug 09 05:16:12 PM PDT 24
Finished Aug 09 05:16:16 PM PDT 24
Peak memory 211096 kb
Host smart-5c3f35b4-333b-49bd-8d99-51a07946d4a5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543719572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2543719572
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2285142964
Short name T369
Test name
Test status
Simulation time 169445494 ps
CPU time 4.29 seconds
Started Aug 09 05:16:21 PM PDT 24
Finished Aug 09 05:16:25 PM PDT 24
Peak memory 211196 kb
Host smart-1e02b3f4-243f-4b98-94bc-8b35be5c168c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285142964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2285142964
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2705793802
Short name T355
Test name
Test status
Simulation time 378756827 ps
CPU time 8.83 seconds
Started Aug 09 05:16:12 PM PDT 24
Finished Aug 09 05:16:21 PM PDT 24
Peak memory 219620 kb
Host smart-4f66af2e-9ff3-4c75-b243-ca11e61d5dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705793802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2705793802
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1017871523
Short name T117
Test name
Test status
Simulation time 400750502 ps
CPU time 36.5 seconds
Started Aug 09 05:16:11 PM PDT 24
Finished Aug 09 05:16:48 PM PDT 24
Peak memory 211824 kb
Host smart-0f0ebb71-0d27-4b2a-a4d0-104f840b787a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017871523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1017871523
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1342837773
Short name T343
Test name
Test status
Simulation time 134257562 ps
CPU time 5.76 seconds
Started Aug 09 05:16:28 PM PDT 24
Finished Aug 09 05:16:34 PM PDT 24
Peak memory 216156 kb
Host smart-f6fa6b3e-3480-4ba7-a3a9-b69cfb229628
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342837773 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1342837773
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3722539114
Short name T374
Test name
Test status
Simulation time 361248011 ps
CPU time 4.15 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:35 PM PDT 24
Peak memory 211172 kb
Host smart-76c1b7c6-d99b-4e5e-8179-16321aeee591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722539114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3722539114
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3601870012
Short name T107
Test name
Test status
Simulation time 616669967 ps
CPU time 21.5 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:51 PM PDT 24
Peak memory 211264 kb
Host smart-1a2e500c-5bd6-400d-92f7-2d0445e7b2b1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601870012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3601870012
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2046889073
Short name T399
Test name
Test status
Simulation time 588186708 ps
CPU time 5.1 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:36 PM PDT 24
Peak memory 211320 kb
Host smart-d58b46a0-0888-4077-9fc8-88fedfbbc2a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046889073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2046889073
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3223237839
Short name T370
Test name
Test status
Simulation time 379357264 ps
CPU time 7.52 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:38 PM PDT 24
Peak memory 219576 kb
Host smart-92b70d52-0898-4fd9-9715-e1a4226c6b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223237839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3223237839
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.619575654
Short name T341
Test name
Test status
Simulation time 315755831 ps
CPU time 5.3 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:37 PM PDT 24
Peak memory 213412 kb
Host smart-15675be3-b12c-4dbf-b538-e5ccd292f9a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619575654 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.619575654
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2054866860
Short name T396
Test name
Test status
Simulation time 1052493098 ps
CPU time 21.5 seconds
Started Aug 09 05:16:33 PM PDT 24
Finished Aug 09 05:16:55 PM PDT 24
Peak memory 211280 kb
Host smart-edf15c6f-d0d6-4d63-b443-5c109f66fb21
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054866860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2054866860
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3465303498
Short name T365
Test name
Test status
Simulation time 89298037 ps
CPU time 4.37 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:36 PM PDT 24
Peak memory 211348 kb
Host smart-1eb6c542-eb09-44b0-986a-59ec8224dec8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465303498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3465303498
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2551726142
Short name T401
Test name
Test status
Simulation time 127075257 ps
CPU time 6.95 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:37 PM PDT 24
Peak memory 216332 kb
Host smart-a8cbaba9-57f0-42bb-9064-89b31855440d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551726142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2551726142
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1805899735
Short name T392
Test name
Test status
Simulation time 523851632 ps
CPU time 69.51 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:17:40 PM PDT 24
Peak memory 212036 kb
Host smart-4615a5b6-571f-4915-bfc3-a0be15f948ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805899735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1805899735
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3188647851
Short name T340
Test name
Test status
Simulation time 372628743 ps
CPU time 4.47 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:35 PM PDT 24
Peak memory 213988 kb
Host smart-07529ed9-7729-4442-8ade-5b48cd7ffbc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188647851 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3188647851
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1666955654
Short name T79
Test name
Test status
Simulation time 85504401 ps
CPU time 4.09 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:35 PM PDT 24
Peak memory 211080 kb
Host smart-9ec59eed-2d7f-4cd7-8a1d-a319704ba774
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666955654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1666955654
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3006990608
Short name T93
Test name
Test status
Simulation time 4098957153 ps
CPU time 32.62 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:17:04 PM PDT 24
Peak memory 211212 kb
Host smart-7fd4d25b-b6b9-40b2-ad6a-6b133465aafa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006990608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3006990608
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.620341726
Short name T378
Test name
Test status
Simulation time 516567655 ps
CPU time 4.91 seconds
Started Aug 09 05:16:34 PM PDT 24
Finished Aug 09 05:16:39 PM PDT 24
Peak memory 218532 kb
Host smart-47df0e11-32ae-4fec-873f-f7089d3a74fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620341726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.620341726
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.4134322548
Short name T419
Test name
Test status
Simulation time 297700167 ps
CPU time 6.45 seconds
Started Aug 09 05:16:29 PM PDT 24
Finished Aug 09 05:16:35 PM PDT 24
Peak memory 219588 kb
Host smart-19b025c9-4d86-41f4-8a6f-5d7e00439ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134322548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.4134322548
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3976908911
Short name T359
Test name
Test status
Simulation time 142425981 ps
CPU time 6.46 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:36 PM PDT 24
Peak memory 216336 kb
Host smart-1a1200d2-4afa-4a3f-9ca3-a166b74b48a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976908911 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3976908911
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.11834661
Short name T394
Test name
Test status
Simulation time 365394490 ps
CPU time 4.13 seconds
Started Aug 09 05:16:29 PM PDT 24
Finished Aug 09 05:16:33 PM PDT 24
Peak memory 211212 kb
Host smart-2e601bee-0e5c-4a05-823c-50404bae12da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11834661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.11834661
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.583751897
Short name T362
Test name
Test status
Simulation time 1712203725 ps
CPU time 32.24 seconds
Started Aug 09 05:16:29 PM PDT 24
Finished Aug 09 05:17:02 PM PDT 24
Peak memory 211272 kb
Host smart-dc18e74c-f3f7-4a67-bdd2-8179e57376ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583751897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_pa
ssthru_mem_tl_intg_err.583751897
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.472644538
Short name T414
Test name
Test status
Simulation time 132769431 ps
CPU time 5.08 seconds
Started Aug 09 05:16:29 PM PDT 24
Finished Aug 09 05:16:34 PM PDT 24
Peak memory 211196 kb
Host smart-8af2ccb4-2de9-461e-bd3f-757804031b17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472644538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.472644538
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.118172518
Short name T333
Test name
Test status
Simulation time 1185430071 ps
CPU time 6.28 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:36 PM PDT 24
Peak memory 219456 kb
Host smart-b0fcdf10-cd4e-4e73-8891-fe3fdd5add25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118172518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.118172518
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3442451552
Short name T363
Test name
Test status
Simulation time 2478010271 ps
CPU time 70.17 seconds
Started Aug 09 05:16:32 PM PDT 24
Finished Aug 09 05:17:43 PM PDT 24
Peak memory 219424 kb
Host smart-72880d9b-b0a7-41e0-8097-b17e9c150ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442451552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3442451552
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1530456530
Short name T417
Test name
Test status
Simulation time 292980730 ps
CPU time 5.86 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:37 PM PDT 24
Peak memory 215980 kb
Host smart-2e45ca45-2aa3-44d7-aef0-26ed28e7259a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530456530 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1530456530
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2419957201
Short name T347
Test name
Test status
Simulation time 168461025 ps
CPU time 4.11 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:35 PM PDT 24
Peak memory 218136 kb
Host smart-0f1ad918-e912-4cf9-bb59-d8ec8a9a252e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419957201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2419957201
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1717651203
Short name T95
Test name
Test status
Simulation time 3263959101 ps
CPU time 32.98 seconds
Started Aug 09 05:16:32 PM PDT 24
Finished Aug 09 05:17:05 PM PDT 24
Peak memory 211336 kb
Host smart-0a6f80bc-3448-492f-94e4-a901c8f53134
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717651203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1717651203
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.215857064
Short name T384
Test name
Test status
Simulation time 145197981 ps
CPU time 5.08 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:36 PM PDT 24
Peak memory 211340 kb
Host smart-c71d3f73-141f-498a-a6b3-bd478619a665
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215857064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_c
trl_same_csr_outstanding.215857064
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3586825762
Short name T427
Test name
Test status
Simulation time 264470866 ps
CPU time 8.62 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:39 PM PDT 24
Peak memory 215088 kb
Host smart-86c97dfd-6130-42cb-914a-788feefa2ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586825762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3586825762
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.1944678287
Short name T385
Test name
Test status
Simulation time 554955511 ps
CPU time 5.48 seconds
Started Aug 09 05:16:29 PM PDT 24
Finished Aug 09 05:16:35 PM PDT 24
Peak memory 219472 kb
Host smart-41c2777b-37fa-45f3-9825-5bac0c26d37f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944678287 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.1944678287
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4233008320
Short name T420
Test name
Test status
Simulation time 132104138 ps
CPU time 5.05 seconds
Started Aug 09 05:16:33 PM PDT 24
Finished Aug 09 05:16:38 PM PDT 24
Peak memory 211160 kb
Host smart-d4749889-897a-4040-9934-ce0f323212f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233008320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4233008320
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.578620155
Short name T424
Test name
Test status
Simulation time 7634604601 ps
CPU time 27.55 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:58 PM PDT 24
Peak memory 211824 kb
Host smart-41ee8321-298b-456f-b94d-c292e92933b1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578620155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.578620155
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.617223900
Short name T357
Test name
Test status
Simulation time 650411093 ps
CPU time 6.04 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:38 PM PDT 24
Peak memory 219376 kb
Host smart-df423dfc-ec63-490a-8068-48e4963472ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617223900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.617223900
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2172873825
Short name T380
Test name
Test status
Simulation time 143539301 ps
CPU time 9.37 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:40 PM PDT 24
Peak memory 219500 kb
Host smart-aef80d9f-2242-48d1-bed2-5c6767f3190e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172873825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2172873825
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.4140109752
Short name T57
Test name
Test status
Simulation time 485330938 ps
CPU time 69.23 seconds
Started Aug 09 05:16:32 PM PDT 24
Finished Aug 09 05:17:41 PM PDT 24
Peak memory 212932 kb
Host smart-de9fb14b-e991-4c2a-848e-1c4fd82a0258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140109752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.4140109752
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3197425180
Short name T63
Test name
Test status
Simulation time 196460661 ps
CPU time 4.85 seconds
Started Aug 09 05:16:42 PM PDT 24
Finished Aug 09 05:16:47 PM PDT 24
Peak memory 219540 kb
Host smart-7050bac6-18be-4819-b1b0-5237d6e99151
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197425180 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3197425180
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.29941265
Short name T345
Test name
Test status
Simulation time 380710258 ps
CPU time 4.11 seconds
Started Aug 09 05:16:40 PM PDT 24
Finished Aug 09 05:16:44 PM PDT 24
Peak memory 211172 kb
Host smart-af4aab4b-2751-428d-9eb0-6a9a1a2296b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29941265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.29941265
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.375999436
Short name T87
Test name
Test status
Simulation time 575903673 ps
CPU time 27.41 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:59 PM PDT 24
Peak memory 211148 kb
Host smart-34a5d971-f68a-4af7-9f6c-ec78cba433c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375999436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.375999436
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2469128599
Short name T353
Test name
Test status
Simulation time 144666282 ps
CPU time 6.98 seconds
Started Aug 09 05:16:39 PM PDT 24
Finished Aug 09 05:16:46 PM PDT 24
Peak memory 219448 kb
Host smart-d308e395-f454-4ad8-b7db-5efe9b3b610c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469128599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2469128599
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1795711901
Short name T354
Test name
Test status
Simulation time 521524530 ps
CPU time 10.75 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:41 PM PDT 24
Peak memory 219576 kb
Host smart-8157d08c-d132-4506-b2ab-97848f3b9bc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795711901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1795711901
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1932694770
Short name T118
Test name
Test status
Simulation time 201052360 ps
CPU time 37.68 seconds
Started Aug 09 05:16:42 PM PDT 24
Finished Aug 09 05:17:19 PM PDT 24
Peak memory 214068 kb
Host smart-4e3dd70c-c767-4853-a4f7-92d09200609a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932694770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1932694770
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2449289376
Short name T339
Test name
Test status
Simulation time 602741369 ps
CPU time 5.56 seconds
Started Aug 09 05:16:43 PM PDT 24
Finished Aug 09 05:16:49 PM PDT 24
Peak memory 214964 kb
Host smart-89eb31c9-aef3-4586-8802-c752125b9d7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449289376 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2449289376
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1375275764
Short name T388
Test name
Test status
Simulation time 322832072 ps
CPU time 5.07 seconds
Started Aug 09 05:16:40 PM PDT 24
Finished Aug 09 05:16:45 PM PDT 24
Peak memory 218268 kb
Host smart-c4a9e0a1-9867-4dc4-8e65-4faf3055a7e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375275764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1375275764
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.795283422
Short name T90
Test name
Test status
Simulation time 3956993377 ps
CPU time 18.81 seconds
Started Aug 09 05:16:40 PM PDT 24
Finished Aug 09 05:16:59 PM PDT 24
Peak memory 211324 kb
Host smart-0631a9f9-21e6-4196-85e9-f3538113f359
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795283422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.795283422
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3461600502
Short name T75
Test name
Test status
Simulation time 495751929 ps
CPU time 5.19 seconds
Started Aug 09 05:16:42 PM PDT 24
Finished Aug 09 05:16:48 PM PDT 24
Peak memory 211344 kb
Host smart-4d1d0c3f-291f-4b04-aba2-77db109f9988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461600502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3461600502
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3254254736
Short name T381
Test name
Test status
Simulation time 344557912 ps
CPU time 10.82 seconds
Started Aug 09 05:16:42 PM PDT 24
Finished Aug 09 05:16:53 PM PDT 24
Peak memory 216432 kb
Host smart-4b420903-5a6f-4a42-9790-842596535021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254254736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3254254736
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3164465544
Short name T408
Test name
Test status
Simulation time 97923367 ps
CPU time 4.84 seconds
Started Aug 09 05:16:48 PM PDT 24
Finished Aug 09 05:16:53 PM PDT 24
Peak memory 219440 kb
Host smart-bd265db7-775e-4dfe-9852-6c14b98a7955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164465544 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3164465544
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3571130448
Short name T100
Test name
Test status
Simulation time 126667686 ps
CPU time 5.04 seconds
Started Aug 09 05:16:48 PM PDT 24
Finished Aug 09 05:16:53 PM PDT 24
Peak memory 211108 kb
Host smart-a554fea1-e2a5-4809-954f-c7dc27ae5439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571130448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3571130448
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.4060006947
Short name T71
Test name
Test status
Simulation time 3934039699 ps
CPU time 32.57 seconds
Started Aug 09 05:16:44 PM PDT 24
Finished Aug 09 05:17:17 PM PDT 24
Peak memory 211624 kb
Host smart-e288b66c-3af3-4723-8a92-3022d1a310d7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060006947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.4060006947
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2927394270
Short name T418
Test name
Test status
Simulation time 131683611 ps
CPU time 5.23 seconds
Started Aug 09 05:16:44 PM PDT 24
Finished Aug 09 05:16:50 PM PDT 24
Peak memory 211188 kb
Host smart-b5522f02-b037-4094-aca8-996679eed90a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927394270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2927394270
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.22662391
Short name T404
Test name
Test status
Simulation time 299373372 ps
CPU time 9.96 seconds
Started Aug 09 05:16:41 PM PDT 24
Finished Aug 09 05:16:51 PM PDT 24
Peak memory 215736 kb
Host smart-b8b37e8c-fc76-48d0-9e8d-4a454dbd0db2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22662391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.22662391
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3334180945
Short name T114
Test name
Test status
Simulation time 205592384 ps
CPU time 69.19 seconds
Started Aug 09 05:16:43 PM PDT 24
Finished Aug 09 05:17:53 PM PDT 24
Peak memory 219344 kb
Host smart-e80ce0b0-e56a-45a2-9a89-959efa7ee8fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334180945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3334180945
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2616006607
Short name T335
Test name
Test status
Simulation time 103431133 ps
CPU time 5.12 seconds
Started Aug 09 05:16:44 PM PDT 24
Finished Aug 09 05:16:49 PM PDT 24
Peak memory 219552 kb
Host smart-7b9a63f3-917a-4d30-aaa0-603740fad713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616006607 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2616006607
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2037624592
Short name T76
Test name
Test status
Simulation time 336429104 ps
CPU time 4.26 seconds
Started Aug 09 05:16:40 PM PDT 24
Finished Aug 09 05:16:44 PM PDT 24
Peak memory 219304 kb
Host smart-0067e012-c55a-4fd5-87d0-6774ee08a7a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037624592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2037624592
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3543612955
Short name T422
Test name
Test status
Simulation time 3603721043 ps
CPU time 18.66 seconds
Started Aug 09 05:16:40 PM PDT 24
Finished Aug 09 05:16:59 PM PDT 24
Peak memory 211280 kb
Host smart-9c3ea139-a7cc-4835-8444-54a2a834e513
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543612955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3543612955
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1392622106
Short name T61
Test name
Test status
Simulation time 519107894 ps
CPU time 5.06 seconds
Started Aug 09 05:16:48 PM PDT 24
Finished Aug 09 05:16:53 PM PDT 24
Peak memory 218792 kb
Host smart-5e20e357-3d91-46bc-8e48-046e832cdbaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392622106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1392622106
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3576106639
Short name T416
Test name
Test status
Simulation time 366473601 ps
CPU time 6.64 seconds
Started Aug 09 05:16:41 PM PDT 24
Finished Aug 09 05:16:47 PM PDT 24
Peak memory 219620 kb
Host smart-02788e09-66d3-45e9-bdfc-cd6777ad9708
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576106639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3576106639
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.357681951
Short name T109
Test name
Test status
Simulation time 1067867009 ps
CPU time 68.86 seconds
Started Aug 09 05:16:42 PM PDT 24
Finished Aug 09 05:17:51 PM PDT 24
Peak memory 219420 kb
Host smart-24ec873b-ef2a-4490-8cfe-436b3bf8f4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357681951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_in
tg_err.357681951
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.390169806
Short name T415
Test name
Test status
Simulation time 1193891462 ps
CPU time 4.26 seconds
Started Aug 09 05:16:21 PM PDT 24
Finished Aug 09 05:16:25 PM PDT 24
Peak memory 211144 kb
Host smart-d34f976b-98ab-46a9-bd18-1ec4dad9dcb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390169806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.390169806
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3214292320
Short name T358
Test name
Test status
Simulation time 926132302 ps
CPU time 4.37 seconds
Started Aug 09 05:16:19 PM PDT 24
Finished Aug 09 05:16:24 PM PDT 24
Peak memory 219364 kb
Host smart-78852607-e775-44d0-b517-09a331760cf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214292320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3214292320
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1240967446
Short name T356
Test name
Test status
Simulation time 539251281 ps
CPU time 8.32 seconds
Started Aug 09 05:16:21 PM PDT 24
Finished Aug 09 05:16:30 PM PDT 24
Peak memory 211152 kb
Host smart-67abb009-d5c2-4ae4-a4b2-d24b68b220ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240967446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1240967446
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2388810048
Short name T375
Test name
Test status
Simulation time 561679101 ps
CPU time 6.01 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:29 PM PDT 24
Peak memory 219408 kb
Host smart-99aecbd0-75a9-4d73-8f84-09a2471b09ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388810048 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2388810048
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.547308847
Short name T105
Test name
Test status
Simulation time 178853870 ps
CPU time 4.18 seconds
Started Aug 09 05:16:19 PM PDT 24
Finished Aug 09 05:16:23 PM PDT 24
Peak memory 211252 kb
Host smart-6d571a91-12e3-4d4a-bc65-0b40e8c988e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547308847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.547308847
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.384614403
Short name T428
Test name
Test status
Simulation time 132587525 ps
CPU time 5.14 seconds
Started Aug 09 05:16:20 PM PDT 24
Finished Aug 09 05:16:26 PM PDT 24
Peak memory 211068 kb
Host smart-1b95d035-eb71-42be-8c8b-e41da730f432
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384614403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.384614403
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1792407735
Short name T364
Test name
Test status
Simulation time 126297258 ps
CPU time 5.22 seconds
Started Aug 09 05:16:21 PM PDT 24
Finished Aug 09 05:16:26 PM PDT 24
Peak memory 211172 kb
Host smart-5e7ece81-84dc-4ca4-a64b-f4a8a9b2a75b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792407735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1792407735
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1051583573
Short name T99
Test name
Test status
Simulation time 393149530 ps
CPU time 18.61 seconds
Started Aug 09 05:16:19 PM PDT 24
Finished Aug 09 05:16:38 PM PDT 24
Peak memory 211244 kb
Host smart-7706a364-0743-4bf4-aa85-ab203ba0e165
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051583573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1051583573
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3718703185
Short name T103
Test name
Test status
Simulation time 140538519 ps
CPU time 6.99 seconds
Started Aug 09 05:16:22 PM PDT 24
Finished Aug 09 05:16:29 PM PDT 24
Peak memory 219480 kb
Host smart-f350feb4-bb82-4c24-8b53-3e87a9cdd0b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718703185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3718703185
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.990619292
Short name T344
Test name
Test status
Simulation time 533935935 ps
CPU time 9.61 seconds
Started Aug 09 05:16:24 PM PDT 24
Finished Aug 09 05:16:34 PM PDT 24
Peak memory 216392 kb
Host smart-ffdd79ce-b19d-4bd3-a5e2-249052655d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990619292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.990619292
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.659852459
Short name T113
Test name
Test status
Simulation time 665352439 ps
CPU time 71.29 seconds
Started Aug 09 05:16:25 PM PDT 24
Finished Aug 09 05:17:37 PM PDT 24
Peak memory 213172 kb
Host smart-7a2ae630-86d0-442c-8cce-f285c639b415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659852459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.659852459
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4074645499
Short name T412
Test name
Test status
Simulation time 506677377 ps
CPU time 7.61 seconds
Started Aug 09 05:16:20 PM PDT 24
Finished Aug 09 05:16:27 PM PDT 24
Peak memory 211140 kb
Host smart-07f3bb85-033e-4311-901f-0b4a64354834
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074645499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4074645499
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1136207982
Short name T411
Test name
Test status
Simulation time 85728785 ps
CPU time 4.25 seconds
Started Aug 09 05:16:19 PM PDT 24
Finished Aug 09 05:16:24 PM PDT 24
Peak memory 217864 kb
Host smart-8698657e-759c-4549-a940-95a36b9b8f63
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136207982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1136207982
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3261191770
Short name T338
Test name
Test status
Simulation time 93386954 ps
CPU time 7.33 seconds
Started Aug 09 05:16:24 PM PDT 24
Finished Aug 09 05:16:32 PM PDT 24
Peak memory 219312 kb
Host smart-781fb719-7582-4dcb-ae08-a8cbdc76c974
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261191770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3261191770
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1379755798
Short name T405
Test name
Test status
Simulation time 193483317 ps
CPU time 5.12 seconds
Started Aug 09 05:16:22 PM PDT 24
Finished Aug 09 05:16:28 PM PDT 24
Peak memory 215704 kb
Host smart-a21c5d31-0632-4b33-a074-94318a22091d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379755798 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1379755798
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.416839896
Short name T104
Test name
Test status
Simulation time 127096698 ps
CPU time 5.06 seconds
Started Aug 09 05:16:24 PM PDT 24
Finished Aug 09 05:16:29 PM PDT 24
Peak memory 218068 kb
Host smart-f20572ed-3f10-4a0d-8bc9-e94e81135dc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416839896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.416839896
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2329898472
Short name T409
Test name
Test status
Simulation time 134053181 ps
CPU time 5.07 seconds
Started Aug 09 05:16:21 PM PDT 24
Finished Aug 09 05:16:27 PM PDT 24
Peak memory 211028 kb
Host smart-c0a12012-d7f3-497d-adf1-b3290b224eb2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329898472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2329898472
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1035328592
Short name T346
Test name
Test status
Simulation time 134424906 ps
CPU time 4.99 seconds
Started Aug 09 05:16:22 PM PDT 24
Finished Aug 09 05:16:27 PM PDT 24
Peak memory 211040 kb
Host smart-016dd0c6-3218-49df-b416-0244b7128b8e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035328592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1035328592
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3241370960
Short name T89
Test name
Test status
Simulation time 1091110109 ps
CPU time 21.2 seconds
Started Aug 09 05:16:24 PM PDT 24
Finished Aug 09 05:16:46 PM PDT 24
Peak memory 211344 kb
Host smart-3e4b0c16-6307-4806-b0d8-7ffb584da9ef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241370960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3241370960
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.767469324
Short name T102
Test name
Test status
Simulation time 174987722 ps
CPU time 4.35 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:28 PM PDT 24
Peak memory 211184 kb
Host smart-62f7e2ec-3440-49bf-90ac-54ad686f36da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767469324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.767469324
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.648169133
Short name T386
Test name
Test status
Simulation time 174492987 ps
CPU time 10.96 seconds
Started Aug 09 05:16:22 PM PDT 24
Finished Aug 09 05:16:33 PM PDT 24
Peak memory 219504 kb
Host smart-6063c978-cbcf-4cb4-9cac-090872b4092a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648169133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.648169133
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3451003635
Short name T389
Test name
Test status
Simulation time 1104878761 ps
CPU time 69.94 seconds
Started Aug 09 05:16:22 PM PDT 24
Finished Aug 09 05:17:32 PM PDT 24
Peak memory 219316 kb
Host smart-24c2a49c-043d-46da-bb8c-c873af7a67c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451003635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3451003635
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3921497718
Short name T97
Test name
Test status
Simulation time 132538630 ps
CPU time 5.03 seconds
Started Aug 09 05:16:22 PM PDT 24
Finished Aug 09 05:16:27 PM PDT 24
Peak memory 218268 kb
Host smart-541086cd-e966-4157-8afa-825beadf6b76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921497718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3921497718
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3118757604
Short name T96
Test name
Test status
Simulation time 255447411 ps
CPU time 5.31 seconds
Started Aug 09 05:16:21 PM PDT 24
Finished Aug 09 05:16:26 PM PDT 24
Peak memory 218172 kb
Host smart-fec24fc7-3fcf-4623-94d0-09f669c9f98d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118757604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3118757604
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4082335104
Short name T421
Test name
Test status
Simulation time 94076251 ps
CPU time 5.74 seconds
Started Aug 09 05:16:19 PM PDT 24
Finished Aug 09 05:16:25 PM PDT 24
Peak memory 211240 kb
Host smart-54312f67-8925-4f3c-8c70-4e38e74a845e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082335104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4082335104
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3640446581
Short name T383
Test name
Test status
Simulation time 533818449 ps
CPU time 6.16 seconds
Started Aug 09 05:16:24 PM PDT 24
Finished Aug 09 05:16:30 PM PDT 24
Peak memory 215956 kb
Host smart-0a19289d-9a8f-4f3c-bff8-fb388577b7b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640446581 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3640446581
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2506943737
Short name T410
Test name
Test status
Simulation time 85641803 ps
CPU time 4.13 seconds
Started Aug 09 05:16:20 PM PDT 24
Finished Aug 09 05:16:24 PM PDT 24
Peak memory 211156 kb
Host smart-cf6ae8d2-03ae-4e60-9179-fb09a2cff973
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506943737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2506943737
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2133888770
Short name T397
Test name
Test status
Simulation time 154226233 ps
CPU time 5.07 seconds
Started Aug 09 05:16:24 PM PDT 24
Finished Aug 09 05:16:30 PM PDT 24
Peak memory 211180 kb
Host smart-c694a3f5-3e87-499e-83f8-891de1a3258a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133888770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2133888770
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2227481535
Short name T368
Test name
Test status
Simulation time 87153551 ps
CPU time 4.2 seconds
Started Aug 09 05:16:21 PM PDT 24
Finished Aug 09 05:16:25 PM PDT 24
Peak memory 211084 kb
Host smart-657eda14-538e-43e7-8e49-3761880d4453
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227481535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2227481535
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3921196531
Short name T101
Test name
Test status
Simulation time 1915729674 ps
CPU time 27.09 seconds
Started Aug 09 05:16:20 PM PDT 24
Finished Aug 09 05:16:47 PM PDT 24
Peak memory 219408 kb
Host smart-fd4d8fbe-7658-4ce1-941c-9e64ad45f8b6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921196531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3921196531
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2745103950
Short name T62
Test name
Test status
Simulation time 168704253 ps
CPU time 4.11 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:27 PM PDT 24
Peak memory 211204 kb
Host smart-2dd34249-90a3-4ab0-a7a0-92bb8612c82f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745103950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2745103950
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3754127210
Short name T366
Test name
Test status
Simulation time 90216502 ps
CPU time 7.76 seconds
Started Aug 09 05:16:24 PM PDT 24
Finished Aug 09 05:16:32 PM PDT 24
Peak memory 219620 kb
Host smart-3d4dce22-69de-4a02-b1c8-fa00cc19e896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754127210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3754127210
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2208230555
Short name T115
Test name
Test status
Simulation time 251606314 ps
CPU time 68.34 seconds
Started Aug 09 05:16:22 PM PDT 24
Finished Aug 09 05:17:30 PM PDT 24
Peak memory 212952 kb
Host smart-4c11aed5-c914-43a2-80f1-55baac9af467
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208230555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2208230555
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3035159746
Short name T372
Test name
Test status
Simulation time 608647318 ps
CPU time 5.78 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:29 PM PDT 24
Peak memory 219448 kb
Host smart-7b4b6bf5-b5af-4174-ad5a-a38d4cc161a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035159746 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3035159746
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3668039107
Short name T413
Test name
Test status
Simulation time 256139984 ps
CPU time 5.23 seconds
Started Aug 09 05:16:18 PM PDT 24
Finished Aug 09 05:16:24 PM PDT 24
Peak memory 211248 kb
Host smart-31c6de3c-33a7-4cee-870d-48aa86b0614a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668039107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3668039107
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2723432968
Short name T73
Test name
Test status
Simulation time 733333805 ps
CPU time 18.33 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:41 PM PDT 24
Peak memory 211200 kb
Host smart-f5d429a2-a4f8-408c-a365-bc5b7d59dbb9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723432968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2723432968
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1083435132
Short name T72
Test name
Test status
Simulation time 87043154 ps
CPU time 4.29 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:27 PM PDT 24
Peak memory 211256 kb
Host smart-ec748a2d-976f-497f-ac24-cbd9f193fba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083435132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1083435132
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1931188459
Short name T334
Test name
Test status
Simulation time 90443076 ps
CPU time 8.37 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:31 PM PDT 24
Peak memory 219488 kb
Host smart-21e79dd3-d549-4dd3-9a6d-dd9b1fa23905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931188459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1931188459
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3471597957
Short name T116
Test name
Test status
Simulation time 353700323 ps
CPU time 69.77 seconds
Started Aug 09 05:16:19 PM PDT 24
Finished Aug 09 05:17:29 PM PDT 24
Peak memory 212956 kb
Host smart-e5b1b649-d0d9-443a-a52a-fc18e14fa3b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471597957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3471597957
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3788674736
Short name T350
Test name
Test status
Simulation time 152582495 ps
CPU time 7.02 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:30 PM PDT 24
Peak memory 216276 kb
Host smart-d846d593-fe72-4e69-801b-4434c235735d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788674736 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3788674736
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4020342806
Short name T402
Test name
Test status
Simulation time 334352948 ps
CPU time 4.36 seconds
Started Aug 09 05:16:25 PM PDT 24
Finished Aug 09 05:16:29 PM PDT 24
Peak memory 219408 kb
Host smart-8bf31a95-9bcf-4ffe-8322-c50eea5e2849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020342806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4020342806
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3779058050
Short name T98
Test name
Test status
Simulation time 531609502 ps
CPU time 21.91 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:45 PM PDT 24
Peak memory 211344 kb
Host smart-02da79d2-928a-453c-bcbb-5f3997ca86b1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779058050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3779058050
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.4092068275
Short name T382
Test name
Test status
Simulation time 85692958 ps
CPU time 4.33 seconds
Started Aug 09 05:16:22 PM PDT 24
Finished Aug 09 05:16:27 PM PDT 24
Peak memory 211152 kb
Host smart-ea8fe17e-19c0-44bb-b43a-e0de1a15103d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092068275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.4092068275
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1386935662
Short name T403
Test name
Test status
Simulation time 466822203 ps
CPU time 8.57 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:31 PM PDT 24
Peak memory 219464 kb
Host smart-be04342f-2c3e-4ef1-9e83-201b65ce0766
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386935662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1386935662
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3354099494
Short name T58
Test name
Test status
Simulation time 248263110 ps
CPU time 68.18 seconds
Started Aug 09 05:16:20 PM PDT 24
Finished Aug 09 05:17:28 PM PDT 24
Peak memory 219388 kb
Host smart-1a658fb5-0181-4b2f-a98e-9cc44016320c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354099494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3354099494
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2911251539
Short name T351
Test name
Test status
Simulation time 147991610 ps
CPU time 5.95 seconds
Started Aug 09 05:16:29 PM PDT 24
Finished Aug 09 05:16:35 PM PDT 24
Peak memory 219564 kb
Host smart-4ce655a2-0840-491f-9b29-7dda5cb00a11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911251539 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2911251539
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2471806195
Short name T336
Test name
Test status
Simulation time 697320290 ps
CPU time 4.12 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:27 PM PDT 24
Peak memory 211192 kb
Host smart-a5d2622c-ba98-4c09-b1ce-57a5207147b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471806195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2471806195
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3672315435
Short name T398
Test name
Test status
Simulation time 980049661 ps
CPU time 32.13 seconds
Started Aug 09 05:16:19 PM PDT 24
Finished Aug 09 05:16:52 PM PDT 24
Peak memory 211332 kb
Host smart-31dd533c-cedc-4258-b299-52f18f6c36c6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672315435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3672315435
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2695338751
Short name T373
Test name
Test status
Simulation time 93780385 ps
CPU time 4.31 seconds
Started Aug 09 05:16:20 PM PDT 24
Finished Aug 09 05:16:25 PM PDT 24
Peak memory 218436 kb
Host smart-e7da688f-414b-4ed1-92a5-fce199f7af3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695338751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2695338751
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2488854981
Short name T348
Test name
Test status
Simulation time 1716852097 ps
CPU time 9.91 seconds
Started Aug 09 05:16:23 PM PDT 24
Finished Aug 09 05:16:33 PM PDT 24
Peak memory 219464 kb
Host smart-4c3357c4-af7d-4c98-a40c-306c11e33f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488854981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2488854981
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1391897159
Short name T119
Test name
Test status
Simulation time 929388574 ps
CPU time 68.79 seconds
Started Aug 09 05:16:22 PM PDT 24
Finished Aug 09 05:17:31 PM PDT 24
Peak memory 219496 kb
Host smart-b08fd6c7-bb1c-4ca3-95b4-b50282d07492
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391897159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1391897159
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.1336873481
Short name T342
Test name
Test status
Simulation time 512346905 ps
CPU time 7.62 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:38 PM PDT 24
Peak memory 219436 kb
Host smart-da7ad6eb-8d7b-4ba6-9945-69da149a1109
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336873481 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.1336873481
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1545104095
Short name T80
Test name
Test status
Simulation time 269385949 ps
CPU time 4.2 seconds
Started Aug 09 05:16:34 PM PDT 24
Finished Aug 09 05:16:38 PM PDT 24
Peak memory 218156 kb
Host smart-ba8b6586-2254-4b8d-bc30-e31c15748adc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545104095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1545104095
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2610342867
Short name T92
Test name
Test status
Simulation time 746519356 ps
CPU time 19.19 seconds
Started Aug 09 05:16:32 PM PDT 24
Finished Aug 09 05:16:52 PM PDT 24
Peak memory 211248 kb
Host smart-135aa691-8a8f-4056-8a6d-c7750b1fd6bf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610342867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2610342867
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.458422913
Short name T349
Test name
Test status
Simulation time 87002365 ps
CPU time 4.39 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:36 PM PDT 24
Peak memory 219328 kb
Host smart-43ffc66d-312f-4632-b66a-abfc8ef07d94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458422913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.458422913
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3841698181
Short name T367
Test name
Test status
Simulation time 180973655 ps
CPU time 9.97 seconds
Started Aug 09 05:16:32 PM PDT 24
Finished Aug 09 05:16:42 PM PDT 24
Peak memory 219612 kb
Host smart-3e2ae909-7755-499a-8296-169157e3ecbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841698181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3841698181
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1028946284
Short name T110
Test name
Test status
Simulation time 243060577 ps
CPU time 38.48 seconds
Started Aug 09 05:16:32 PM PDT 24
Finished Aug 09 05:17:11 PM PDT 24
Peak memory 211920 kb
Host smart-6b2c455d-b48f-4f55-9223-f0068d8c327a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028946284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1028946284
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.182068725
Short name T371
Test name
Test status
Simulation time 496505849 ps
CPU time 5.86 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:16:37 PM PDT 24
Peak memory 216384 kb
Host smart-d20aa6f8-71af-47f5-bcee-468047baae4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182068725 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.182068725
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1030052036
Short name T400
Test name
Test status
Simulation time 171382215 ps
CPU time 4.16 seconds
Started Aug 09 05:16:29 PM PDT 24
Finished Aug 09 05:16:33 PM PDT 24
Peak memory 211276 kb
Host smart-d030fc66-ab1f-4a7d-9480-4d470d13731e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030052036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1030052036
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1251563713
Short name T379
Test name
Test status
Simulation time 574745600 ps
CPU time 28.66 seconds
Started Aug 09 05:16:31 PM PDT 24
Finished Aug 09 05:17:00 PM PDT 24
Peak memory 211264 kb
Host smart-a2f644a0-d8e9-4406-bb51-32a646f4d134
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251563713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1251563713
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1582350615
Short name T360
Test name
Test status
Simulation time 85846115 ps
CPU time 4.36 seconds
Started Aug 09 05:16:34 PM PDT 24
Finished Aug 09 05:16:38 PM PDT 24
Peak memory 211188 kb
Host smart-0f5547cf-48c9-406a-a715-63d56e317cf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582350615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1582350615
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.770127875
Short name T387
Test name
Test status
Simulation time 499402058 ps
CPU time 8.78 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:16:38 PM PDT 24
Peak memory 216520 kb
Host smart-23cc5cbf-7dbe-4c9f-b5e6-bda187483b69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770127875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.770127875
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1427244211
Short name T426
Test name
Test status
Simulation time 738593512 ps
CPU time 37.02 seconds
Started Aug 09 05:16:30 PM PDT 24
Finished Aug 09 05:17:08 PM PDT 24
Peak memory 211832 kb
Host smart-0073d417-9d25-4a57-86d2-fb4f4e797e51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427244211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1427244211
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3330513019
Short name T263
Test name
Test status
Simulation time 445427185 ps
CPU time 5.26 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:25:24 PM PDT 24
Peak memory 212080 kb
Host smart-9c04bd76-d6f9-442e-a917-721522550688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330513019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3330513019
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1226105230
Short name T324
Test name
Test status
Simulation time 251982386 ps
CPU time 11.34 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:25:29 PM PDT 24
Peak memory 212996 kb
Host smart-c0a292c8-f816-46f3-80c8-a0dec1544bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226105230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1226105230
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.540361357
Short name T149
Test name
Test status
Simulation time 541198112 ps
CPU time 6.6 seconds
Started Aug 09 07:25:23 PM PDT 24
Finished Aug 09 07:25:29 PM PDT 24
Peak memory 212140 kb
Host smart-a524913d-0470-4026-a0d4-f4db738939e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=540361357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.540361357
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3237568933
Short name T30
Test name
Test status
Simulation time 207371139 ps
CPU time 52.98 seconds
Started Aug 09 07:25:20 PM PDT 24
Finished Aug 09 07:26:13 PM PDT 24
Peak memory 237440 kb
Host smart-fcd28050-b77a-4760-9867-2e9773c2b593
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237568933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3237568933
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1189316011
Short name T261
Test name
Test status
Simulation time 142607827 ps
CPU time 6.48 seconds
Started Aug 09 07:25:22 PM PDT 24
Finished Aug 09 07:25:28 PM PDT 24
Peak memory 212128 kb
Host smart-016b698a-0c8a-4e98-a1de-022d2490c838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189316011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1189316011
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2927590982
Short name T38
Test name
Test status
Simulation time 1637019126 ps
CPU time 17.54 seconds
Started Aug 09 07:25:22 PM PDT 24
Finished Aug 09 07:25:39 PM PDT 24
Peak memory 216368 kb
Host smart-37380972-59dc-4ca2-ae85-c59d84c7de0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927590982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2927590982
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3232179144
Short name T234
Test name
Test status
Simulation time 333051645 ps
CPU time 4.33 seconds
Started Aug 09 07:25:26 PM PDT 24
Finished Aug 09 07:25:30 PM PDT 24
Peak memory 212032 kb
Host smart-f3543949-8c3a-4cb8-8dee-25940bcdd61f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232179144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3232179144
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1012708547
Short name T43
Test name
Test status
Simulation time 3742282264 ps
CPU time 67.24 seconds
Started Aug 09 07:25:26 PM PDT 24
Finished Aug 09 07:26:33 PM PDT 24
Peak memory 226136 kb
Host smart-213f784e-486f-4385-a8bd-42cb9cd3521c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012708547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1012708547
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3926991640
Short name T199
Test name
Test status
Simulation time 363764290 ps
CPU time 5.37 seconds
Started Aug 09 07:25:27 PM PDT 24
Finished Aug 09 07:25:32 PM PDT 24
Peak memory 212172 kb
Host smart-e92bdebc-9dae-46f2-9ae8-bb9dc7ac105a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926991640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3926991640
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1674265902
Short name T219
Test name
Test status
Simulation time 101042248 ps
CPU time 5.62 seconds
Started Aug 09 07:25:19 PM PDT 24
Finished Aug 09 07:25:25 PM PDT 24
Peak memory 212124 kb
Host smart-44bcdfca-a9c2-40a4-a06c-900325243b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674265902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1674265902
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.100056720
Short name T85
Test name
Test status
Simulation time 278972887 ps
CPU time 13.47 seconds
Started Aug 09 07:25:18 PM PDT 24
Finished Aug 09 07:25:32 PM PDT 24
Peak memory 213816 kb
Host smart-6fcb811f-76b0-49f0-8f6d-d9862ee8e793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100056720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.100056720
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.718965138
Short name T294
Test name
Test status
Simulation time 82227008753 ps
CPU time 2214.9 seconds
Started Aug 09 07:25:27 PM PDT 24
Finished Aug 09 08:02:22 PM PDT 24
Peak memory 236632 kb
Host smart-dff9f330-8934-421a-ac59-8c8dcd17f6e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718965138 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.718965138
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3119726559
Short name T282
Test name
Test status
Simulation time 37470539019 ps
CPU time 105.72 seconds
Started Aug 09 07:26:02 PM PDT 24
Finished Aug 09 07:27:48 PM PDT 24
Peak memory 238224 kb
Host smart-6a130c53-20d1-4115-b183-5ced8f49d7de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119726559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3119726559
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2136730074
Short name T171
Test name
Test status
Simulation time 992594663 ps
CPU time 11.47 seconds
Started Aug 09 07:26:02 PM PDT 24
Finished Aug 09 07:26:14 PM PDT 24
Peak memory 212908 kb
Host smart-c57b5c7f-010c-4932-b330-fa4107904c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136730074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2136730074
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1558160962
Short name T244
Test name
Test status
Simulation time 97576434 ps
CPU time 5.88 seconds
Started Aug 09 07:25:57 PM PDT 24
Finished Aug 09 07:26:03 PM PDT 24
Peak memory 212132 kb
Host smart-edaa33ce-30ea-423b-9da2-521231750862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558160962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1558160962
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1053450450
Short name T185
Test name
Test status
Simulation time 1177494108 ps
CPU time 15.08 seconds
Started Aug 09 07:25:50 PM PDT 24
Finished Aug 09 07:26:05 PM PDT 24
Peak memory 215052 kb
Host smart-b3759f7c-6251-49d4-b3ce-c71f411329ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053450450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1053450450
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.59284219
Short name T33
Test name
Test status
Simulation time 329535136305 ps
CPU time 3461.48 seconds
Started Aug 09 07:26:02 PM PDT 24
Finished Aug 09 08:23:44 PM PDT 24
Peak memory 253040 kb
Host smart-44a77c0a-5019-45cc-81a2-d479f37f97f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59284219 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.59284219
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.2790643856
Short name T257
Test name
Test status
Simulation time 85854851 ps
CPU time 4.36 seconds
Started Aug 09 07:26:03 PM PDT 24
Finished Aug 09 07:26:07 PM PDT 24
Peak memory 212012 kb
Host smart-347d19cb-5d30-4ae4-9d27-599257359926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790643856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.2790643856
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3002392532
Short name T205
Test name
Test status
Simulation time 1721571002 ps
CPU time 96.21 seconds
Started Aug 09 07:26:02 PM PDT 24
Finished Aug 09 07:27:38 PM PDT 24
Peak memory 214364 kb
Host smart-2ef3446a-0802-43ea-954f-bd53e766ed4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002392532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3002392532
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.653757878
Short name T264
Test name
Test status
Simulation time 994232036 ps
CPU time 11.47 seconds
Started Aug 09 07:26:03 PM PDT 24
Finished Aug 09 07:26:15 PM PDT 24
Peak memory 213012 kb
Host smart-26e6fb57-b26f-4d15-aa81-74f0cebd6579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653757878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.653757878
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3518650831
Short name T268
Test name
Test status
Simulation time 2623327300 ps
CPU time 6.42 seconds
Started Aug 09 07:26:04 PM PDT 24
Finished Aug 09 07:26:10 PM PDT 24
Peak memory 212256 kb
Host smart-47149810-0584-4935-b65d-7aaf3f4a12ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518650831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3518650831
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2002560811
Short name T83
Test name
Test status
Simulation time 262420413 ps
CPU time 11.81 seconds
Started Aug 09 07:26:04 PM PDT 24
Finished Aug 09 07:26:16 PM PDT 24
Peak memory 214652 kb
Host smart-768ab029-8452-4c4d-9eed-f9503f581fa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002560811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2002560811
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1218017905
Short name T157
Test name
Test status
Simulation time 132964902 ps
CPU time 5.3 seconds
Started Aug 09 07:26:03 PM PDT 24
Finished Aug 09 07:26:09 PM PDT 24
Peak memory 212040 kb
Host smart-e8ef17da-4bd7-4996-8fde-a40f56b5e96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218017905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1218017905
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.236796658
Short name T169
Test name
Test status
Simulation time 1773448301 ps
CPU time 129.49 seconds
Started Aug 09 07:26:04 PM PDT 24
Finished Aug 09 07:28:14 PM PDT 24
Peak memory 238388 kb
Host smart-16890fc8-85d4-4448-8d69-e38a51104836
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236796658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.236796658
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1072193108
Short name T229
Test name
Test status
Simulation time 531951884 ps
CPU time 6.34 seconds
Started Aug 09 07:26:04 PM PDT 24
Finished Aug 09 07:26:10 PM PDT 24
Peak memory 212136 kb
Host smart-cce878b0-f91f-41cb-82c4-9a25778718dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072193108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1072193108
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2688023857
Short name T228
Test name
Test status
Simulation time 162160922 ps
CPU time 7.33 seconds
Started Aug 09 07:26:03 PM PDT 24
Finished Aug 09 07:26:10 PM PDT 24
Peak memory 212140 kb
Host smart-56276a4b-1e17-42c1-9713-6f7fcb60412e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688023857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2688023857
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1237112486
Short name T210
Test name
Test status
Simulation time 89272445 ps
CPU time 4.44 seconds
Started Aug 09 07:26:03 PM PDT 24
Finished Aug 09 07:26:08 PM PDT 24
Peak memory 212044 kb
Host smart-78c607a0-a508-4625-95bf-edcf1d14da98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237112486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1237112486
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2412400732
Short name T182
Test name
Test status
Simulation time 6590201480 ps
CPU time 157.12 seconds
Started Aug 09 07:26:04 PM PDT 24
Finished Aug 09 07:28:41 PM PDT 24
Peak memory 213476 kb
Host smart-a640261a-45f3-497d-8a2e-6e4e000cf556
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412400732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2412400732
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3456714688
Short name T60
Test name
Test status
Simulation time 530767687 ps
CPU time 10.97 seconds
Started Aug 09 07:26:07 PM PDT 24
Finished Aug 09 07:26:18 PM PDT 24
Peak memory 212920 kb
Host smart-7bed25fd-7cfb-4766-941c-86bf48c96bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456714688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3456714688
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2466082751
Short name T143
Test name
Test status
Simulation time 190166564 ps
CPU time 5.2 seconds
Started Aug 09 07:26:04 PM PDT 24
Finished Aug 09 07:26:09 PM PDT 24
Peak memory 212160 kb
Host smart-51dd5e8d-9cb9-44f1-b3f3-077c4b570da3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2466082751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2466082751
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2707403597
Short name T313
Test name
Test status
Simulation time 315805443 ps
CPU time 12.53 seconds
Started Aug 09 07:26:02 PM PDT 24
Finished Aug 09 07:26:14 PM PDT 24
Peak memory 215312 kb
Host smart-3c639afd-8afa-4429-94f3-eecaa84c2279
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707403597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2707403597
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3039701304
Short name T32
Test name
Test status
Simulation time 86430748 ps
CPU time 4.18 seconds
Started Aug 09 07:26:03 PM PDT 24
Finished Aug 09 07:26:07 PM PDT 24
Peak memory 212080 kb
Host smart-fda03150-c890-4513-9488-0019467d75cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039701304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3039701304
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1270424609
Short name T279
Test name
Test status
Simulation time 29010209162 ps
CPU time 140.17 seconds
Started Aug 09 07:26:03 PM PDT 24
Finished Aug 09 07:28:23 PM PDT 24
Peak memory 240500 kb
Host smart-64a84891-98e6-4e47-a9a5-edc5bd9a3430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270424609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1270424609
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.4248105544
Short name T203
Test name
Test status
Simulation time 1040178338 ps
CPU time 10.99 seconds
Started Aug 09 07:26:07 PM PDT 24
Finished Aug 09 07:26:18 PM PDT 24
Peak memory 212952 kb
Host smart-8fd2f229-3525-4f14-b364-ac6107859ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248105544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.4248105544
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2362464375
Short name T186
Test name
Test status
Simulation time 251963323 ps
CPU time 6.19 seconds
Started Aug 09 07:26:02 PM PDT 24
Finished Aug 09 07:26:09 PM PDT 24
Peak memory 212180 kb
Host smart-5bac4e7d-8e6f-474b-a877-61a295bd598f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362464375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2362464375
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2061506021
Short name T222
Test name
Test status
Simulation time 270579117 ps
CPU time 14.94 seconds
Started Aug 09 07:26:03 PM PDT 24
Finished Aug 09 07:26:18 PM PDT 24
Peak memory 215208 kb
Host smart-49ebf3c6-106e-45d5-a04b-08998453b15a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061506021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2061506021
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.2899633536
Short name T276
Test name
Test status
Simulation time 48520796720 ps
CPU time 1763.21 seconds
Started Aug 09 07:26:04 PM PDT 24
Finished Aug 09 07:55:27 PM PDT 24
Peak memory 236652 kb
Host smart-470d384c-b311-420b-b954-2e7930dd4f81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899633536 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.2899633536
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.987701890
Short name T161
Test name
Test status
Simulation time 85517054 ps
CPU time 4.31 seconds
Started Aug 09 07:26:11 PM PDT 24
Finished Aug 09 07:26:15 PM PDT 24
Peak memory 212032 kb
Host smart-7f260be9-f11b-45c8-bf78-79ed328f172b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987701890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.987701890
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3182369508
Short name T181
Test name
Test status
Simulation time 251450962 ps
CPU time 11.24 seconds
Started Aug 09 07:26:10 PM PDT 24
Finished Aug 09 07:26:21 PM PDT 24
Peak memory 213056 kb
Host smart-0cece446-0aef-4f1e-8936-c5491a1794ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182369508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3182369508
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1272685689
Short name T326
Test name
Test status
Simulation time 463335304 ps
CPU time 6.56 seconds
Started Aug 09 07:26:10 PM PDT 24
Finished Aug 09 07:26:16 PM PDT 24
Peak memory 212164 kb
Host smart-be8707db-32db-4b65-922a-cd913a9a5f5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272685689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1272685689
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3179050052
Short name T18
Test name
Test status
Simulation time 768972347 ps
CPU time 11.7 seconds
Started Aug 09 07:26:11 PM PDT 24
Finished Aug 09 07:26:22 PM PDT 24
Peak memory 214044 kb
Host smart-f9c0fc00-5b59-47f8-892a-dcbc909af4d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179050052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3179050052
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1827227120
Short name T311
Test name
Test status
Simulation time 244995749 ps
CPU time 5.26 seconds
Started Aug 09 07:26:12 PM PDT 24
Finished Aug 09 07:26:18 PM PDT 24
Peak memory 212084 kb
Host smart-ec08b234-c0c5-47a5-be2c-545bcef3804f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827227120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1827227120
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1250142968
Short name T137
Test name
Test status
Simulation time 2680028705 ps
CPU time 103.75 seconds
Started Aug 09 07:26:12 PM PDT 24
Finished Aug 09 07:27:56 PM PDT 24
Peak memory 237624 kb
Host smart-e7158588-ca8c-4a40-8ad6-d46942e8fe6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250142968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1250142968
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3938170358
Short name T69
Test name
Test status
Simulation time 260118398 ps
CPU time 11.37 seconds
Started Aug 09 07:26:12 PM PDT 24
Finished Aug 09 07:26:23 PM PDT 24
Peak memory 212836 kb
Host smart-aed56c6c-34a1-4053-bbd9-b843d35ba74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938170358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3938170358
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.2515986288
Short name T314
Test name
Test status
Simulation time 140030494 ps
CPU time 6.18 seconds
Started Aug 09 07:26:12 PM PDT 24
Finished Aug 09 07:26:18 PM PDT 24
Peak memory 212132 kb
Host smart-96fb3f45-2504-4d8c-97c7-2c8f056afc95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515986288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.2515986288
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1350978120
Short name T208
Test name
Test status
Simulation time 556870336 ps
CPU time 9.85 seconds
Started Aug 09 07:26:10 PM PDT 24
Finished Aug 09 07:26:19 PM PDT 24
Peak memory 212292 kb
Host smart-f1c70dc4-0477-4100-bc8e-364fde538806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350978120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1350978120
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3091082105
Short name T184
Test name
Test status
Simulation time 131556332 ps
CPU time 5.32 seconds
Started Aug 09 07:26:12 PM PDT 24
Finished Aug 09 07:26:18 PM PDT 24
Peak memory 212080 kb
Host smart-2ef047aa-beb0-4634-806c-e3f8bc391977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091082105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3091082105
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2428718962
Short name T134
Test name
Test status
Simulation time 1006189218 ps
CPU time 5.39 seconds
Started Aug 09 07:26:10 PM PDT 24
Finished Aug 09 07:26:16 PM PDT 24
Peak memory 212152 kb
Host smart-337df96f-f7b8-4878-b949-ae539f17f15c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428718962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2428718962
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2242936227
Short name T298
Test name
Test status
Simulation time 1222276787 ps
CPU time 15.66 seconds
Started Aug 09 07:26:12 PM PDT 24
Finished Aug 09 07:26:28 PM PDT 24
Peak memory 213788 kb
Host smart-a64ac479-82c1-4752-bb94-b302ee4bca9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242936227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2242936227
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2987815926
Short name T160
Test name
Test status
Simulation time 130922656 ps
CPU time 5.3 seconds
Started Aug 09 07:26:15 PM PDT 24
Finished Aug 09 07:26:20 PM PDT 24
Peak memory 212044 kb
Host smart-20daa208-4b4b-4ba4-9fee-786a348719cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987815926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2987815926
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1879574796
Short name T23
Test name
Test status
Simulation time 3065192708 ps
CPU time 153.26 seconds
Started Aug 09 07:26:12 PM PDT 24
Finished Aug 09 07:28:45 PM PDT 24
Peak memory 238500 kb
Host smart-e6c0402f-6988-4c0c-ae5f-d6549dd86e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879574796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1879574796
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3120206617
Short name T272
Test name
Test status
Simulation time 609179351 ps
CPU time 11.35 seconds
Started Aug 09 07:26:13 PM PDT 24
Finished Aug 09 07:26:25 PM PDT 24
Peak memory 213116 kb
Host smart-838cad2d-c15c-4551-9ae4-86852a2bab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120206617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3120206617
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3420347918
Short name T284
Test name
Test status
Simulation time 287194549 ps
CPU time 6.57 seconds
Started Aug 09 07:26:11 PM PDT 24
Finished Aug 09 07:26:18 PM PDT 24
Peak memory 212112 kb
Host smart-60f1ee7d-ae40-428d-acff-b5ec8743a4db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3420347918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3420347918
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3718224867
Short name T218
Test name
Test status
Simulation time 677790867 ps
CPU time 20.52 seconds
Started Aug 09 07:26:11 PM PDT 24
Finished Aug 09 07:26:32 PM PDT 24
Peak memory 215936 kb
Host smart-474ad4af-6d63-4a8a-a957-fff1f76b6135
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718224867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3718224867
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.923567539
Short name T285
Test name
Test status
Simulation time 133013965 ps
CPU time 5.31 seconds
Started Aug 09 07:26:15 PM PDT 24
Finished Aug 09 07:26:20 PM PDT 24
Peak memory 212076 kb
Host smart-337f35de-a07b-47db-aa3a-de922d3a65bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923567539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.923567539
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.279257330
Short name T183
Test name
Test status
Simulation time 12688793601 ps
CPU time 159.46 seconds
Started Aug 09 07:26:14 PM PDT 24
Finished Aug 09 07:28:54 PM PDT 24
Peak memory 213428 kb
Host smart-eae24393-2f93-416e-8f4f-abe2aab37314
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279257330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.279257330
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1460802003
Short name T309
Test name
Test status
Simulation time 2768771628 ps
CPU time 11.54 seconds
Started Aug 09 07:26:14 PM PDT 24
Finished Aug 09 07:26:26 PM PDT 24
Peak memory 212884 kb
Host smart-d3e05067-c2ee-4781-ab13-5dcffbf1dbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460802003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1460802003
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.93750526
Short name T307
Test name
Test status
Simulation time 229913471 ps
CPU time 14.07 seconds
Started Aug 09 07:26:12 PM PDT 24
Finished Aug 09 07:26:26 PM PDT 24
Peak memory 213380 kb
Host smart-98173f9f-6067-40e4-adec-f2ba5da42e3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93750526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 19.rom_ctrl_stress_all.93750526
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.690914716
Short name T256
Test name
Test status
Simulation time 30536745801 ps
CPU time 3754.57 seconds
Started Aug 09 07:26:16 PM PDT 24
Finished Aug 09 08:28:51 PM PDT 24
Peak memory 235520 kb
Host smart-153ab3b9-30fb-47ca-b1d2-4bfa7dec98c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690914716 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.690914716
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2516649149
Short name T320
Test name
Test status
Simulation time 168520345 ps
CPU time 4.29 seconds
Started Aug 09 07:25:26 PM PDT 24
Finished Aug 09 07:25:30 PM PDT 24
Peak memory 212072 kb
Host smart-d4770456-bb5f-4436-8731-4afbdd507020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516649149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2516649149
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2328969626
Short name T121
Test name
Test status
Simulation time 13497984703 ps
CPU time 155.38 seconds
Started Aug 09 07:25:26 PM PDT 24
Finished Aug 09 07:28:02 PM PDT 24
Peak memory 214584 kb
Host smart-1c61659b-eadc-4409-b66c-a732d20c421b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328969626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2328969626
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.282692450
Short name T164
Test name
Test status
Simulation time 175957070 ps
CPU time 9.55 seconds
Started Aug 09 07:25:26 PM PDT 24
Finished Aug 09 07:25:36 PM PDT 24
Peak memory 213032 kb
Host smart-b21d8181-a9e5-4a99-adb5-2ae2376aa9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282692450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.282692450
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2270093632
Short name T241
Test name
Test status
Simulation time 137165684 ps
CPU time 6.42 seconds
Started Aug 09 07:25:26 PM PDT 24
Finished Aug 09 07:25:33 PM PDT 24
Peak memory 212192 kb
Host smart-ee07e909-ab27-421b-b598-770cb82ef3f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270093632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2270093632
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3123579571
Short name T24
Test name
Test status
Simulation time 1031926622 ps
CPU time 52.62 seconds
Started Aug 09 07:25:25 PM PDT 24
Finished Aug 09 07:26:18 PM PDT 24
Peak memory 237324 kb
Host smart-40f84569-62f2-408a-b001-6f7fc6cd496a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123579571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3123579571
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3201041341
Short name T159
Test name
Test status
Simulation time 451828955 ps
CPU time 5.18 seconds
Started Aug 09 07:25:26 PM PDT 24
Finished Aug 09 07:25:31 PM PDT 24
Peak memory 212112 kb
Host smart-07776d9e-a793-4adf-9831-1e2d88617efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201041341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3201041341
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3737625710
Short name T81
Test name
Test status
Simulation time 1286470108 ps
CPU time 16.29 seconds
Started Aug 09 07:25:26 PM PDT 24
Finished Aug 09 07:25:42 PM PDT 24
Peak memory 213852 kb
Host smart-cb46fb04-df91-4d58-9587-4f63aff84564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737625710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3737625710
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.341959353
Short name T50
Test name
Test status
Simulation time 487233719845 ps
CPU time 3399.32 seconds
Started Aug 09 07:25:27 PM PDT 24
Finished Aug 09 08:22:06 PM PDT 24
Peak memory 253080 kb
Host smart-b9e84382-4280-47a9-b98f-38ddd35d77da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341959353 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.341959353
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2204729951
Short name T258
Test name
Test status
Simulation time 336596039 ps
CPU time 4.36 seconds
Started Aug 09 07:26:23 PM PDT 24
Finished Aug 09 07:26:27 PM PDT 24
Peak memory 212068 kb
Host smart-2a5e26cd-3e1b-4e05-9980-f9190535dd6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204729951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2204729951
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1822490504
Short name T200
Test name
Test status
Simulation time 1860673675 ps
CPU time 100.08 seconds
Started Aug 09 07:26:14 PM PDT 24
Finished Aug 09 07:27:54 PM PDT 24
Peak memory 238360 kb
Host smart-9b01d05c-74d5-474f-90ec-1db4f925a6d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822490504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1822490504
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.368659252
Short name T45
Test name
Test status
Simulation time 340098882 ps
CPU time 9.43 seconds
Started Aug 09 07:26:15 PM PDT 24
Finished Aug 09 07:26:25 PM PDT 24
Peak memory 212852 kb
Host smart-858fa23c-4386-45f4-88dd-44b717db5745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368659252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.368659252
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1335968444
Short name T231
Test name
Test status
Simulation time 616621520 ps
CPU time 5.36 seconds
Started Aug 09 07:26:14 PM PDT 24
Finished Aug 09 07:26:20 PM PDT 24
Peak memory 212128 kb
Host smart-65668acc-20bc-4aac-9b44-2ad54ebb71e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335968444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1335968444
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2069626343
Short name T86
Test name
Test status
Simulation time 113471476 ps
CPU time 8.98 seconds
Started Aug 09 07:26:12 PM PDT 24
Finished Aug 09 07:26:21 PM PDT 24
Peak memory 212136 kb
Host smart-e2c6bd30-e46b-4b0c-bd5f-b23826d928dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069626343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2069626343
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1716522781
Short name T47
Test name
Test status
Simulation time 59945708271 ps
CPU time 941.79 seconds
Started Aug 09 07:26:22 PM PDT 24
Finished Aug 09 07:42:04 PM PDT 24
Peak memory 236676 kb
Host smart-8e1e1ec5-c353-4b11-b3d9-ea8833e6845c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716522781 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1716522781
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1691055469
Short name T332
Test name
Test status
Simulation time 496680194 ps
CPU time 5.11 seconds
Started Aug 09 07:26:19 PM PDT 24
Finished Aug 09 07:26:24 PM PDT 24
Peak memory 212012 kb
Host smart-db0d93c0-9e12-4ad5-967d-7eb070dfbdfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691055469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1691055469
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3315422615
Short name T46
Test name
Test status
Simulation time 4106306853 ps
CPU time 66.11 seconds
Started Aug 09 07:26:21 PM PDT 24
Finished Aug 09 07:27:27 PM PDT 24
Peak memory 238492 kb
Host smart-a29a7c45-4532-405d-857c-5313a4bc0361
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315422615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3315422615
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2732539851
Short name T196
Test name
Test status
Simulation time 3936402361 ps
CPU time 15.94 seconds
Started Aug 09 07:26:19 PM PDT 24
Finished Aug 09 07:26:35 PM PDT 24
Peak memory 213020 kb
Host smart-8bd8e6b3-ddf0-4380-a184-0ac2eb571e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732539851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2732539851
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3944574343
Short name T269
Test name
Test status
Simulation time 2492251684 ps
CPU time 8.51 seconds
Started Aug 09 07:26:19 PM PDT 24
Finished Aug 09 07:26:28 PM PDT 24
Peak memory 212284 kb
Host smart-6bd5767a-3c2c-4224-a5f4-bd7cc0decd66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944574343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3944574343
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.642698784
Short name T68
Test name
Test status
Simulation time 285943991 ps
CPU time 17.84 seconds
Started Aug 09 07:26:19 PM PDT 24
Finished Aug 09 07:26:37 PM PDT 24
Peak memory 216248 kb
Host smart-c72fdb20-6bac-4733-b398-2d5d7ae1645d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642698784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.rom_ctrl_stress_all.642698784
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.4176305782
Short name T51
Test name
Test status
Simulation time 784040079599 ps
CPU time 2402.37 seconds
Started Aug 09 07:26:21 PM PDT 24
Finished Aug 09 08:06:24 PM PDT 24
Peak memory 244856 kb
Host smart-a31bd9ff-414c-449d-95e6-78eee8e1c920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176305782 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.4176305782
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.207392486
Short name T224
Test name
Test status
Simulation time 950154423 ps
CPU time 5 seconds
Started Aug 09 07:26:19 PM PDT 24
Finished Aug 09 07:26:24 PM PDT 24
Peak memory 212064 kb
Host smart-3495eac3-35f4-49a3-86ba-a795a548b35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207392486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.207392486
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1501302225
Short name T204
Test name
Test status
Simulation time 12839547656 ps
CPU time 110.18 seconds
Started Aug 09 07:26:19 PM PDT 24
Finished Aug 09 07:28:09 PM PDT 24
Peak memory 234380 kb
Host smart-32257cd3-21a2-4485-a6cb-d1c55f70954e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501302225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1501302225
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3448041111
Short name T226
Test name
Test status
Simulation time 176613697 ps
CPU time 9.63 seconds
Started Aug 09 07:26:21 PM PDT 24
Finished Aug 09 07:26:31 PM PDT 24
Peak memory 212888 kb
Host smart-9829d499-c67b-4f7a-b9be-c00eba7d3354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448041111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3448041111
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.801378575
Short name T239
Test name
Test status
Simulation time 876494788 ps
CPU time 6.57 seconds
Started Aug 09 07:26:18 PM PDT 24
Finished Aug 09 07:26:25 PM PDT 24
Peak memory 212132 kb
Host smart-106d5d50-6ccc-408c-8382-96f2415adf46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801378575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.801378575
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1214253596
Short name T290
Test name
Test status
Simulation time 302147395 ps
CPU time 16.72 seconds
Started Aug 09 07:26:19 PM PDT 24
Finished Aug 09 07:26:36 PM PDT 24
Peak memory 214272 kb
Host smart-1b91e048-25d6-4b49-a860-b1f788b39375
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214253596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1214253596
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1640844300
Short name T248
Test name
Test status
Simulation time 134805772 ps
CPU time 5.19 seconds
Started Aug 09 07:26:31 PM PDT 24
Finished Aug 09 07:26:36 PM PDT 24
Peak memory 212044 kb
Host smart-b66bd8a1-e7ff-4929-b35f-7ed95dc11ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640844300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1640844300
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.841627985
Short name T144
Test name
Test status
Simulation time 4893446105 ps
CPU time 148.01 seconds
Started Aug 09 07:26:20 PM PDT 24
Finished Aug 09 07:28:48 PM PDT 24
Peak memory 229172 kb
Host smart-b8bc7aeb-95ad-4efb-9691-c340383782b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841627985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.841627985
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.772734131
Short name T316
Test name
Test status
Simulation time 665886937 ps
CPU time 9.74 seconds
Started Aug 09 07:26:19 PM PDT 24
Finished Aug 09 07:26:29 PM PDT 24
Peak memory 213140 kb
Host smart-afacb604-88a6-4b83-9a75-c3f9ab80b91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772734131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.772734131
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3951010894
Short name T270
Test name
Test status
Simulation time 524750019 ps
CPU time 6.2 seconds
Started Aug 09 07:26:18 PM PDT 24
Finished Aug 09 07:26:25 PM PDT 24
Peak memory 212168 kb
Host smart-6756d3ce-6f16-4208-8300-cbf03dcffcfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951010894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3951010894
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3404244426
Short name T238
Test name
Test status
Simulation time 163029424 ps
CPU time 8.7 seconds
Started Aug 09 07:26:18 PM PDT 24
Finished Aug 09 07:26:27 PM PDT 24
Peak memory 212984 kb
Host smart-720ec90c-c76d-438b-bd86-b6f960bb239a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404244426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3404244426
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.4275924553
Short name T49
Test name
Test status
Simulation time 109659003513 ps
CPU time 666.5 seconds
Started Aug 09 07:26:22 PM PDT 24
Finished Aug 09 07:37:29 PM PDT 24
Peak memory 236672 kb
Host smart-a1ef2ad2-124f-4645-ac8d-d98379de1829
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275924553 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.4275924553
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3053400846
Short name T283
Test name
Test status
Simulation time 479755436 ps
CPU time 5.17 seconds
Started Aug 09 07:26:28 PM PDT 24
Finished Aug 09 07:26:34 PM PDT 24
Peak memory 212012 kb
Host smart-3aa6bb0e-72db-4e78-b801-0f0a2f5cc030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053400846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3053400846
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2691011598
Short name T323
Test name
Test status
Simulation time 4132766522 ps
CPU time 76.41 seconds
Started Aug 09 07:26:27 PM PDT 24
Finished Aug 09 07:27:44 PM PDT 24
Peak memory 233384 kb
Host smart-8c506f51-5bf7-4246-b50a-c033718f639e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691011598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2691011598
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3336851244
Short name T131
Test name
Test status
Simulation time 264115430 ps
CPU time 11.21 seconds
Started Aug 09 07:26:29 PM PDT 24
Finished Aug 09 07:26:40 PM PDT 24
Peak memory 213348 kb
Host smart-e23dd6e6-ccaf-45b4-87de-295787de8294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336851244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3336851244
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.712523657
Short name T286
Test name
Test status
Simulation time 561564542 ps
CPU time 6.55 seconds
Started Aug 09 07:26:30 PM PDT 24
Finished Aug 09 07:26:37 PM PDT 24
Peak memory 212148 kb
Host smart-9ec336e5-66b2-4cbd-bfe0-1ac9190830b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712523657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.712523657
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2542270283
Short name T289
Test name
Test status
Simulation time 3839080641 ps
CPU time 19.03 seconds
Started Aug 09 07:26:27 PM PDT 24
Finished Aug 09 07:26:46 PM PDT 24
Peak memory 215512 kb
Host smart-30915acc-c3f7-44c3-a907-7c8f329bd5ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542270283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2542270283
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2236460191
Short name T67
Test name
Test status
Simulation time 85957259 ps
CPU time 4.19 seconds
Started Aug 09 07:26:28 PM PDT 24
Finished Aug 09 07:26:32 PM PDT 24
Peak memory 212064 kb
Host smart-d199ecb3-1cc1-46d5-b8c5-eadeab3c4d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236460191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2236460191
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2788663329
Short name T11
Test name
Test status
Simulation time 14299146996 ps
CPU time 176.19 seconds
Started Aug 09 07:26:30 PM PDT 24
Finished Aug 09 07:29:26 PM PDT 24
Peak memory 237608 kb
Host smart-5da72739-dc45-430f-aa8e-374464077cd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788663329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2788663329
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2566443114
Short name T262
Test name
Test status
Simulation time 1002893779 ps
CPU time 11.17 seconds
Started Aug 09 07:26:27 PM PDT 24
Finished Aug 09 07:26:38 PM PDT 24
Peak memory 213000 kb
Host smart-66b0547f-021b-4a2e-a2d6-4625a591e1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566443114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2566443114
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2727164051
Short name T129
Test name
Test status
Simulation time 1342328834 ps
CPU time 6.68 seconds
Started Aug 09 07:26:29 PM PDT 24
Finished Aug 09 07:26:35 PM PDT 24
Peak memory 212140 kb
Host smart-078ed653-8798-4cfa-af04-341fde0806db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727164051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2727164051
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.895990928
Short name T303
Test name
Test status
Simulation time 631208264 ps
CPU time 16.2 seconds
Started Aug 09 07:26:28 PM PDT 24
Finished Aug 09 07:26:45 PM PDT 24
Peak memory 215640 kb
Host smart-276a8539-ba76-4e7e-a8d3-f0459c111b2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895990928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.895990928
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2087314636
Short name T172
Test name
Test status
Simulation time 1382349402 ps
CPU time 5.11 seconds
Started Aug 09 07:26:26 PM PDT 24
Finished Aug 09 07:26:31 PM PDT 24
Peak memory 212080 kb
Host smart-7c95ddb9-4b35-4daf-84ef-83c7971cb24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087314636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2087314636
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3515094288
Short name T253
Test name
Test status
Simulation time 4526338274 ps
CPU time 78.42 seconds
Started Aug 09 07:26:28 PM PDT 24
Finished Aug 09 07:27:47 PM PDT 24
Peak memory 238460 kb
Host smart-f51e8376-ebc8-4fd9-916b-eabede7429d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515094288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3515094288
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.785024186
Short name T154
Test name
Test status
Simulation time 616521563 ps
CPU time 9.41 seconds
Started Aug 09 07:26:29 PM PDT 24
Finished Aug 09 07:26:38 PM PDT 24
Peak memory 212796 kb
Host smart-efc4a5d7-6735-430d-a7b9-40fc5c1c7a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785024186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.785024186
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1383518575
Short name T34
Test name
Test status
Simulation time 144139578 ps
CPU time 6.52 seconds
Started Aug 09 07:26:29 PM PDT 24
Finished Aug 09 07:26:36 PM PDT 24
Peak memory 212464 kb
Host smart-be3139db-b896-4e79-a6f0-affb40a21bc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383518575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1383518575
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1333385732
Short name T167
Test name
Test status
Simulation time 302658493 ps
CPU time 14.02 seconds
Started Aug 09 07:26:27 PM PDT 24
Finished Aug 09 07:26:41 PM PDT 24
Peak memory 215312 kb
Host smart-3e49c143-232f-4f8b-a717-03e4084aaf46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333385732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1333385732
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3017229940
Short name T240
Test name
Test status
Simulation time 85861574 ps
CPU time 4.37 seconds
Started Aug 09 07:26:28 PM PDT 24
Finished Aug 09 07:26:33 PM PDT 24
Peak memory 212088 kb
Host smart-5a75891f-9f17-4463-bd85-137a4c755d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017229940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3017229940
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2192917546
Short name T206
Test name
Test status
Simulation time 7223261337 ps
CPU time 200.85 seconds
Started Aug 09 07:26:28 PM PDT 24
Finished Aug 09 07:29:49 PM PDT 24
Peak memory 234824 kb
Host smart-69673c13-005e-4e24-a68e-aaa7e44ce96d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192917546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2192917546
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2993914280
Short name T35
Test name
Test status
Simulation time 179129575 ps
CPU time 9.59 seconds
Started Aug 09 07:26:27 PM PDT 24
Finished Aug 09 07:26:37 PM PDT 24
Peak memory 212864 kb
Host smart-db85e389-d880-48de-b2ce-238ea241cce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993914280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2993914280
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3300492235
Short name T197
Test name
Test status
Simulation time 98756687 ps
CPU time 5.69 seconds
Started Aug 09 07:26:27 PM PDT 24
Finished Aug 09 07:26:33 PM PDT 24
Peak memory 212140 kb
Host smart-3cf3934f-501b-4201-994b-11fab48dfc1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300492235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3300492235
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.552673131
Short name T266
Test name
Test status
Simulation time 347182738 ps
CPU time 4.26 seconds
Started Aug 09 07:26:38 PM PDT 24
Finished Aug 09 07:26:42 PM PDT 24
Peak memory 212040 kb
Host smart-ec669eec-0c71-4b3d-937a-5910fdbd278c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552673131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.552673131
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.658756171
Short name T179
Test name
Test status
Simulation time 3344473895 ps
CPU time 131.97 seconds
Started Aug 09 07:26:36 PM PDT 24
Finished Aug 09 07:28:48 PM PDT 24
Peak memory 229216 kb
Host smart-b33e3e95-de18-40d8-a361-316bdbf0f2d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658756171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.658756171
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3333373505
Short name T123
Test name
Test status
Simulation time 2338835861 ps
CPU time 16.59 seconds
Started Aug 09 07:26:36 PM PDT 24
Finished Aug 09 07:26:53 PM PDT 24
Peak memory 213068 kb
Host smart-b8ca5c15-6a25-443f-a7bc-637cf03fe164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333373505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3333373505
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2788961618
Short name T331
Test name
Test status
Simulation time 141870298 ps
CPU time 6.72 seconds
Started Aug 09 07:26:35 PM PDT 24
Finished Aug 09 07:26:42 PM PDT 24
Peak memory 212144 kb
Host smart-cac57e65-d132-400e-b500-fe393ae94245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788961618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2788961618
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3474218776
Short name T306
Test name
Test status
Simulation time 200646444 ps
CPU time 12.49 seconds
Started Aug 09 07:26:37 PM PDT 24
Finished Aug 09 07:26:50 PM PDT 24
Peak memory 214412 kb
Host smart-38fc5721-6a2d-465e-ab95-3c4ca771dccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474218776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3474218776
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3972237928
Short name T15
Test name
Test status
Simulation time 14279700837 ps
CPU time 524.02 seconds
Started Aug 09 07:26:36 PM PDT 24
Finished Aug 09 07:35:20 PM PDT 24
Peak memory 224692 kb
Host smart-5cba247e-2940-47bf-bb2d-57653e881f6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972237928 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3972237928
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2760780902
Short name T142
Test name
Test status
Simulation time 730140129 ps
CPU time 5.2 seconds
Started Aug 09 07:26:36 PM PDT 24
Finished Aug 09 07:26:42 PM PDT 24
Peak memory 212032 kb
Host smart-3dd47d99-6a08-4414-a537-fdb983890424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760780902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2760780902
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2138523245
Short name T21
Test name
Test status
Simulation time 2739031188 ps
CPU time 84.58 seconds
Started Aug 09 07:26:39 PM PDT 24
Finished Aug 09 07:28:04 PM PDT 24
Peak memory 238456 kb
Host smart-c38fefe1-8e3f-4242-a7ed-11540be46b0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138523245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2138523245
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.4170493834
Short name T8
Test name
Test status
Simulation time 168719972 ps
CPU time 9.24 seconds
Started Aug 09 07:26:34 PM PDT 24
Finished Aug 09 07:26:44 PM PDT 24
Peak memory 212836 kb
Host smart-94c66abe-a5c3-4d08-930b-b370b3f91427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170493834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.4170493834
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3670772745
Short name T150
Test name
Test status
Simulation time 408805832 ps
CPU time 5.6 seconds
Started Aug 09 07:26:36 PM PDT 24
Finished Aug 09 07:26:42 PM PDT 24
Peak memory 212160 kb
Host smart-88941624-424b-46ed-9d13-63413b364d78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3670772745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3670772745
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4271013063
Short name T170
Test name
Test status
Simulation time 806330103 ps
CPU time 11.77 seconds
Started Aug 09 07:26:36 PM PDT 24
Finished Aug 09 07:26:47 PM PDT 24
Peak memory 213252 kb
Host smart-f58ea12c-aaca-4fdc-9a61-9f1a61c6d3b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271013063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4271013063
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3260217277
Short name T302
Test name
Test status
Simulation time 334849902 ps
CPU time 4.18 seconds
Started Aug 09 07:25:41 PM PDT 24
Finished Aug 09 07:25:45 PM PDT 24
Peak memory 212024 kb
Host smart-4dc1f984-46c5-41b5-b158-27b00130cec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260217277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3260217277
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2162744546
Short name T305
Test name
Test status
Simulation time 1695832183 ps
CPU time 71.88 seconds
Started Aug 09 07:25:39 PM PDT 24
Finished Aug 09 07:26:51 PM PDT 24
Peak memory 213300 kb
Host smart-cbda3648-ee77-4bd3-94ea-d4885b7622c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162744546 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2162744546
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3474249014
Short name T230
Test name
Test status
Simulation time 995155890 ps
CPU time 11.34 seconds
Started Aug 09 07:25:40 PM PDT 24
Finished Aug 09 07:25:51 PM PDT 24
Peak memory 212092 kb
Host smart-ca657b13-e115-405d-af0f-0473040c567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474249014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3474249014
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3073535012
Short name T242
Test name
Test status
Simulation time 746596413 ps
CPU time 5.44 seconds
Started Aug 09 07:25:39 PM PDT 24
Finished Aug 09 07:25:45 PM PDT 24
Peak memory 212204 kb
Host smart-abe3b3bc-ff50-4e4f-9cde-d3889d05e1ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3073535012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3073535012
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.4014586999
Short name T26
Test name
Test status
Simulation time 861347853 ps
CPU time 112.49 seconds
Started Aug 09 07:25:39 PM PDT 24
Finished Aug 09 07:27:32 PM PDT 24
Peak memory 241428 kb
Host smart-be104477-e557-490a-a960-f6fa5e99a3fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014586999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.4014586999
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1521807532
Short name T265
Test name
Test status
Simulation time 1540106304 ps
CPU time 5.56 seconds
Started Aug 09 07:25:25 PM PDT 24
Finished Aug 09 07:25:31 PM PDT 24
Peak memory 212116 kb
Host smart-6ddeb8e8-1b8e-4bb0-bf6c-112deac36b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521807532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1521807532
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.2558933820
Short name T195
Test name
Test status
Simulation time 582706497 ps
CPU time 10.05 seconds
Started Aug 09 07:25:40 PM PDT 24
Finished Aug 09 07:25:50 PM PDT 24
Peak memory 213232 kb
Host smart-b91a7caa-5e56-4b33-be02-87a9709034ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558933820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.2558933820
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2336890979
Short name T10
Test name
Test status
Simulation time 262236934 ps
CPU time 5.19 seconds
Started Aug 09 07:26:39 PM PDT 24
Finished Aug 09 07:26:44 PM PDT 24
Peak memory 212028 kb
Host smart-b33f9216-5b1c-42e6-960a-9e6adf271efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336890979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2336890979
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3540080647
Short name T236
Test name
Test status
Simulation time 26561330997 ps
CPU time 152.05 seconds
Started Aug 09 07:26:37 PM PDT 24
Finished Aug 09 07:29:09 PM PDT 24
Peak memory 234684 kb
Host smart-5b9fb4b2-d52f-4124-b0d9-0eb8be34631e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540080647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3540080647
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.233960222
Short name T7
Test name
Test status
Simulation time 510455318 ps
CPU time 11.46 seconds
Started Aug 09 07:26:39 PM PDT 24
Finished Aug 09 07:26:51 PM PDT 24
Peak memory 212816 kb
Host smart-fe363bef-bc9a-461c-a0a3-a0cfa0f24b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233960222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.233960222
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2784338
Short name T193
Test name
Test status
Simulation time 516599007 ps
CPU time 6.27 seconds
Started Aug 09 07:26:36 PM PDT 24
Finished Aug 09 07:26:43 PM PDT 24
Peak memory 212168 kb
Host smart-9f836732-bbdc-42c0-9a1a-ba596f469079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2784338
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2594729885
Short name T178
Test name
Test status
Simulation time 556723278 ps
CPU time 16.78 seconds
Started Aug 09 07:26:37 PM PDT 24
Finished Aug 09 07:26:54 PM PDT 24
Peak memory 214916 kb
Host smart-1e52a01b-1361-4823-8a5d-6f0bbdc5fad7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594729885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2594729885
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3741334335
Short name T288
Test name
Test status
Simulation time 6003263264 ps
CPU time 261.9 seconds
Started Aug 09 07:26:43 PM PDT 24
Finished Aug 09 07:31:05 PM PDT 24
Peak memory 224248 kb
Host smart-95aedf36-4e02-4201-b34d-9f99038b2a8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741334335 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3741334335
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2996936356
Short name T271
Test name
Test status
Simulation time 517359589 ps
CPU time 5.27 seconds
Started Aug 09 07:26:38 PM PDT 24
Finished Aug 09 07:26:43 PM PDT 24
Peak memory 212044 kb
Host smart-2a543b9b-2536-4dcc-8855-62b604209755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996936356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2996936356
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3652147610
Short name T251
Test name
Test status
Simulation time 2772322871 ps
CPU time 61.09 seconds
Started Aug 09 07:26:44 PM PDT 24
Finished Aug 09 07:27:45 PM PDT 24
Peak memory 234384 kb
Host smart-895ce83d-1953-48f0-b238-11ff819d6691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652147610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3652147610
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3694703521
Short name T187
Test name
Test status
Simulation time 671067762 ps
CPU time 9.49 seconds
Started Aug 09 07:26:44 PM PDT 24
Finished Aug 09 07:26:53 PM PDT 24
Peak memory 212888 kb
Host smart-3e8d1241-afd5-4b1a-8de6-6f4e83369ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694703521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3694703521
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2078428179
Short name T190
Test name
Test status
Simulation time 390852092 ps
CPU time 5.8 seconds
Started Aug 09 07:26:38 PM PDT 24
Finished Aug 09 07:26:44 PM PDT 24
Peak memory 212172 kb
Host smart-795f2f0c-c3b1-4ee7-b96c-d6897d981937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2078428179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2078428179
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2627585736
Short name T329
Test name
Test status
Simulation time 286229603 ps
CPU time 16.67 seconds
Started Aug 09 07:26:38 PM PDT 24
Finished Aug 09 07:26:55 PM PDT 24
Peak memory 217060 kb
Host smart-0af90fa5-3a6d-4d9f-aa9e-2255b27a309a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627585736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2627585736
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2063710210
Short name T52
Test name
Test status
Simulation time 201505536794 ps
CPU time 3922.27 seconds
Started Aug 09 07:26:36 PM PDT 24
Finished Aug 09 08:31:59 PM PDT 24
Peak memory 253052 kb
Host smart-1908ed43-d296-4857-b63f-336aa61ca812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063710210 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2063710210
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.928476097
Short name T36
Test name
Test status
Simulation time 522167598 ps
CPU time 5.18 seconds
Started Aug 09 07:26:46 PM PDT 24
Finished Aug 09 07:26:51 PM PDT 24
Peak memory 212028 kb
Host smart-d86096ad-4281-4b17-979f-36c5d314c24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928476097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.928476097
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3733166272
Short name T168
Test name
Test status
Simulation time 1572230127 ps
CPU time 97.41 seconds
Started Aug 09 07:26:58 PM PDT 24
Finished Aug 09 07:28:35 PM PDT 24
Peak memory 238220 kb
Host smart-02c128c3-abc0-4001-b99f-b4814a580b02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733166272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3733166272
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1358404375
Short name T202
Test name
Test status
Simulation time 250696579 ps
CPU time 11.26 seconds
Started Aug 09 07:26:43 PM PDT 24
Finished Aug 09 07:26:55 PM PDT 24
Peak memory 212908 kb
Host smart-93ffb1d0-b0a5-4dc5-b697-f01289d57c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358404375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1358404375
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2801807390
Short name T255
Test name
Test status
Simulation time 649524806 ps
CPU time 5.71 seconds
Started Aug 09 07:26:46 PM PDT 24
Finished Aug 09 07:26:51 PM PDT 24
Peak memory 212096 kb
Host smart-2f016430-f689-4524-84f0-588c6a66a14a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2801807390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2801807390
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1912926575
Short name T176
Test name
Test status
Simulation time 204108638 ps
CPU time 13.97 seconds
Started Aug 09 07:26:46 PM PDT 24
Finished Aug 09 07:27:00 PM PDT 24
Peak memory 213068 kb
Host smart-a1727a78-c991-441d-ae24-02b9cbbd4173
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912926575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1912926575
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2807735642
Short name T246
Test name
Test status
Simulation time 133865640374 ps
CPU time 2096.35 seconds
Started Aug 09 07:26:58 PM PDT 24
Finished Aug 09 08:01:55 PM PDT 24
Peak memory 236500 kb
Host smart-fb83a876-8e5a-4c1b-9877-e2fe9dbdd284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807735642 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2807735642
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1053006024
Short name T156
Test name
Test status
Simulation time 388345260 ps
CPU time 5.07 seconds
Started Aug 09 07:26:44 PM PDT 24
Finished Aug 09 07:26:49 PM PDT 24
Peak memory 212060 kb
Host smart-dd80c714-6578-44a7-a465-efe55df39cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053006024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1053006024
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1934754541
Short name T292
Test name
Test status
Simulation time 337952736 ps
CPU time 9.53 seconds
Started Aug 09 07:26:46 PM PDT 24
Finished Aug 09 07:26:55 PM PDT 24
Peak memory 212880 kb
Host smart-b6a0933a-76f0-49e2-a324-e370fe42e6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934754541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1934754541
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1185525852
Short name T260
Test name
Test status
Simulation time 147441983 ps
CPU time 6.32 seconds
Started Aug 09 07:26:45 PM PDT 24
Finished Aug 09 07:26:51 PM PDT 24
Peak memory 212144 kb
Host smart-82d5cee4-5ef8-4a87-9bc9-07a21a4755bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185525852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1185525852
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1946469078
Short name T212
Test name
Test status
Simulation time 2129047844 ps
CPU time 6.65 seconds
Started Aug 09 07:26:44 PM PDT 24
Finished Aug 09 07:26:51 PM PDT 24
Peak memory 212128 kb
Host smart-90129262-6b52-42cb-ae80-064579c135a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946469078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1946469078
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.977003916
Short name T201
Test name
Test status
Simulation time 210142743 ps
CPU time 4.29 seconds
Started Aug 09 07:26:44 PM PDT 24
Finished Aug 09 07:26:49 PM PDT 24
Peak memory 212072 kb
Host smart-670460c6-5197-4554-b34e-d74a437f45fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977003916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.977003916
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1991970701
Short name T281
Test name
Test status
Simulation time 15375551370 ps
CPU time 165.08 seconds
Started Aug 09 07:26:45 PM PDT 24
Finished Aug 09 07:29:30 PM PDT 24
Peak memory 237600 kb
Host smart-a0dd0517-4889-4930-a6fc-d27bc0b495d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991970701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1991970701
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2783498242
Short name T64
Test name
Test status
Simulation time 1035323271 ps
CPU time 11.24 seconds
Started Aug 09 07:26:46 PM PDT 24
Finished Aug 09 07:26:57 PM PDT 24
Peak memory 212844 kb
Host smart-8ea83d9d-64e3-462d-af55-f712b2ddb563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783498242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2783498242
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1797479801
Short name T158
Test name
Test status
Simulation time 476566086 ps
CPU time 6.52 seconds
Started Aug 09 07:26:45 PM PDT 24
Finished Aug 09 07:26:52 PM PDT 24
Peak memory 212136 kb
Host smart-134c7838-c49a-465a-be7a-f2b6b444c866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797479801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1797479801
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1059242997
Short name T17
Test name
Test status
Simulation time 3999647964 ps
CPU time 12.37 seconds
Started Aug 09 07:26:46 PM PDT 24
Finished Aug 09 07:26:58 PM PDT 24
Peak memory 213548 kb
Host smart-41bec321-8c93-48cf-9b89-ecbd3a627695
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059242997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1059242997
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.751482616
Short name T304
Test name
Test status
Simulation time 49576981606 ps
CPU time 808.9 seconds
Started Aug 09 07:26:58 PM PDT 24
Finished Aug 09 07:40:27 PM PDT 24
Peak memory 234604 kb
Host smart-a3597e8a-53b4-43fc-ab10-cdf5b4bc2ba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751482616 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.751482616
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4040172282
Short name T315
Test name
Test status
Simulation time 87519688 ps
CPU time 4.36 seconds
Started Aug 09 07:26:44 PM PDT 24
Finished Aug 09 07:26:48 PM PDT 24
Peak memory 212068 kb
Host smart-11e5804f-67f2-40fc-98d5-fedbb267ed84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040172282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4040172282
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.177866761
Short name T20
Test name
Test status
Simulation time 4206678296 ps
CPU time 109.92 seconds
Started Aug 09 07:26:43 PM PDT 24
Finished Aug 09 07:28:33 PM PDT 24
Peak memory 226280 kb
Host smart-4848b993-e3be-4358-9286-10c27058139d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177866761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.177866761
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3441483369
Short name T287
Test name
Test status
Simulation time 261129242 ps
CPU time 11.52 seconds
Started Aug 09 07:26:46 PM PDT 24
Finished Aug 09 07:26:58 PM PDT 24
Peak memory 212880 kb
Host smart-0c34cb2a-2c0b-4c73-a872-5fb33851f794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441483369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3441483369
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3485615956
Short name T189
Test name
Test status
Simulation time 562770364 ps
CPU time 6.35 seconds
Started Aug 09 07:26:46 PM PDT 24
Finished Aug 09 07:26:52 PM PDT 24
Peak memory 212180 kb
Host smart-d3086f51-5fa3-4a02-8ae5-2250bd8fc08a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485615956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3485615956
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3532289167
Short name T318
Test name
Test status
Simulation time 273665609 ps
CPU time 12.95 seconds
Started Aug 09 07:26:57 PM PDT 24
Finished Aug 09 07:27:10 PM PDT 24
Peak memory 213240 kb
Host smart-65321ab3-dd9a-4a67-8071-3ff27d13e2d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532289167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3532289167
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3299182431
Short name T29
Test name
Test status
Simulation time 463282698 ps
CPU time 4.14 seconds
Started Aug 09 07:26:58 PM PDT 24
Finished Aug 09 07:27:02 PM PDT 24
Peak memory 211888 kb
Host smart-67904441-ffb0-4047-86e8-155471e6c6f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299182431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3299182431
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3470432091
Short name T322
Test name
Test status
Simulation time 3432033410 ps
CPU time 51.33 seconds
Started Aug 09 07:26:58 PM PDT 24
Finished Aug 09 07:27:49 PM PDT 24
Peak memory 213304 kb
Host smart-93aef44c-48d4-4b43-88c9-e081c73b06ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470432091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3470432091
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3143953809
Short name T6
Test name
Test status
Simulation time 256211216 ps
CPU time 11.27 seconds
Started Aug 09 07:26:46 PM PDT 24
Finished Aug 09 07:26:58 PM PDT 24
Peak memory 212772 kb
Host smart-bbdc19e0-bd42-459b-804a-9b4e829ee66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143953809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3143953809
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.574566924
Short name T128
Test name
Test status
Simulation time 195371428 ps
CPU time 5.58 seconds
Started Aug 09 07:26:57 PM PDT 24
Finished Aug 09 07:27:03 PM PDT 24
Peak memory 211988 kb
Host smart-73a23717-b4fc-4bbd-afac-5b077b7a8442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=574566924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.574566924
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3667939155
Short name T213
Test name
Test status
Simulation time 808690694 ps
CPU time 10.48 seconds
Started Aug 09 07:26:44 PM PDT 24
Finished Aug 09 07:26:55 PM PDT 24
Peak memory 214848 kb
Host smart-714f2f03-8816-4607-ac6c-38e3a3fd6584
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667939155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3667939155
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1386659489
Short name T250
Test name
Test status
Simulation time 133961216 ps
CPU time 5.24 seconds
Started Aug 09 07:26:53 PM PDT 24
Finished Aug 09 07:26:59 PM PDT 24
Peak memory 212080 kb
Host smart-19ec8343-f801-46b6-8f6f-d2334cd19d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386659489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1386659489
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4288925967
Short name T41
Test name
Test status
Simulation time 12384385522 ps
CPU time 156.99 seconds
Started Aug 09 07:26:53 PM PDT 24
Finished Aug 09 07:29:30 PM PDT 24
Peak memory 238476 kb
Host smart-19a96a76-dcf5-4a26-8158-dd43e7f54fb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288925967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4288925967
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.747060269
Short name T152
Test name
Test status
Simulation time 350973508 ps
CPU time 9.47 seconds
Started Aug 09 07:26:53 PM PDT 24
Finished Aug 09 07:27:03 PM PDT 24
Peak memory 213052 kb
Host smart-fc88742b-7b4c-4691-9a3a-3ec89c026518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747060269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.747060269
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1745614058
Short name T127
Test name
Test status
Simulation time 378682433 ps
CPU time 5.72 seconds
Started Aug 09 07:26:54 PM PDT 24
Finished Aug 09 07:27:00 PM PDT 24
Peak memory 212164 kb
Host smart-860f85ab-7fce-4cfa-8110-fe0753857c37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1745614058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1745614058
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.4243770869
Short name T1
Test name
Test status
Simulation time 320742530 ps
CPU time 15.3 seconds
Started Aug 09 07:26:58 PM PDT 24
Finished Aug 09 07:27:13 PM PDT 24
Peak memory 212832 kb
Host smart-c08ae521-f510-4eab-b75f-dbedf6a7e981
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243770869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.4243770869
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.278408017
Short name T247
Test name
Test status
Simulation time 348193944 ps
CPU time 4.27 seconds
Started Aug 09 07:26:53 PM PDT 24
Finished Aug 09 07:26:58 PM PDT 24
Peak memory 212032 kb
Host smart-baaa9e55-74b2-44dd-a21c-a9179e895b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278408017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.278408017
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1405775203
Short name T223
Test name
Test status
Simulation time 6105651501 ps
CPU time 53.05 seconds
Started Aug 09 07:26:53 PM PDT 24
Finished Aug 09 07:27:46 PM PDT 24
Peak memory 237468 kb
Host smart-77e4332e-9a78-403b-bf06-6341d91c2f95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405775203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1405775203
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.769598311
Short name T245
Test name
Test status
Simulation time 1565025957 ps
CPU time 11.48 seconds
Started Aug 09 07:26:54 PM PDT 24
Finished Aug 09 07:27:05 PM PDT 24
Peak memory 213600 kb
Host smart-4035bd50-d215-4d08-950a-351dd265dac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769598311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.769598311
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2620941177
Short name T321
Test name
Test status
Simulation time 553178248 ps
CPU time 6.18 seconds
Started Aug 09 07:26:51 PM PDT 24
Finished Aug 09 07:26:58 PM PDT 24
Peak memory 212124 kb
Host smart-cef366ca-31be-4aec-9755-c60f28260930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2620941177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2620941177
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1286808699
Short name T319
Test name
Test status
Simulation time 172146651 ps
CPU time 9.42 seconds
Started Aug 09 07:26:54 PM PDT 24
Finished Aug 09 07:27:03 PM PDT 24
Peak memory 212996 kb
Host smart-37e523fd-0b53-46e4-b118-1c3319e6db19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286808699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1286808699
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1121973264
Short name T27
Test name
Test status
Simulation time 334554172 ps
CPU time 4.28 seconds
Started Aug 09 07:26:54 PM PDT 24
Finished Aug 09 07:26:59 PM PDT 24
Peak memory 212092 kb
Host smart-7953aba7-d974-44b4-9afb-8de4ffb3e72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121973264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1121973264
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1023796565
Short name T280
Test name
Test status
Simulation time 3514113063 ps
CPU time 94.86 seconds
Started Aug 09 07:26:54 PM PDT 24
Finished Aug 09 07:28:29 PM PDT 24
Peak memory 229284 kb
Host smart-0a22326b-4229-4f03-8796-c43d189347ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023796565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1023796565
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.156497124
Short name T139
Test name
Test status
Simulation time 251584606 ps
CPU time 11.32 seconds
Started Aug 09 07:26:54 PM PDT 24
Finished Aug 09 07:27:06 PM PDT 24
Peak memory 213032 kb
Host smart-2d44ab0e-e3d0-4cb9-aea7-43d3680ce2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156497124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.156497124
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2982442738
Short name T194
Test name
Test status
Simulation time 141477785 ps
CPU time 6.29 seconds
Started Aug 09 07:26:53 PM PDT 24
Finished Aug 09 07:26:59 PM PDT 24
Peak memory 212112 kb
Host smart-c398344f-3e95-41c8-9601-31b7406bf005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982442738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2982442738
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1219716671
Short name T274
Test name
Test status
Simulation time 1172334072 ps
CPU time 14.68 seconds
Started Aug 09 07:26:54 PM PDT 24
Finished Aug 09 07:27:09 PM PDT 24
Peak memory 216216 kb
Host smart-db1468b5-ad9b-4439-9509-2a47a653e5ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219716671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1219716671
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.909485926
Short name T66
Test name
Test status
Simulation time 622737717 ps
CPU time 5.19 seconds
Started Aug 09 07:25:40 PM PDT 24
Finished Aug 09 07:25:45 PM PDT 24
Peak memory 212012 kb
Host smart-993c6a75-f032-4c3b-857a-e5e3f24dc262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909485926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.909485926
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3800112955
Short name T216
Test name
Test status
Simulation time 11405081885 ps
CPU time 116.65 seconds
Started Aug 09 07:25:41 PM PDT 24
Finished Aug 09 07:27:38 PM PDT 24
Peak memory 233824 kb
Host smart-beeb33dc-08bb-4663-b2d4-3c5715f7e8d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800112955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3800112955
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1725424013
Short name T136
Test name
Test status
Simulation time 250158774 ps
CPU time 11.15 seconds
Started Aug 09 07:25:40 PM PDT 24
Finished Aug 09 07:25:51 PM PDT 24
Peak memory 212904 kb
Host smart-4b41c985-1025-467a-a223-71e27ae2e121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725424013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1725424013
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.811324756
Short name T308
Test name
Test status
Simulation time 149006494 ps
CPU time 6.63 seconds
Started Aug 09 07:25:40 PM PDT 24
Finished Aug 09 07:25:47 PM PDT 24
Peak memory 212184 kb
Host smart-605a83a5-ac91-4a1e-a50f-344bdb3f4120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=811324756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.811324756
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3560054698
Short name T31
Test name
Test status
Simulation time 204900648 ps
CPU time 54.21 seconds
Started Aug 09 07:25:40 PM PDT 24
Finished Aug 09 07:26:34 PM PDT 24
Peak memory 236512 kb
Host smart-a14b5db5-011e-401c-90b5-48c7fee4bc3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560054698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3560054698
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.4210297012
Short name T19
Test name
Test status
Simulation time 390129100 ps
CPU time 5.43 seconds
Started Aug 09 07:25:40 PM PDT 24
Finished Aug 09 07:25:45 PM PDT 24
Peak memory 212172 kb
Host smart-67dfae1e-7471-4e25-9cbe-a0b959220748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210297012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.4210297012
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1017902503
Short name T174
Test name
Test status
Simulation time 273086015 ps
CPU time 9.61 seconds
Started Aug 09 07:25:39 PM PDT 24
Finished Aug 09 07:25:49 PM PDT 24
Peak memory 212080 kb
Host smart-489bc5d2-f882-4a83-9ba3-72c27f1d859c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017902503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1017902503
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2449442009
Short name T254
Test name
Test status
Simulation time 88823669 ps
CPU time 4.29 seconds
Started Aug 09 07:27:01 PM PDT 24
Finished Aug 09 07:27:05 PM PDT 24
Peak memory 212044 kb
Host smart-ad2e6829-89b5-4252-a188-f07389d9d1c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449442009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2449442009
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3617258892
Short name T296
Test name
Test status
Simulation time 3610425379 ps
CPU time 96.6 seconds
Started Aug 09 07:26:56 PM PDT 24
Finished Aug 09 07:28:33 PM PDT 24
Peak memory 226048 kb
Host smart-4cafff32-c98b-4dab-a30d-b22adbc6903d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617258892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3617258892
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3526113439
Short name T44
Test name
Test status
Simulation time 362397779 ps
CPU time 9.68 seconds
Started Aug 09 07:26:56 PM PDT 24
Finished Aug 09 07:27:06 PM PDT 24
Peak memory 212784 kb
Host smart-4831d7fa-8159-4201-9317-6e838e9de6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526113439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3526113439
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.405553122
Short name T310
Test name
Test status
Simulation time 101112623 ps
CPU time 5.7 seconds
Started Aug 09 07:26:51 PM PDT 24
Finished Aug 09 07:26:57 PM PDT 24
Peak memory 212132 kb
Host smart-8b772438-4270-4d51-9b9e-ead93cc9796b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405553122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.405553122
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3453012313
Short name T177
Test name
Test status
Simulation time 151501023 ps
CPU time 11.07 seconds
Started Aug 09 07:26:52 PM PDT 24
Finished Aug 09 07:27:03 PM PDT 24
Peak memory 212096 kb
Host smart-8b04ff7c-c28b-45c6-87c0-44b32e00671c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453012313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3453012313
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3342810650
Short name T259
Test name
Test status
Simulation time 499791461 ps
CPU time 5.12 seconds
Started Aug 09 07:27:01 PM PDT 24
Finished Aug 09 07:27:06 PM PDT 24
Peak memory 212080 kb
Host smart-003dceee-7262-401b-8894-fdca42362669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342810650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3342810650
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1108444266
Short name T220
Test name
Test status
Simulation time 1958292177 ps
CPU time 99.05 seconds
Started Aug 09 07:27:00 PM PDT 24
Finished Aug 09 07:28:39 PM PDT 24
Peak memory 229124 kb
Host smart-de8d5b6c-3c3e-4790-82df-067993f0c4c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108444266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1108444266
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.965692811
Short name T291
Test name
Test status
Simulation time 999869416 ps
CPU time 11.32 seconds
Started Aug 09 07:27:00 PM PDT 24
Finished Aug 09 07:27:11 PM PDT 24
Peak memory 213040 kb
Host smart-3ed6a89a-36c5-42ab-bb0b-e596e3e46a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965692811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.965692811
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.58884185
Short name T12
Test name
Test status
Simulation time 269318868 ps
CPU time 6.7 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:27:09 PM PDT 24
Peak memory 212144 kb
Host smart-e8df9757-7cb3-49ce-8d43-eb3c8d8fe0e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58884185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.58884185
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.608837683
Short name T82
Test name
Test status
Simulation time 229991398 ps
CPU time 14.69 seconds
Started Aug 09 07:27:01 PM PDT 24
Finished Aug 09 07:27:16 PM PDT 24
Peak memory 215256 kb
Host smart-2e7d8ef3-c4e8-4328-9557-0218933be030
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608837683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.608837683
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3435873478
Short name T148
Test name
Test status
Simulation time 214865307 ps
CPU time 4.27 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:27:06 PM PDT 24
Peak memory 212092 kb
Host smart-9f29fa1d-73a1-4b3a-ade3-a7549c4d52c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435873478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3435873478
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3297700969
Short name T22
Test name
Test status
Simulation time 3129591210 ps
CPU time 155.27 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:29:37 PM PDT 24
Peak memory 238516 kb
Host smart-9e73ac97-0088-422b-9064-3fa055799500
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297700969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3297700969
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2228351545
Short name T301
Test name
Test status
Simulation time 257346482 ps
CPU time 11.05 seconds
Started Aug 09 07:27:03 PM PDT 24
Finished Aug 09 07:27:14 PM PDT 24
Peak memory 212904 kb
Host smart-44c3a623-b19d-4951-977a-69cccba6e969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228351545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2228351545
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.190888342
Short name T175
Test name
Test status
Simulation time 417843346 ps
CPU time 6.3 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:27:09 PM PDT 24
Peak memory 212168 kb
Host smart-d227fae8-ac22-4f66-86a8-b4c97fe82d8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=190888342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.190888342
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1625152942
Short name T293
Test name
Test status
Simulation time 309918294 ps
CPU time 8.8 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:27:11 PM PDT 24
Peak memory 213060 kb
Host smart-97513531-ec4f-4962-a1a8-e6e05684218a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625152942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1625152942
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.308748660
Short name T48
Test name
Test status
Simulation time 98058030734 ps
CPU time 1932.25 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:59:14 PM PDT 24
Peak memory 236636 kb
Host smart-a6dff643-5ead-4130-8771-f0f42878b97f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308748660 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.308748660
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.816931264
Short name T65
Test name
Test status
Simulation time 336500970 ps
CPU time 4.32 seconds
Started Aug 09 07:27:01 PM PDT 24
Finished Aug 09 07:27:05 PM PDT 24
Peak memory 212080 kb
Host smart-15e587f7-975c-4eab-95a5-f720af684223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816931264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.816931264
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.2281374209
Short name T299
Test name
Test status
Simulation time 19223323439 ps
CPU time 164.71 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:29:47 PM PDT 24
Peak memory 234816 kb
Host smart-5c3f16a4-bc2e-4bb7-8ea2-75cb3a6db778
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281374209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.2281374209
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3288240793
Short name T37
Test name
Test status
Simulation time 980912130 ps
CPU time 16.22 seconds
Started Aug 09 07:27:01 PM PDT 24
Finished Aug 09 07:27:17 PM PDT 24
Peak memory 212820 kb
Host smart-7d982d14-47ef-4bd4-b702-7bca1c41d27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288240793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3288240793
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.413541897
Short name T138
Test name
Test status
Simulation time 394244438 ps
CPU time 5.35 seconds
Started Aug 09 07:27:01 PM PDT 24
Finished Aug 09 07:27:06 PM PDT 24
Peak memory 212168 kb
Host smart-2bb22f8a-fdbc-40cd-9bdf-1170e996b3cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=413541897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.413541897
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2851837797
Short name T297
Test name
Test status
Simulation time 1341020402 ps
CPU time 14.83 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:27:17 PM PDT 24
Peak memory 215104 kb
Host smart-92c1e1a9-9383-4cb0-ad06-d0ce5d877eed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851837797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2851837797
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.7264442
Short name T249
Test name
Test status
Simulation time 1380752999 ps
CPU time 4.35 seconds
Started Aug 09 07:27:04 PM PDT 24
Finished Aug 09 07:27:08 PM PDT 24
Peak memory 212040 kb
Host smart-77b0b00d-54ec-4338-afe5-528d01cc6a4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7264442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.7264442
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.737973674
Short name T130
Test name
Test status
Simulation time 1035795697 ps
CPU time 69.2 seconds
Started Aug 09 07:27:01 PM PDT 24
Finished Aug 09 07:28:10 PM PDT 24
Peak memory 237276 kb
Host smart-55e64283-1d25-4051-b07a-48f7590d5af1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737973674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.737973674
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3865239915
Short name T209
Test name
Test status
Simulation time 251311945 ps
CPU time 11.18 seconds
Started Aug 09 07:27:04 PM PDT 24
Finished Aug 09 07:27:15 PM PDT 24
Peak memory 212924 kb
Host smart-e04b563c-fc6b-487d-8d4f-fef645eb95a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865239915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3865239915
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3582171768
Short name T252
Test name
Test status
Simulation time 377266449 ps
CPU time 5.29 seconds
Started Aug 09 07:27:00 PM PDT 24
Finished Aug 09 07:27:05 PM PDT 24
Peak memory 212156 kb
Host smart-5834d901-20e0-4c89-961c-3721816baaa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3582171768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3582171768
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3131116532
Short name T277
Test name
Test status
Simulation time 318130908 ps
CPU time 15.68 seconds
Started Aug 09 07:27:01 PM PDT 24
Finished Aug 09 07:27:17 PM PDT 24
Peak memory 214328 kb
Host smart-5fa33f6b-2617-4866-aaa8-ed0b1e2219a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131116532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3131116532
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3292434222
Short name T162
Test name
Test status
Simulation time 168248305 ps
CPU time 4.37 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:27:06 PM PDT 24
Peak memory 212068 kb
Host smart-3c197eaf-2d42-4a77-a1bd-c2e92a31c77a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292434222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3292434222
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.325551460
Short name T227
Test name
Test status
Simulation time 13233444866 ps
CPU time 248.63 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:31:11 PM PDT 24
Peak memory 234820 kb
Host smart-4752a9c5-a05c-42fb-bc55-c07f1596d734
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325551460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.325551460
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2550939241
Short name T275
Test name
Test status
Simulation time 224957246 ps
CPU time 9.82 seconds
Started Aug 09 07:27:02 PM PDT 24
Finished Aug 09 07:27:12 PM PDT 24
Peak memory 212800 kb
Host smart-7087ca28-d334-4f16-9077-be27dc6119cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550939241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2550939241
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2863289749
Short name T232
Test name
Test status
Simulation time 143159134 ps
CPU time 6.67 seconds
Started Aug 09 07:27:03 PM PDT 24
Finished Aug 09 07:27:10 PM PDT 24
Peak memory 212172 kb
Host smart-39248397-240b-481f-b1ac-8ceae5bd606f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2863289749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2863289749
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.347115948
Short name T191
Test name
Test status
Simulation time 164389421 ps
CPU time 11.58 seconds
Started Aug 09 07:27:00 PM PDT 24
Finished Aug 09 07:27:12 PM PDT 24
Peak memory 212772 kb
Host smart-45883e35-966d-4c58-84dc-ca7cc36c984f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347115948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.347115948
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.3078309628
Short name T166
Test name
Test status
Simulation time 1378558311 ps
CPU time 4.34 seconds
Started Aug 09 07:27:10 PM PDT 24
Finished Aug 09 07:27:15 PM PDT 24
Peak memory 212084 kb
Host smart-6ac3a8d9-25d0-4d93-b095-8eab7c9d0765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078309628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.3078309628
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.880629331
Short name T126
Test name
Test status
Simulation time 3358864633 ps
CPU time 81.99 seconds
Started Aug 09 07:27:08 PM PDT 24
Finished Aug 09 07:28:31 PM PDT 24
Peak memory 228992 kb
Host smart-6347a657-41e6-4764-848e-00fa080f95ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880629331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_c
orrupt_sig_fatal_chk.880629331
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3539200588
Short name T151
Test name
Test status
Simulation time 1133162810 ps
CPU time 11.27 seconds
Started Aug 09 07:27:09 PM PDT 24
Finished Aug 09 07:27:20 PM PDT 24
Peak memory 212916 kb
Host smart-f8b03c87-142f-4727-af0c-022167ca8b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539200588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3539200588
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4174378947
Short name T133
Test name
Test status
Simulation time 139913430 ps
CPU time 6.2 seconds
Started Aug 09 07:27:10 PM PDT 24
Finished Aug 09 07:27:17 PM PDT 24
Peak memory 212172 kb
Host smart-00227dc3-43b0-4289-af78-ff00d383513e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4174378947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4174378947
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3371453741
Short name T243
Test name
Test status
Simulation time 934289207 ps
CPU time 9.15 seconds
Started Aug 09 07:27:09 PM PDT 24
Finished Aug 09 07:27:19 PM PDT 24
Peak memory 212124 kb
Host smart-7330b35d-d862-4792-8b7d-8add2e0ba2e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371453741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3371453741
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1029386272
Short name T233
Test name
Test status
Simulation time 215357360 ps
CPU time 4.35 seconds
Started Aug 09 07:27:09 PM PDT 24
Finished Aug 09 07:27:14 PM PDT 24
Peak memory 212080 kb
Host smart-707e83de-18b9-413e-859e-8c4493c30772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029386272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1029386272
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.4163036276
Short name T215
Test name
Test status
Simulation time 53198333786 ps
CPU time 240.47 seconds
Started Aug 09 07:27:10 PM PDT 24
Finished Aug 09 07:31:11 PM PDT 24
Peak memory 238384 kb
Host smart-f7579b1b-6cf4-453b-81ef-cf36f62679eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163036276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.4163036276
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2728038393
Short name T125
Test name
Test status
Simulation time 257012887 ps
CPU time 11.26 seconds
Started Aug 09 07:27:11 PM PDT 24
Finished Aug 09 07:27:22 PM PDT 24
Peak memory 212816 kb
Host smart-735ac116-f3f3-4334-b12d-e52664aba552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728038393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2728038393
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2330473377
Short name T132
Test name
Test status
Simulation time 98629796 ps
CPU time 6.01 seconds
Started Aug 09 07:27:09 PM PDT 24
Finished Aug 09 07:27:15 PM PDT 24
Peak memory 212184 kb
Host smart-ec93fdfc-5e3b-4880-87e1-d46fca725c12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330473377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2330473377
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3885718192
Short name T325
Test name
Test status
Simulation time 350852527 ps
CPU time 11.19 seconds
Started Aug 09 07:27:09 PM PDT 24
Finished Aug 09 07:27:21 PM PDT 24
Peak memory 214004 kb
Host smart-1ad55813-dfd4-4a39-8919-93ce796ba7cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885718192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3885718192
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2592553271
Short name T180
Test name
Test status
Simulation time 520560045 ps
CPU time 4.99 seconds
Started Aug 09 07:27:10 PM PDT 24
Finished Aug 09 07:27:15 PM PDT 24
Peak memory 212028 kb
Host smart-b562e40e-309b-4454-a87d-a43bed60b10b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592553271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2592553271
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3526903904
Short name T317
Test name
Test status
Simulation time 21920517984 ps
CPU time 97.35 seconds
Started Aug 09 07:27:11 PM PDT 24
Finished Aug 09 07:28:48 PM PDT 24
Peak memory 213468 kb
Host smart-9edfea61-3935-4f67-a7c2-505859c5aee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526903904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3526903904
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3533318768
Short name T225
Test name
Test status
Simulation time 2072435906 ps
CPU time 10.79 seconds
Started Aug 09 07:27:09 PM PDT 24
Finished Aug 09 07:27:20 PM PDT 24
Peak memory 212804 kb
Host smart-25624157-70d4-4127-9683-88ad2dd41b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533318768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3533318768
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.861319571
Short name T327
Test name
Test status
Simulation time 143606750 ps
CPU time 6.7 seconds
Started Aug 09 07:27:11 PM PDT 24
Finished Aug 09 07:27:18 PM PDT 24
Peak memory 212192 kb
Host smart-16f71e57-ff40-4152-bc40-d037a4c46536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=861319571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.861319571
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3010380692
Short name T40
Test name
Test status
Simulation time 159113987 ps
CPU time 8.47 seconds
Started Aug 09 07:27:11 PM PDT 24
Finished Aug 09 07:27:19 PM PDT 24
Peak memory 212100 kb
Host smart-c3f9c514-c619-4280-bc9b-1773eb3de852
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010380692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3010380692
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.164599716
Short name T235
Test name
Test status
Simulation time 176085485 ps
CPU time 4.32 seconds
Started Aug 09 07:27:14 PM PDT 24
Finished Aug 09 07:27:18 PM PDT 24
Peak memory 212056 kb
Host smart-bc25d476-d7da-420f-a1fc-bd2e651028b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164599716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.164599716
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3029625264
Short name T14
Test name
Test status
Simulation time 1479892606 ps
CPU time 88.3 seconds
Started Aug 09 07:27:11 PM PDT 24
Finished Aug 09 07:28:39 PM PDT 24
Peak memory 225484 kb
Host smart-c00aa55f-12cd-466c-9c85-2548712bfdc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029625264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3029625264
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1569028499
Short name T135
Test name
Test status
Simulation time 754796240 ps
CPU time 9.76 seconds
Started Aug 09 07:27:10 PM PDT 24
Finished Aug 09 07:27:20 PM PDT 24
Peak memory 212888 kb
Host smart-8f523129-3f2e-4dce-b934-60da0a79f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569028499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1569028499
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1646496776
Short name T39
Test name
Test status
Simulation time 326897460 ps
CPU time 6.49 seconds
Started Aug 09 07:27:11 PM PDT 24
Finished Aug 09 07:27:17 PM PDT 24
Peak memory 212136 kb
Host smart-53d2c02b-a46c-4f96-8ca1-d70aa71d5cb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646496776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1646496776
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1438055049
Short name T106
Test name
Test status
Simulation time 1176248037 ps
CPU time 12.12 seconds
Started Aug 09 07:27:12 PM PDT 24
Finished Aug 09 07:27:24 PM PDT 24
Peak memory 214288 kb
Host smart-54b5eb25-c1f0-4c50-a60b-a7741232e04a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438055049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1438055049
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4215967663
Short name T278
Test name
Test status
Simulation time 86620337 ps
CPU time 4.3 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:25:55 PM PDT 24
Peak memory 212060 kb
Host smart-91ce3d16-5019-4883-b151-0d35cf4b8b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215967663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4215967663
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3759388732
Short name T237
Test name
Test status
Simulation time 7939793713 ps
CPU time 132.3 seconds
Started Aug 09 07:25:39 PM PDT 24
Finished Aug 09 07:27:52 PM PDT 24
Peak memory 235576 kb
Host smart-2b348e63-6c90-410c-bfa8-1168185a4e6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759388732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3759388732
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1025068568
Short name T192
Test name
Test status
Simulation time 754521180 ps
CPU time 9.54 seconds
Started Aug 09 07:25:39 PM PDT 24
Finished Aug 09 07:25:49 PM PDT 24
Peak memory 212840 kb
Host smart-fd7c3c61-6418-466e-a2a8-049cebb8337e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025068568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1025068568
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1531984340
Short name T153
Test name
Test status
Simulation time 103153906 ps
CPU time 5.94 seconds
Started Aug 09 07:25:42 PM PDT 24
Finished Aug 09 07:25:48 PM PDT 24
Peak memory 212184 kb
Host smart-aff01357-70e6-4588-ab0f-bfc68c02d498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1531984340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1531984340
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3553116577
Short name T188
Test name
Test status
Simulation time 545387272 ps
CPU time 6.6 seconds
Started Aug 09 07:25:39 PM PDT 24
Finished Aug 09 07:25:46 PM PDT 24
Peak memory 212172 kb
Host smart-fcc42ab7-dcdb-451e-9b0d-969fe8766c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553116577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3553116577
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.1767063745
Short name T221
Test name
Test status
Simulation time 379330064 ps
CPU time 11.63 seconds
Started Aug 09 07:25:38 PM PDT 24
Finished Aug 09 07:25:50 PM PDT 24
Peak memory 214784 kb
Host smart-0209429d-36bd-4536-9696-ea619f3e9dea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767063745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.1767063745
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.355242832
Short name T214
Test name
Test status
Simulation time 89656397 ps
CPU time 4.37 seconds
Started Aug 09 07:25:50 PM PDT 24
Finished Aug 09 07:25:55 PM PDT 24
Peak memory 212064 kb
Host smart-6bc733ed-6074-475c-8123-f64ee5199140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355242832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.355242832
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1026716203
Short name T140
Test name
Test status
Simulation time 3991503845 ps
CPU time 125.42 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:27:56 PM PDT 24
Peak memory 238608 kb
Host smart-8f4b1a09-024f-4956-80a4-834d89ccfd85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026716203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1026716203
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2814953105
Short name T5
Test name
Test status
Simulation time 1308742078 ps
CPU time 11.1 seconds
Started Aug 09 07:25:53 PM PDT 24
Finished Aug 09 07:26:04 PM PDT 24
Peak memory 212908 kb
Host smart-e733743e-901d-4574-9396-36a3d8ebbe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814953105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2814953105
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2010235581
Short name T173
Test name
Test status
Simulation time 105496720 ps
CPU time 5.78 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:25:57 PM PDT 24
Peak memory 212172 kb
Host smart-a122b751-85fd-48ef-929c-7990cf63793b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010235581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2010235581
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2901281025
Short name T145
Test name
Test status
Simulation time 520555601 ps
CPU time 6.01 seconds
Started Aug 09 07:25:52 PM PDT 24
Finished Aug 09 07:25:58 PM PDT 24
Peak memory 212224 kb
Host smart-f159a2d5-f673-48fa-bb22-08f4f592b91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901281025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2901281025
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.220337794
Short name T267
Test name
Test status
Simulation time 292020613 ps
CPU time 17.08 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:26:08 PM PDT 24
Peak memory 213824 kb
Host smart-e1c2a23d-6ae7-4bd9-ac73-cb7a3d7dfd7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220337794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.220337794
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3371623600
Short name T146
Test name
Test status
Simulation time 349608362 ps
CPU time 4.28 seconds
Started Aug 09 07:25:52 PM PDT 24
Finished Aug 09 07:25:56 PM PDT 24
Peak memory 212024 kb
Host smart-3ab468d4-aef7-455b-9179-1023e349b035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371623600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3371623600
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2545650579
Short name T122
Test name
Test status
Simulation time 8595336280 ps
CPU time 152.68 seconds
Started Aug 09 07:25:50 PM PDT 24
Finished Aug 09 07:28:23 PM PDT 24
Peak memory 234448 kb
Host smart-b6e4a788-01dc-47d3-aa19-5d7978f9e6e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545650579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2545650579
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.4222370997
Short name T141
Test name
Test status
Simulation time 169489218 ps
CPU time 9.5 seconds
Started Aug 09 07:25:53 PM PDT 24
Finished Aug 09 07:26:02 PM PDT 24
Peak memory 212940 kb
Host smart-4d9119d2-8018-4ec3-ae57-517015661c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222370997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.4222370997
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.829221626
Short name T54
Test name
Test status
Simulation time 1565506435 ps
CPU time 5.75 seconds
Started Aug 09 07:25:50 PM PDT 24
Finished Aug 09 07:25:56 PM PDT 24
Peak memory 212192 kb
Host smart-101a07fe-3956-4e5d-a656-ec1d79a9ed97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829221626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.829221626
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1690154361
Short name T56
Test name
Test status
Simulation time 202368735 ps
CPU time 5.64 seconds
Started Aug 09 07:25:57 PM PDT 24
Finished Aug 09 07:26:03 PM PDT 24
Peak memory 212196 kb
Host smart-6021a195-df0d-40eb-bb6b-b4c4e33c5044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690154361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1690154361
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2811029998
Short name T55
Test name
Test status
Simulation time 303988919 ps
CPU time 14.33 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:26:05 PM PDT 24
Peak memory 213820 kb
Host smart-243541fd-7102-4d38-8bc6-59e2f2e5e682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811029998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2811029998
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1332900662
Short name T328
Test name
Test status
Simulation time 28011858454 ps
CPU time 1252.17 seconds
Started Aug 09 07:25:50 PM PDT 24
Finished Aug 09 07:46:42 PM PDT 24
Peak memory 236868 kb
Host smart-9799d8be-f508-4465-a748-7639b3337e15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332900662 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1332900662
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1602497960
Short name T295
Test name
Test status
Simulation time 522965244 ps
CPU time 5.14 seconds
Started Aug 09 07:25:52 PM PDT 24
Finished Aug 09 07:25:57 PM PDT 24
Peak memory 212036 kb
Host smart-85799384-a6a2-4ad3-b28f-d48b947db251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602497960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1602497960
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3681218398
Short name T147
Test name
Test status
Simulation time 1347762306 ps
CPU time 75.65 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:27:07 PM PDT 24
Peak memory 237052 kb
Host smart-3d94a617-e98c-4204-a426-22bd11ae6f61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681218398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3681218398
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2652383169
Short name T163
Test name
Test status
Simulation time 169405001 ps
CPU time 9.71 seconds
Started Aug 09 07:25:52 PM PDT 24
Finished Aug 09 07:26:02 PM PDT 24
Peak memory 213092 kb
Host smart-644aabd3-a667-42b5-ae9d-226d579be23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652383169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2652383169
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1883570040
Short name T273
Test name
Test status
Simulation time 137599660 ps
CPU time 6.33 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:25:57 PM PDT 24
Peak memory 212136 kb
Host smart-d81f9a8b-6161-4520-bdf7-1ace28321904
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883570040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1883570040
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3499727356
Short name T211
Test name
Test status
Simulation time 141271089 ps
CPU time 6.38 seconds
Started Aug 09 07:25:53 PM PDT 24
Finished Aug 09 07:25:59 PM PDT 24
Peak memory 212216 kb
Host smart-97881abb-0456-4238-97e5-41d47037e1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499727356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3499727356
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3787822688
Short name T312
Test name
Test status
Simulation time 373228947 ps
CPU time 13.45 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:26:04 PM PDT 24
Peak memory 214372 kb
Host smart-833e3d16-1323-43b4-bd0b-dcbb9bba6752
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787822688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3787822688
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1483383352
Short name T217
Test name
Test status
Simulation time 397174452 ps
CPU time 4.21 seconds
Started Aug 09 07:25:52 PM PDT 24
Finished Aug 09 07:25:57 PM PDT 24
Peak memory 212032 kb
Host smart-a0eed2ba-895b-442b-a3a5-f21899e57d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483383352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1483383352
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1659693110
Short name T330
Test name
Test status
Simulation time 2047849127 ps
CPU time 53.02 seconds
Started Aug 09 07:25:52 PM PDT 24
Finished Aug 09 07:26:45 PM PDT 24
Peak memory 212348 kb
Host smart-dce8708a-5635-473e-97fc-28a8abb6d032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659693110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1659693110
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3335461411
Short name T4
Test name
Test status
Simulation time 696595842 ps
CPU time 9.29 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:26:01 PM PDT 24
Peak memory 212884 kb
Host smart-adba9140-8808-46bd-8efc-01edec6ef20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335461411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3335461411
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4101055230
Short name T198
Test name
Test status
Simulation time 97314844 ps
CPU time 5.47 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:25:57 PM PDT 24
Peak memory 212184 kb
Host smart-93eea8bb-94d9-43c7-a850-ffcc9f3ecfec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101055230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4101055230
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2293530808
Short name T155
Test name
Test status
Simulation time 196706529 ps
CPU time 5.47 seconds
Started Aug 09 07:25:51 PM PDT 24
Finished Aug 09 07:25:57 PM PDT 24
Peak memory 212144 kb
Host smart-f6b9fad9-29cb-4e97-aa12-988e9473ca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293530808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2293530808
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.885653747
Short name T207
Test name
Test status
Simulation time 285220645 ps
CPU time 12.62 seconds
Started Aug 09 07:25:52 PM PDT 24
Finished Aug 09 07:26:05 PM PDT 24
Peak memory 214464 kb
Host smart-94f5d735-9173-4110-9d20-ea290f994b0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885653747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.885653747
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3115667807
Short name T300
Test name
Test status
Simulation time 174560143314 ps
CPU time 1415.98 seconds
Started Aug 09 07:25:53 PM PDT 24
Finished Aug 09 07:49:29 PM PDT 24
Peak memory 236664 kb
Host smart-91747199-781c-4b4a-835c-c64ff77382ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115667807 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3115667807
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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