Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1739944

1

T2

3

T3

9

T6

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	456149	1			T2	42		T3	72		T6	391
values[0x0]	657332	1			T12	97875		T14	15330		T15	196775
values[0x1]	681650	1			T12	101222		T14	16075		T15	205008

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29680	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1765451

1

T2

26

T3

45

T6

229

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6131	1			T12	1018		T17	3		T14	145
valid_sources[0x01]	7595	1			T3	2		T12	1022		T17	5
valid_sources[0x02]	5856	1			T3	1		T12	1071		T17	1
valid_sources[0x03]	5750	1			T8	8		T12	1029		T17	1
valid_sources[0x04]	6628	1			T6	14		T12	1007		T17	6
valid_sources[0x05]	7394	1			T3	1		T12	1034		T17	1
valid_sources[0x06]	6627	1			T12	945		T14	209		T15	1381
valid_sources[0x07]	6843	1			T12	1059		T14	244		T15	2020
valid_sources[0x08]	9688	1			T2	1		T12	1010		T14	328
valid_sources[0x09]	7677	1			T3	1		T12	965		T14	200
valid_sources[0x0a]	9006	1			T12	1057		T14	119		T15	4075
valid_sources[0x0b]	6063	1			T3	2		T12	1024		T14	193
valid_sources[0x0c]	6958	1			T12	1004		T17	1		T14	99
valid_sources[0x0d]	5357	1			T2	1		T12	1044		T17	1
valid_sources[0x0e]	5577	1			T12	1112		T17	1		T14	229
valid_sources[0x0f]	6012	1			T12	1018		T14	93		T15	1352
valid_sources[0x10]	6628	1			T3	1		T12	1023		T14	180
valid_sources[0x11]	7111	1			T12	989		T14	183		T15	2340
valid_sources[0x12]	7598	1			T12	1040		T13	4		T17	3
valid_sources[0x13]	6992	1			T6	45		T12	1052		T17	1
valid_sources[0x14]	7432	1			T3	1		T12	972		T17	5
valid_sources[0x15]	7525	1			T12	961		T17	2		T14	177
valid_sources[0x16]	6380	1			T2	1		T12	1025		T17	2
valid_sources[0x17]	7058	1			T6	15		T12	1017		T17	4
valid_sources[0x18]	8579	1			T3	3		T12	1136		T14	232
valid_sources[0x19]	7204	1			T12	1074		T14	103		T15	1973
valid_sources[0x1a]	5885	1			T3	2		T12	1032		T14	142
valid_sources[0x1b]	7640	1			T12	993		T14	136		T15	3169
valid_sources[0x1c]	6149	1			T12	984		T17	1		T14	185
valid_sources[0x1d]	7763	1			T12	999		T17	2		T14	173
valid_sources[0x1e]	5497	1			T3	1		T12	1028		T17	3
valid_sources[0x1f]	6927	1			T3	3		T12	1046		T17	5
valid_sources[0x20]	7087	1			T12	1065		T17	2		T14	119
valid_sources[0x21]	6918	1			T12	1099		T14	160		T15	2283
valid_sources[0x22]	6731	1			T12	1053		T17	3		T14	121
valid_sources[0x23]	6233	1			T12	1066		T14	201		T15	1270
valid_sources[0x24]	5571	1			T12	1047		T17	4		T14	213
valid_sources[0x25]	6734	1			T12	1059		T17	3		T14	225
valid_sources[0x26]	6451	1			T3	1		T12	1016		T14	136
valid_sources[0x27]	7471	1			T12	973		T17	1		T14	155
valid_sources[0x28]	6975	1			T6	5		T12	1006		T17	3
valid_sources[0x29]	6367	1			T12	1064		T17	1		T14	155
valid_sources[0x2a]	5404	1			T12	1027		T17	4		T14	144
valid_sources[0x2b]	7283	1			T12	1039		T17	3		T14	150
valid_sources[0x2c]	7362	1			T6	9		T12	1018		T14	228
valid_sources[0x2d]	6328	1			T12	1006		T17	3		T14	130
valid_sources[0x2e]	7715	1			T12	934		T17	2		T14	134
valid_sources[0x2f]	8333	1			T6	7		T12	1015		T14	189
valid_sources[0x30]	6231	1			T12	979		T17	1		T14	84
valid_sources[0x31]	6252	1			T12	1044		T14	136		T15	1328
valid_sources[0x32]	9280	1			T12	1008		T17	1		T14	153
valid_sources[0x33]	6014	1			T12	1046		T14	279		T15	1202
valid_sources[0x34]	8772	1			T12	951		T17	2		T14	102
valid_sources[0x35]	8534	1			T3	4		T12	1083		T17	1
valid_sources[0x36]	7054	1			T3	1		T12	1052		T14	203
valid_sources[0x37]	6656	1			T12	1032		T13	11		T17	1
valid_sources[0x38]	7612	1			T3	1		T6	10		T12	1048
valid_sources[0x39]	6969	1			T11	1		T12	1058		T14	193
valid_sources[0x3a]	9715	1			T12	1000		T17	3		T14	90
valid_sources[0x3b]	6558	1			T3	1		T12	1043		T14	220
valid_sources[0x3c]	8324	1			T8	9		T12	1036		T17	7
valid_sources[0x3d]	8114	1			T3	1		T12	1072		T13	7
valid_sources[0x3e]	6401	1			T12	1028		T14	235		T15	1509
valid_sources[0x3f]	7737	1			T12	994		T17	3		T14	202
valid_sources[0x40]	8135	1			T3	1		T8	4		T12	1066
valid_sources[0x41]	5301	1			T3	3		T6	8		T11	2
valid_sources[0x42]	6767	1			T6	6		T12	924		T17	3
valid_sources[0x43]	6608	1			T2	1		T12	1064		T17	2
valid_sources[0x44]	6617	1			T8	8		T12	999		T17	3
valid_sources[0x45]	5680	1			T6	11		T12	1070		T17	1
valid_sources[0x46]	7888	1			T2	1		T12	1050		T14	158
valid_sources[0x47]	6151	1			T12	1003		T14	121		T15	1029
valid_sources[0x48]	6968	1			T2	1		T12	1084		T13	1
valid_sources[0x49]	7496	1			T12	1058		T17	1		T14	204
valid_sources[0x4a]	5975	1			T12	972		T14	165		T15	1400
valid_sources[0x4b]	5973	1			T6	2		T12	985		T17	1
valid_sources[0x4c]	6075	1			T12	1035		T17	1		T14	118
valid_sources[0x4d]	7495	1			T12	997		T14	129		T15	2933
valid_sources[0x4e]	7043	1			T2	1		T8	5		T12	1036
valid_sources[0x4f]	6030	1			T12	1018		T14	211		T15	943
valid_sources[0x50]	6038	1			T12	1022		T14	145		T15	1141
valid_sources[0x51]	5799	1			T12	1001		T17	1		T14	217
valid_sources[0x52]	8599	1			T6	2		T12	986		T17	2
valid_sources[0x53]	6525	1			T6	1		T12	977		T17	2
valid_sources[0x54]	7997	1			T12	994		T17	2		T14	199
valid_sources[0x55]	6146	1			T12	1079		T14	156		T15	1015
valid_sources[0x56]	8542	1			T2	1		T12	1029		T14	261
valid_sources[0x57]	6971	1			T12	1082		T17	3		T14	196
valid_sources[0x58]	8168	1			T6	8		T12	996		T14	168
valid_sources[0x59]	7068	1			T6	24		T12	985		T17	5
valid_sources[0x5a]	5997	1			T12	1019		T14	175		T15	1211
valid_sources[0x5b]	8513	1			T12	1088		T17	3		T14	167
valid_sources[0x5c]	7176	1			T3	1		T12	1009		T17	1
valid_sources[0x5d]	5969	1			T3	1		T12	1005		T17	1
valid_sources[0x5e]	6827	1			T12	1021		T14	228		T15	2006
valid_sources[0x5f]	7740	1			T3	2		T12	1077		T17	1
valid_sources[0x60]	7054	1			T2	1		T3	1		T12	1041
valid_sources[0x61]	6493	1			T12	1046		T17	2		T14	163
valid_sources[0x62]	6040	1			T12	1059		T17	2		T14	165
valid_sources[0x63]	8087	1			T12	1009		T14	126		T15	2761
valid_sources[0x64]	8703	1			T12	1107		T14	184		T15	3372
valid_sources[0x65]	6515	1			T12	1017		T17	3		T14	120
valid_sources[0x66]	8486	1			T12	1040		T14	151		T15	3457
valid_sources[0x67]	6947	1			T12	1075		T17	1		T14	71
valid_sources[0x68]	7102	1			T6	8		T12	1059		T14	212
valid_sources[0x69]	8821	1			T12	1072		T17	1		T14	117
valid_sources[0x6a]	7843	1			T2	1		T12	983		T17	1
valid_sources[0x6b]	5842	1			T3	1		T6	5		T12	991
valid_sources[0x6c]	8069	1			T3	2		T12	1077		T17	1
valid_sources[0x6d]	7861	1			T12	1035		T14	125		T15	3180
valid_sources[0x6e]	5563	1			T8	2		T12	1053		T17	2
valid_sources[0x6f]	5178	1			T12	1015		T17	2		T14	125
valid_sources[0x70]	6197	1			T12	1055		T17	2		T14	96
valid_sources[0x71]	5563	1			T2	1		T6	3		T12	1046
valid_sources[0x72]	7829	1			T2	1		T12	1066		T14	102
valid_sources[0x73]	6306	1			T12	972		T13	9		T17	3
valid_sources[0x74]	8720	1			T8	16		T12	1018		T14	132
valid_sources[0x75]	6343	1			T6	23		T12	1008		T14	122
valid_sources[0x76]	6353	1			T12	1056		T17	3		T14	135
valid_sources[0x77]	6059	1			T12	1022		T17	1		T14	204
valid_sources[0x78]	8015	1			T2	1		T6	2		T12	1058
valid_sources[0x79]	6273	1			T8	3		T12	1027		T14	140
valid_sources[0x7a]	6543	1			T12	968		T14	200		T15	1918
valid_sources[0x7b]	7614	1			T12	1059		T17	1		T14	227
valid_sources[0x7c]	6351	1			T2	2		T12	1129		T14	155
valid_sources[0x7d]	7121	1			T2	1		T12	1043		T17	1
valid_sources[0x7e]	6453	1			T12	970		T14	221		T15	1782
valid_sources[0x7f]	6143	1			T2	1		T3	1		T12	1019
valid_sources[0x80]	6800	1			T6	1		T12	1113		T14	177

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

436521

1

T2

3

T3

9

T6

34

values[0x0]

all_enables

biggest_size

651588

1

T12

97006

T14

15212

T15

195113

values[0x1]

all_enables

biggest_size

651835

1

T12

96869

T14

15346

T15

195915

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126129	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1322738

1

T1

3

T2

7

T3

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	355669	1			T2	16		T3	32		T4	1
values[0x0]	505550	1			T1	4		T5	4		T7	7
values[0x1]	587648	1			T1	8		T5	4		T7	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55191	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1393676

1

T1

5

T2

10

T3

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5238	1			T12	962		T14	122		T15	1653
valid_sources[0x01]	6348	1			T12	819		T14	130		T15	1653
valid_sources[0x02]	6151	1			T12	671		T14	130		T15	1593
valid_sources[0x03]	6246	1			T12	684		T13	1		T14	143
valid_sources[0x04]	6331	1			T12	902		T14	119		T15	1626
valid_sources[0x05]	5733	1			T12	720		T14	147		T15	1739
valid_sources[0x06]	6078	1			T12	707		T14	127		T15	1751
valid_sources[0x07]	5461	1			T8	1		T12	843		T14	102
valid_sources[0x08]	5415	1			T12	899		T14	95		T15	1620
valid_sources[0x09]	5586	1			T12	764		T14	102		T15	1725
valid_sources[0x0a]	5472	1			T8	1		T12	786		T13	1
valid_sources[0x0b]	5799	1			T12	1000		T14	107		T15	1709
valid_sources[0x0c]	5383	1			T12	765		T14	139		T15	1680
valid_sources[0x0d]	5127	1			T3	1		T12	713		T13	1
valid_sources[0x0e]	5070	1			T12	806		T14	91		T15	1675
valid_sources[0x0f]	6088	1			T12	981		T14	120		T15	1691
valid_sources[0x10]	5451	1			T12	949		T14	106		T15	1669
valid_sources[0x11]	5440	1			T8	1		T12	797		T14	163
valid_sources[0x12]	5638	1			T2	2		T8	2		T12	798
valid_sources[0x13]	5741	1			T12	833		T14	120		T15	1608
valid_sources[0x14]	5571	1			T1	1		T12	785		T14	106
valid_sources[0x15]	5321	1			T12	802		T14	112		T15	1592
valid_sources[0x16]	6049	1			T12	845		T13	1		T14	114
valid_sources[0x17]	6503	1			T1	1		T12	763		T14	103
valid_sources[0x18]	6138	1			T12	822		T14	104		T15	1656
valid_sources[0x19]	5719	1			T8	1		T12	776		T14	130
valid_sources[0x1a]	6147	1			T12	812		T14	161		T15	1657
valid_sources[0x1b]	5855	1			T8	1		T12	839		T14	118
valid_sources[0x1c]	5440	1			T12	1019		T14	134		T15	1677
valid_sources[0x1d]	6812	1			T3	5		T12	981		T14	120
valid_sources[0x1e]	5255	1			T12	669		T14	109		T15	1611
valid_sources[0x1f]	4898	1			T3	2		T8	1		T12	763
valid_sources[0x20]	5906	1			T12	811		T13	1		T14	123
valid_sources[0x21]	5770	1			T12	840		T14	138		T15	1720
valid_sources[0x22]	5656	1			T12	1033		T14	162		T15	1752
valid_sources[0x23]	5534	1			T5	2		T12	933		T14	122
valid_sources[0x24]	5549	1			T12	932		T14	122		T15	1731
valid_sources[0x25]	5179	1			T12	828		T14	145		T15	1669
valid_sources[0x26]	5585	1			T12	914		T13	1		T14	122
valid_sources[0x27]	5559	1			T12	691		T14	91		T15	1660
valid_sources[0x28]	5364	1			T12	776		T14	116		T15	1724
valid_sources[0x29]	6453	1			T12	887		T14	112		T15	1643
valid_sources[0x2a]	5145	1			T3	2		T8	1		T12	577
valid_sources[0x2b]	4916	1			T12	605		T14	111		T15	1681
valid_sources[0x2c]	6107	1			T12	954		T14	107		T15	1732
valid_sources[0x2d]	6060	1			T12	725		T14	115		T15	1668
valid_sources[0x2e]	6110	1			T12	953		T14	135		T15	1704
valid_sources[0x2f]	4889	1			T12	724		T14	84		T15	1694
valid_sources[0x30]	6118	1			T2	2		T3	2		T12	710
valid_sources[0x31]	5284	1			T12	787		T14	133		T15	1700
valid_sources[0x32]	5155	1			T12	873		T14	126		T15	1668
valid_sources[0x33]	5799	1			T12	818		T14	126		T15	1724
valid_sources[0x34]	5957	1			T12	789		T14	106		T15	1664
valid_sources[0x35]	5787	1			T12	495		T14	97		T15	1677
valid_sources[0x36]	6093	1			T12	967		T14	84		T15	1663
valid_sources[0x37]	6088	1			T12	992		T14	160		T15	1697
valid_sources[0x38]	5889	1			T12	806		T14	88		T15	1717
valid_sources[0x39]	5484	1			T12	757		T14	149		T15	1742
valid_sources[0x3a]	5776	1			T2	2		T12	750		T14	136
valid_sources[0x3b]	6065	1			T12	641		T13	1		T14	115
valid_sources[0x3c]	5351	1			T8	1		T12	890		T14	124
valid_sources[0x3d]	5112	1			T12	762		T14	154		T15	1686
valid_sources[0x3e]	6257	1			T12	941		T13	2		T14	117
valid_sources[0x3f]	5638	1			T12	731		T14	104		T15	1638
valid_sources[0x40]	5923	1			T12	774		T14	153		T15	1625
valid_sources[0x41]	5427	1			T12	709		T14	123		T15	1668
valid_sources[0x42]	6350	1			T12	949		T14	148		T15	1724
valid_sources[0x43]	5742	1			T12	914		T14	131		T15	1649
valid_sources[0x44]	5355	1			T12	814		T14	148		T15	1715
valid_sources[0x45]	5931	1			T12	852		T13	1		T14	155
valid_sources[0x46]	5045	1			T12	1047		T13	1		T14	143
valid_sources[0x47]	6238	1			T11	23		T12	977		T14	150
valid_sources[0x48]	5690	1			T8	3		T12	783		T14	89
valid_sources[0x49]	5308	1			T12	877		T14	133		T15	1748
valid_sources[0x4a]	5678	1			T12	910		T14	128		T15	1638
valid_sources[0x4b]	6249	1			T1	1		T3	1		T12	896
valid_sources[0x4c]	5450	1			T12	756		T14	93		T15	1689
valid_sources[0x4d]	6032	1			T12	671		T14	165		T15	1638
valid_sources[0x4e]	5565	1			T12	672		T14	126		T15	1725
valid_sources[0x4f]	5665	1			T8	1		T12	863		T14	171
valid_sources[0x50]	5419	1			T12	867		T13	1		T14	106
valid_sources[0x51]	5525	1			T12	843		T13	1		T14	109
valid_sources[0x52]	5208	1			T12	742		T14	152		T15	1705
valid_sources[0x53]	5700	1			T12	885		T14	109		T15	1684
valid_sources[0x54]	6066	1			T12	883		T14	113		T15	1712
valid_sources[0x55]	5590	1			T12	933		T14	163		T15	1724
valid_sources[0x56]	5185	1			T12	705		T14	85		T15	1613
valid_sources[0x57]	5489	1			T12	887		T13	1		T14	93
valid_sources[0x58]	4801	1			T4	1		T8	1		T12	646
valid_sources[0x59]	6145	1			T12	1009		T14	155		T15	1686
valid_sources[0x5a]	5588	1			T12	717		T14	120		T15	1592
valid_sources[0x5b]	5921	1			T12	774		T14	80		T15	1680
valid_sources[0x5c]	6034	1			T5	1		T8	1		T12	721
valid_sources[0x5d]	5168	1			T12	936		T14	96		T15	1663
valid_sources[0x5e]	5115	1			T12	747		T14	129		T15	1599
valid_sources[0x5f]	5278	1			T12	754		T14	125		T15	1726
valid_sources[0x60]	5763	1			T12	1258		T14	102		T15	1757
valid_sources[0x61]	5118	1			T2	1		T12	703		T14	114
valid_sources[0x62]	5173	1			T8	1		T12	836		T14	109
valid_sources[0x63]	5477	1			T12	614		T14	134		T15	1713
valid_sources[0x64]	5618	1			T8	1		T12	889		T14	121
valid_sources[0x65]	5458	1			T12	752		T14	116		T15	1657
valid_sources[0x66]	5679	1			T12	779		T14	133		T15	1686
valid_sources[0x67]	6095	1			T12	880		T14	87		T15	1702
valid_sources[0x68]	5584	1			T12	792		T14	129		T15	1647
valid_sources[0x69]	5627	1			T12	874		T14	131		T15	1711
valid_sources[0x6a]	5946	1			T8	1		T12	866		T14	138
valid_sources[0x6b]	5808	1			T12	736		T14	134		T15	1701
valid_sources[0x6c]	5434	1			T12	512		T14	127		T15	1682
valid_sources[0x6d]	5825	1			T12	918		T14	144		T15	1649
valid_sources[0x6e]	5774	1			T12	801		T14	115		T15	1751
valid_sources[0x6f]	5786	1			T12	1100		T14	142		T15	1621
valid_sources[0x70]	5274	1			T12	810		T14	135		T15	1681
valid_sources[0x71]	6533	1			T12	701		T14	166		T15	1776
valid_sources[0x72]	5044	1			T12	846		T14	113		T15	1662
valid_sources[0x73]	6144	1			T8	1		T12	750		T14	130
valid_sources[0x74]	6448	1			T12	696		T14	146		T15	1742
valid_sources[0x75]	5953	1			T1	2		T12	785		T14	97
valid_sources[0x76]	5278	1			T12	896		T14	115		T15	1696
valid_sources[0x77]	5745	1			T12	754		T14	140		T15	1610
valid_sources[0x78]	5130	1			T7	12		T12	876		T14	89
valid_sources[0x79]	5564	1			T1	5		T12	703		T14	103
valid_sources[0x7a]	5305	1			T12	936		T14	134		T15	1650
valid_sources[0x7b]	5363	1			T12	909		T14	122		T15	1621
valid_sources[0x7c]	5360	1			T12	797		T14	121		T15	1693
valid_sources[0x7d]	5714	1			T1	1		T12	768		T13	1
valid_sources[0x7e]	6071	1			T3	1		T8	1		T12	953
valid_sources[0x7f]	6041	1			T12	1175		T14	144		T15	1665
valid_sources[0x80]	5820	1			T12	869		T14	114		T15	1715

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

331145

1

T2

7

T3

15

T8

21

values[0x0]

all_enables

biggest_size

495207

1

T1

1

T5

1

T7

5

values[0x1]

all_enables

biggest_size

496386

1

T1

2

T7

2

T12

71836