Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3181160

1

T2

39

T3

63

T6

357

full_word

2032265

1

T2

3

T3

9

T6

34

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	5213125	1			T2	42		T3	72		T6	391
auto[TlIntgErrCmd]	93	1			T53	3		T54	6		T55	10
auto[TlIntgErrData]	100	1			T53	2		T54	4		T55	3
auto[TlIntgErrBoth]	107	1			T53	5		T54	10		T55	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

817008

1

T2

42

T3

72

T6

391

auto[1]

4396417

1

T12

652467

T14

102432

T15

131822

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	337318	1			T2	39		T3	63		T6	357
auto[TlIntgErrNone]	partial	auto[1]	2843566	1			T12	421307		T14	66132		T15	852415
auto[TlIntgErrNone]	full_word	auto[0]	479550	1			T2	3		T3	9		T6	34
auto[TlIntgErrNone]	full_word	auto[1]	1552691	1			T12	231160		T14	36300		T15	465805
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T53	1		T54	2		T55	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T53	1		T54	4		T55	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T109	1		T113	1		T115	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T53	1		T55	1		T113	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T53	1		T54	3		T109	1
auto[TlIntgErrData]	partial	auto[1]	36	1			T53	1		T54	1		T55	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T114	1		T116	1		T111	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T106	1		T116	1		T107	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T53	2		T54	1		T55	3
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T53	3		T54	6		T55	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T54	2		T115	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T54	1		T55	2		T109	1