Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	72467	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2335822

1

T2

10

T5

31518

T9

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	609419	1			T2	85		T5	8199		T9	42
values[0x0]	883859	1			T5	11947		T11	28110		T12	31939
values[0x1]	915011	1			T5	12366		T11	29212		T12	32782

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39463	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2368826

1

T2

45

T5

31943

T9

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9323	1			T5	128		T11	327		T17	3
valid_sources[0x01]	9297	1			T5	143		T11	291		T14	12
valid_sources[0x02]	9367	1			T5	108		T11	290		T17	1
valid_sources[0x03]	9326	1			T5	100		T11	272		T47	2
valid_sources[0x04]	9464	1			T5	134		T11	278		T99	1
valid_sources[0x05]	9205	1			T5	122		T11	340		T99	3
valid_sources[0x06]	9217	1			T5	132		T11	269		T47	1
valid_sources[0x07]	9347	1			T5	126		T10	2		T11	376
valid_sources[0x08]	9442	1			T5	124		T11	315		T99	7
valid_sources[0x09]	9249	1			T5	138		T11	315		T44	19
valid_sources[0x0a]	9167	1			T5	124		T11	282		T17	2
valid_sources[0x0b]	9398	1			T5	113		T10	6		T11	313
valid_sources[0x0c]	9097	1			T5	128		T11	297		T47	1
valid_sources[0x0d]	9469	1			T5	129		T11	306		T99	5
valid_sources[0x0e]	10951	1			T5	118		T10	2		T11	307
valid_sources[0x0f]	9088	1			T5	120		T16	6		T11	244
valid_sources[0x10]	9309	1			T5	136		T11	277		T17	1
valid_sources[0x11]	9155	1			T5	146		T10	2		T11	252
valid_sources[0x12]	9229	1			T5	140		T11	292		T100	1
valid_sources[0x13]	9568	1			T5	127		T11	300		T17	1
valid_sources[0x14]	9215	1			T5	131		T16	2		T11	298
valid_sources[0x15]	10616	1			T5	115		T11	250		T99	2
valid_sources[0x16]	9247	1			T5	135		T11	313		T101	3
valid_sources[0x17]	9323	1			T5	130		T10	1		T11	320
valid_sources[0x18]	9269	1			T5	124		T9	21		T10	6
valid_sources[0x19]	10429	1			T5	113		T11	350		T17	1
valid_sources[0x1a]	9303	1			T5	110		T10	1		T11	260
valid_sources[0x1b]	9700	1			T5	97		T11	282		T99	1
valid_sources[0x1c]	9170	1			T5	120		T11	281		T17	2
valid_sources[0x1d]	9322	1			T5	131		T11	341		T47	1
valid_sources[0x1e]	9479	1			T5	134		T11	296		T47	1
valid_sources[0x1f]	9773	1			T5	109		T11	238		T118	4
valid_sources[0x20]	9175	1			T5	151		T11	259		T47	2
valid_sources[0x21]	9314	1			T5	142		T11	296		T13	6
valid_sources[0x22]	9187	1			T5	138		T11	377		T17	1
valid_sources[0x23]	9089	1			T5	132		T11	256		T99	11
valid_sources[0x24]	9121	1			T5	111		T11	306		T67	15
valid_sources[0x25]	9315	1			T5	134		T11	304		T45	1
valid_sources[0x26]	9108	1			T5	115		T11	324		T17	2
valid_sources[0x27]	10148	1			T5	128		T16	7		T11	281
valid_sources[0x28]	9232	1			T5	145		T11	265		T17	2
valid_sources[0x29]	9211	1			T5	136		T11	302		T98	4
valid_sources[0x2a]	9242	1			T5	131		T11	338		T47	2
valid_sources[0x2b]	9985	1			T5	131		T11	349		T17	2
valid_sources[0x2c]	9472	1			T5	106		T11	347		T47	1
valid_sources[0x2d]	9698	1			T5	107		T11	278		T99	3
valid_sources[0x2e]	9648	1			T5	144		T11	299		T100	3
valid_sources[0x2f]	9442	1			T5	121		T11	326		T18	26
valid_sources[0x30]	9164	1			T5	140		T11	327		T100	1
valid_sources[0x31]	9144	1			T5	134		T10	1		T11	302
valid_sources[0x32]	9250	1			T5	128		T11	275		T45	3
valid_sources[0x33]	9285	1			T5	143		T11	305		T17	1
valid_sources[0x34]	9195	1			T5	115		T11	270		T45	1
valid_sources[0x35]	9266	1			T5	142		T10	4		T11	296
valid_sources[0x36]	9263	1			T5	118		T11	305		T45	1
valid_sources[0x37]	9312	1			T5	126		T11	316		T99	7
valid_sources[0x38]	9669	1			T5	123		T11	327		T47	1
valid_sources[0x39]	9224	1			T5	123		T11	294		T47	2
valid_sources[0x3a]	9491	1			T5	141		T11	299		T17	1
valid_sources[0x3b]	8983	1			T5	120		T11	334		T100	2
valid_sources[0x3c]	9301	1			T5	135		T11	284		T45	1
valid_sources[0x3d]	9027	1			T2	25		T5	103		T11	265
valid_sources[0x3e]	9383	1			T5	122		T16	1		T11	322
valid_sources[0x3f]	9122	1			T5	106		T11	296		T99	7
valid_sources[0x40]	9764	1			T5	162		T11	274		T98	8
valid_sources[0x41]	9283	1			T5	131		T16	5		T11	243
valid_sources[0x42]	9189	1			T5	125		T11	363		T118	4
valid_sources[0x43]	9243	1			T5	142		T11	318		T99	6
valid_sources[0x44]	9955	1			T5	111		T11	342		T100	1
valid_sources[0x45]	9723	1			T2	43		T5	145		T11	322
valid_sources[0x46]	9091	1			T5	110		T10	1		T11	324
valid_sources[0x47]	9179	1			T5	136		T11	297		T17	2
valid_sources[0x48]	9170	1			T5	125		T10	1		T11	270
valid_sources[0x49]	9264	1			T5	119		T11	303		T12	325
valid_sources[0x4a]	9314	1			T5	120		T11	341		T47	1
valid_sources[0x4b]	9518	1			T5	131		T10	1		T11	293
valid_sources[0x4c]	9391	1			T5	140		T11	255		T12	361
valid_sources[0x4d]	9136	1			T5	114		T11	277		T17	1
valid_sources[0x4e]	9006	1			T5	125		T11	272		T100	1
valid_sources[0x4f]	9145	1			T5	135		T11	274		T100	1
valid_sources[0x50]	9378	1			T5	129		T11	292		T47	2
valid_sources[0x51]	9219	1			T5	125		T11	310		T101	6
valid_sources[0x52]	9417	1			T5	103		T11	304		T45	1
valid_sources[0x53]	9170	1			T5	129		T11	298		T17	1
valid_sources[0x54]	9442	1			T5	129		T10	1		T11	298
valid_sources[0x55]	9319	1			T5	118		T11	325		T67	14
valid_sources[0x56]	9649	1			T5	139		T11	313		T99	5
valid_sources[0x57]	9954	1			T5	136		T11	341		T47	2
valid_sources[0x58]	9431	1			T5	124		T11	328		T17	1
valid_sources[0x59]	9935	1			T5	130		T11	306		T98	4
valid_sources[0x5a]	9317	1			T2	17		T5	144		T11	342
valid_sources[0x5b]	9377	1			T5	111		T10	8		T11	326
valid_sources[0x5c]	9315	1			T5	121		T11	346		T17	2
valid_sources[0x5d]	10036	1			T5	110		T11	312		T17	1
valid_sources[0x5e]	9644	1			T5	112		T11	264		T99	7
valid_sources[0x5f]	9185	1			T5	145		T10	1		T11	280
valid_sources[0x60]	9283	1			T5	119		T11	251		T17	1
valid_sources[0x61]	9421	1			T5	120		T11	314		T31	5
valid_sources[0x62]	9467	1			T5	137		T11	324		T67	54
valid_sources[0x63]	8946	1			T5	151		T11	259		T45	1
valid_sources[0x64]	9219	1			T5	115		T11	273		T99	6
valid_sources[0x65]	9385	1			T5	134		T11	349		T99	1
valid_sources[0x66]	9866	1			T5	151		T11	289		T47	3
valid_sources[0x67]	9851	1			T5	141		T10	2		T11	319
valid_sources[0x68]	9304	1			T5	132		T11	328		T17	1
valid_sources[0x69]	9394	1			T5	112		T11	367		T17	3
valid_sources[0x6a]	9526	1			T5	125		T11	339		T17	1
valid_sources[0x6b]	9402	1			T5	121		T10	1		T11	299
valid_sources[0x6c]	9570	1			T5	130		T10	1		T11	291
valid_sources[0x6d]	9009	1			T5	150		T11	247		T17	2
valid_sources[0x6e]	9170	1			T5	133		T11	268		T17	1
valid_sources[0x6f]	9695	1			T5	132		T11	229		T17	2
valid_sources[0x70]	9267	1			T5	110		T11	275		T98	10
valid_sources[0x71]	9220	1			T5	104		T11	328		T17	1
valid_sources[0x72]	9543	1			T5	103		T10	2		T11	395
valid_sources[0x73]	9356	1			T5	139		T11	280		T99	1
valid_sources[0x74]	9002	1			T5	131		T11	320		T17	2
valid_sources[0x75]	9783	1			T5	111		T11	329		T100	6
valid_sources[0x76]	9446	1			T5	102		T15	13		T11	269
valid_sources[0x77]	9721	1			T5	130		T11	321		T18	15
valid_sources[0x78]	9368	1			T5	115		T11	269		T100	1
valid_sources[0x79]	9127	1			T5	102		T11	258		T118	4
valid_sources[0x7a]	9497	1			T5	134		T11	307		T67	21
valid_sources[0x7b]	9180	1			T5	111		T11	286		T12	349
valid_sources[0x7c]	9258	1			T5	142		T11	260		T99	1
valid_sources[0x7d]	9342	1			T5	128		T16	6		T11	291
valid_sources[0x7e]	9464	1			T5	121		T11	263		T45	1
valid_sources[0x7f]	9264	1			T5	109		T10	1		T11	294
valid_sources[0x80]	9263	1			T5	147		T11	280		T100	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

585165

1

T2

10

T5

7854

T9

3

values[0x0]

all_enables

biggest_size

875945

1

T5

11837

T11

27832

T12

31663

values[0x1]

all_enables

biggest_size

874712

1

T5

11827

T11

27973

T12

31397

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	168598	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1800496

1

T2

20

T4

6

T5

25061

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	483670	1			T2	32		T3	1		T5	6802
values[0x0]	687890	1			T1	1		T4	11		T5	9587
values[0x1]	797534	1			T4	11		T5	10913		T8	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	73428	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1895666

1

T2

20

T4

9

T5

26326

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8554	1			T5	86		T11	503		T17	11
valid_sources[0x01]	7343	1			T5	108		T10	1		T11	364
valid_sources[0x02]	8195	1			T5	123		T11	199		T12	662
valid_sources[0x03]	8111	1			T5	83		T10	2		T11	254
valid_sources[0x04]	8197	1			T5	104		T11	259		T12	867
valid_sources[0x05]	6631	1			T5	130		T11	7		T12	525
valid_sources[0x06]	7598	1			T5	114		T16	6		T11	205
valid_sources[0x07]	9617	1			T5	84		T10	1		T11	1087
valid_sources[0x08]	8424	1			T5	133		T11	955		T65	1
valid_sources[0x09]	7428	1			T4	1		T5	103		T8	1
valid_sources[0x0a]	10404	1			T5	119		T11	647		T12	1126
valid_sources[0x0b]	8580	1			T5	110		T11	831		T12	660
valid_sources[0x0c]	7213	1			T4	1		T5	98		T11	14
valid_sources[0x0d]	8214	1			T5	103		T11	193		T12	273
valid_sources[0x0e]	8560	1			T5	99		T10	1		T11	474
valid_sources[0x0f]	7915	1			T5	114		T10	2		T11	233
valid_sources[0x10]	9196	1			T1	1		T5	93		T11	378
valid_sources[0x11]	7737	1			T4	1		T5	101		T11	198
valid_sources[0x12]	7280	1			T5	96		T11	12		T12	21
valid_sources[0x13]	7851	1			T5	110		T11	301		T14	3
valid_sources[0x14]	7664	1			T5	96		T11	745		T32	162
valid_sources[0x15]	7739	1			T5	112		T10	1		T11	65
valid_sources[0x16]	7321	1			T5	107		T11	343		T101	3
valid_sources[0x17]	7558	1			T4	1		T5	117		T11	88
valid_sources[0x18]	8077	1			T5	95		T11	488		T12	587
valid_sources[0x19]	7278	1			T5	104		T11	109		T12	761
valid_sources[0x1a]	8127	1			T5	111		T7	6		T11	329
valid_sources[0x1b]	6937	1			T5	104		T11	382		T12	186
valid_sources[0x1c]	8050	1			T5	115		T11	141		T61	1
valid_sources[0x1d]	8235	1			T5	103		T11	662		T12	385
valid_sources[0x1e]	7369	1			T5	102		T8	1		T10	1
valid_sources[0x1f]	7278	1			T5	116		T16	1		T11	19
valid_sources[0x20]	8690	1			T5	99		T11	174		T12	151
valid_sources[0x21]	8242	1			T5	111		T11	8		T12	638
valid_sources[0x22]	8609	1			T4	1		T5	105		T11	586
valid_sources[0x23]	7280	1			T5	97		T11	7		T65	2
valid_sources[0x24]	8091	1			T4	1		T5	91		T12	101
valid_sources[0x25]	6138	1			T5	87		T11	125		T12	75
valid_sources[0x26]	7676	1			T4	1		T5	98		T10	1
valid_sources[0x27]	7024	1			T5	106		T11	569		T12	148
valid_sources[0x28]	7688	1			T5	94		T11	178		T32	65
valid_sources[0x29]	7818	1			T5	133		T13	16		T35	3
valid_sources[0x2a]	8632	1			T5	107		T8	1		T9	1
valid_sources[0x2b]	8534	1			T5	110		T11	631		T27	8
valid_sources[0x2c]	7385	1			T5	77		T11	5		T44	2
valid_sources[0x2d]	7624	1			T5	152		T12	14		T32	498
valid_sources[0x2e]	8021	1			T5	120		T11	3		T14	1
valid_sources[0x2f]	7941	1			T5	108		T11	6		T12	978
valid_sources[0x30]	7968	1			T5	103		T9	1		T14	5
valid_sources[0x31]	7492	1			T5	80		T8	1		T11	281
valid_sources[0x32]	7603	1			T5	90		T11	325		T17	2
valid_sources[0x33]	6680	1			T5	88		T11	2		T61	1
valid_sources[0x34]	8169	1			T5	123		T11	64		T12	24
valid_sources[0x35]	7241	1			T5	116		T11	330		T18	2
valid_sources[0x36]	8217	1			T5	133		T11	181		T12	735
valid_sources[0x37]	7349	1			T5	108		T11	133		T12	471
valid_sources[0x38]	7089	1			T5	117		T11	7		T17	1
valid_sources[0x39]	6666	1			T2	32		T5	125		T11	284
valid_sources[0x3a]	7994	1			T5	123		T11	178		T12	277
valid_sources[0x3b]	7595	1			T5	110		T8	1		T11	12
valid_sources[0x3c]	6796	1			T5	101		T11	184		T12	219
valid_sources[0x3d]	7313	1			T5	121		T11	662		T12	93
valid_sources[0x3e]	7345	1			T5	99		T10	1		T32	212
valid_sources[0x3f]	7617	1			T5	128		T11	1		T12	726
valid_sources[0x40]	7224	1			T5	93		T9	1		T11	251
valid_sources[0x41]	8059	1			T5	105		T11	170		T12	381
valid_sources[0x42]	7753	1			T5	85		T12	53		T32	431
valid_sources[0x43]	9034	1			T5	106		T11	516		T18	2
valid_sources[0x44]	8141	1			T5	101		T11	295		T12	117
valid_sources[0x45]	7489	1			T5	131		T11	21		T12	279
valid_sources[0x46]	7282	1			T5	113		T11	229		T61	1
valid_sources[0x47]	7502	1			T5	122		T11	377		T29	1
valid_sources[0x48]	7492	1			T5	112		T10	1		T11	211
valid_sources[0x49]	7263	1			T5	103		T11	147		T64	2
valid_sources[0x4a]	7682	1			T5	103		T11	185		T12	204
valid_sources[0x4b]	8362	1			T5	125		T10	1		T11	972
valid_sources[0x4c]	8068	1			T5	99		T11	11		T12	344
valid_sources[0x4d]	7130	1			T5	96		T11	133		T18	2
valid_sources[0x4e]	7564	1			T4	1		T5	86		T11	208
valid_sources[0x4f]	7791	1			T5	63		T11	26		T12	370
valid_sources[0x50]	7871	1			T5	116		T10	1		T11	98
valid_sources[0x51]	7616	1			T4	1		T5	99		T11	409
valid_sources[0x52]	8169	1			T5	113		T11	329		T12	579
valid_sources[0x53]	8211	1			T5	130		T11	75		T18	1
valid_sources[0x54]	7926	1			T5	98		T12	521		T32	274
valid_sources[0x55]	8526	1			T5	95		T10	1		T11	593
valid_sources[0x56]	7562	1			T5	101		T11	112		T12	79
valid_sources[0x57]	7645	1			T5	103		T9	1		T11	278
valid_sources[0x58]	7624	1			T5	82		T11	470		T12	53
valid_sources[0x59]	7351	1			T5	109		T10	1		T65	1
valid_sources[0x5a]	7680	1			T5	110		T9	4		T11	214
valid_sources[0x5b]	7836	1			T5	124		T11	351		T12	540
valid_sources[0x5c]	6904	1			T4	1		T5	125		T11	271
valid_sources[0x5d]	8239	1			T5	117		T11	171		T35	5
valid_sources[0x5e]	7969	1			T5	111		T10	2		T11	275
valid_sources[0x5f]	7830	1			T5	117		T11	570		T12	273
valid_sources[0x60]	7901	1			T5	104		T11	189		T12	135
valid_sources[0x61]	8109	1			T5	128		T9	2		T11	196
valid_sources[0x62]	7896	1			T5	103		T10	1		T11	158
valid_sources[0x63]	7179	1			T5	112		T11	135		T20	9
valid_sources[0x64]	7181	1			T5	110		T11	99		T66	10
valid_sources[0x65]	8116	1			T5	113		T11	220		T14	2
valid_sources[0x66]	7118	1			T5	94		T11	222		T42	1
valid_sources[0x67]	7697	1			T5	109		T11	281		T42	2
valid_sources[0x68]	7657	1			T5	93		T11	123		T49	1
valid_sources[0x69]	6396	1			T5	100		T11	8		T18	1
valid_sources[0x6a]	7673	1			T5	96		T10	1		T11	584
valid_sources[0x6b]	7474	1			T5	111		T11	577		T12	21
valid_sources[0x6c]	7086	1			T4	1		T5	108		T11	8
valid_sources[0x6d]	8772	1			T5	122		T11	689		T12	421
valid_sources[0x6e]	7949	1			T5	111		T8	1		T11	1043
valid_sources[0x6f]	7595	1			T5	104		T7	12		T8	2
valid_sources[0x70]	9516	1			T5	113		T11	662		T12	469
valid_sources[0x71]	7454	1			T5	135		T11	90		T12	169
valid_sources[0x72]	7841	1			T5	127		T11	2		T20	2
valid_sources[0x73]	7560	1			T5	109		T11	250		T12	244
valid_sources[0x74]	7405	1			T5	82		T11	2		T65	4
valid_sources[0x75]	8056	1			T3	1		T5	104		T11	635
valid_sources[0x76]	7788	1			T5	81		T11	279		T61	1
valid_sources[0x77]	7577	1			T5	119		T12	612		T32	114
valid_sources[0x78]	7980	1			T5	108		T11	205		T12	253
valid_sources[0x79]	7785	1			T5	129		T11	136		T12	127
valid_sources[0x7a]	7082	1			T5	93		T11	254		T12	462
valid_sources[0x7b]	7387	1			T5	102		T9	1		T16	4
valid_sources[0x7c]	7605	1			T5	99		T11	267		T12	167
valid_sources[0x7d]	8608	1			T5	101		T10	1		T11	673
valid_sources[0x7e]	7642	1			T5	96		T11	219		T44	1
valid_sources[0x7f]	7390	1			T5	103		T16	1		T11	87
valid_sources[0x80]	6866	1			T5	99		T17	19		T49	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

451209

1

T2

20

T5

6340

T7

11

values[0x0]

all_enables

biggest_size

674133

1

T4

4

T5

9413

T8

2

values[0x1]

all_enables

biggest_size

675154

1

T4

2

T5

9308

T8

2