Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4271233

1

T2

75

T5

58596

T9

39

full_word

2728556

1

T2

10

T5

36724

T9

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6999509	1			T2	85		T5	95320		T9	42
auto[TlIntgErrCmd]	96	1			T58	9		T59	3		T60	5
auto[TlIntgErrData]	86	1			T58	5		T59	4		T105	1
auto[TlIntgErrBoth]	98	1			T58	6		T59	3		T60	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087138

1

T2

85

T5

14817

T9

42

auto[1]

5912651

1

T5

80503

T11

190425

T12

211904

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	444984	1			T2	75		T5	6240		T9	39
auto[TlIntgErrNone]	partial	auto[1]	3825986	1			T5	52356		T11	123598		T12	136622
auto[TlIntgErrNone]	full_word	auto[0]	642042	1			T2	10		T5	8577		T9	3
auto[TlIntgErrNone]	full_word	auto[1]	2086497	1			T5	28147		T11	66827		T12	75282
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T105	1		T106	1		T108	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T58	6		T59	3		T60	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T58	2		T60	1		T108	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T58	1		T106	2		T107	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T59	1		T106	2		T107	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T58	5		T59	3		T105	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T107	1		T111	1		T112	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T113	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T58	2		T59	2		T60	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T58	4		T59	1		T60	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T106	1		T110	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T113	1		T114	1		-	-