Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15120	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36632

1

T6

3

T7

24

T8

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24844	1			T6	3		T7	257		T8	22
values[0x0]	13158	1			T14	2582		T15	4260		T16	2502
values[0x1]	13750	1			T14	2691		T15	4344		T16	2696

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6841	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

44911

1

T6

3

T7

163

T8

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	135	1			T7	9		T17	1		T102	1
valid_sources[0x01]	109	1			T11	1		T112	2		T113	3
valid_sources[0x02]	476	1			T7	1		T18	2		T102	2
valid_sources[0x03]	153	1			T102	1		T112	3		T113	1
valid_sources[0x04]	163	1			T112	1		T114	23		T113	2
valid_sources[0x05]	113	1			T102	3		T19	3		T112	1
valid_sources[0x06]	154	1			T17	2		T102	6		T12	1
valid_sources[0x07]	113	1			T6	3		T7	3		T102	2
valid_sources[0x08]	279	1			T81	6		T112	1		T113	1
valid_sources[0x09]	273	1			T7	1		T10	24		T17	2
valid_sources[0x0a]	118	1			T7	4		T11	1		T31	1
valid_sources[0x0b]	176	1			T7	2		T10	14		T20	2
valid_sources[0x0c]	112	1			T17	1		T19	1		T115	1
valid_sources[0x0d]	136	1			T7	3		T102	3		T33	16
valid_sources[0x0e]	118	1			T7	1		T8	3		T115	3
valid_sources[0x0f]	460	1			T11	1		T102	2		T112	2
valid_sources[0x10]	88	1			T17	1		T115	1		T113	2
valid_sources[0x11]	180	1			T17	1		T112	1		T113	1
valid_sources[0x12]	101	1			T7	2		T102	2		T115	1
valid_sources[0x13]	138	1			T7	1		T10	20		T112	1
valid_sources[0x14]	123	1			T11	2		T12	3		T115	1
valid_sources[0x15]	160	1			T31	3		T112	1		T116	33
valid_sources[0x16]	147	1			T12	1		T19	1		T115	2
valid_sources[0x17]	657	1			T7	1		T112	5		T113	3
valid_sources[0x18]	216	1			T7	2		T11	1		T102	2
valid_sources[0x19]	113	1			T7	1		T12	1		T112	1
valid_sources[0x1a]	125	1			T7	2		T12	1		T33	1
valid_sources[0x1b]	101	1			T102	1		T82	2		T113	1
valid_sources[0x1c]	149	1			T102	3		T12	2		T112	1
valid_sources[0x1d]	136	1			T7	6		T102	2		T115	3
valid_sources[0x1e]	118	1			T19	1		T33	19		T112	1
valid_sources[0x1f]	131	1			T7	8		T115	5		T113	3
valid_sources[0x20]	138	1			T11	1		T19	1		T33	8
valid_sources[0x21]	142	1			T7	1		T11	1		T12	1
valid_sources[0x22]	145	1			T12	2		T113	1		T54	3
valid_sources[0x23]	636	1			T112	1		T113	1		T15	539
valid_sources[0x24]	107	1			T11	1		T19	6		T115	2
valid_sources[0x25]	101	1			T7	6		T17	1		T19	3
valid_sources[0x26]	107	1			T43	13		T115	2		T112	1
valid_sources[0x27]	124	1			T17	1		T102	2		T12	1
valid_sources[0x28]	652	1			T7	3		T102	1		T31	2
valid_sources[0x29]	538	1			T19	1		T115	3		T112	2
valid_sources[0x2a]	149	1			T7	1		T18	1		T19	8
valid_sources[0x2b]	142	1			T7	1		T17	1		T115	2
valid_sources[0x2c]	337	1			T7	2		T10	120		T17	1
valid_sources[0x2d]	270	1			T11	1		T102	2		T12	1
valid_sources[0x2e]	131	1			T11	2		T102	1		T81	2
valid_sources[0x2f]	107	1			T7	3		T11	1		T102	3
valid_sources[0x30]	138	1			T7	3		T8	2		T17	1
valid_sources[0x31]	114	1			T11	5		T102	1		T115	1
valid_sources[0x32]	151	1			T7	4		T113	1		T117	1
valid_sources[0x33]	152	1			T7	3		T11	1		T102	1
valid_sources[0x34]	125	1			T112	1		T116	11		T113	1
valid_sources[0x35]	153	1			T7	1		T19	3		T33	8
valid_sources[0x36]	118	1			T7	1		T102	1		T115	3
valid_sources[0x37]	96	1			T17	1		T11	1		T82	1
valid_sources[0x38]	146	1			T17	1		T11	2		T102	1
valid_sources[0x39]	479	1			T7	2		T102	1		T112	1
valid_sources[0x3a]	230	1			T7	1		T11	1		T102	1
valid_sources[0x3b]	145	1			T19	1		T115	3		T113	1
valid_sources[0x3c]	157	1			T114	2		T14	47		T118	3
valid_sources[0x3d]	147	1			T17	1		T12	2		T115	2
valid_sources[0x3e]	106	1			T17	1		T102	1		T115	1
valid_sources[0x3f]	154	1			T7	5		T102	1		T19	1
valid_sources[0x40]	151	1			T102	1		T113	4		T119	6
valid_sources[0x41]	119	1			T102	1		T112	4		T113	1
valid_sources[0x42]	128	1			T7	1		T11	3		T61	3
valid_sources[0x43]	161	1			T12	2		T19	1		T112	2
valid_sources[0x44]	122	1			T7	2		T11	4		T114	1
valid_sources[0x45]	102	1			T17	1		T19	2		T115	1
valid_sources[0x46]	255	1			T112	1		T54	3		T15	139
valid_sources[0x47]	104	1			T102	7		T113	2		T117	1
valid_sources[0x48]	250	1			T7	1		T11	3		T82	2
valid_sources[0x49]	134	1			T7	1		T43	9		T115	1
valid_sources[0x4a]	129	1			T102	1		T112	2		T14	3
valid_sources[0x4b]	386	1			T7	2		T9	1		T102	1
valid_sources[0x4c]	134	1			T102	2		T112	1		T113	2
valid_sources[0x4d]	690	1			T7	3		T43	26		T19	3
valid_sources[0x4e]	157	1			T7	4		T102	1		T31	1
valid_sources[0x4f]	120	1			T7	5		T112	2		T113	6
valid_sources[0x50]	220	1			T102	2		T12	1		T19	2
valid_sources[0x51]	99	1			T102	3		T31	5		T112	1
valid_sources[0x52]	241	1			T112	1		T82	1		T15	107
valid_sources[0x53]	175	1			T7	2		T31	4		T113	3
valid_sources[0x54]	83	1			T33	1		T115	1		T112	4
valid_sources[0x55]	92	1			T102	1		T33	1		T112	1
valid_sources[0x56]	146	1			T10	22		T17	1		T11	2
valid_sources[0x57]	273	1			T112	1		T117	1		T14	172
valid_sources[0x58]	103	1			T7	1		T11	1		T102	1
valid_sources[0x59]	155	1			T102	1		T36	53		T113	2
valid_sources[0x5a]	112	1			T12	1		T113	1		T119	1
valid_sources[0x5b]	83	1			T102	2		T113	1		T117	1
valid_sources[0x5c]	160	1			T43	4		T112	1		T113	1
valid_sources[0x5d]	158	1			T7	3		T15	1		T119	2
valid_sources[0x5e]	104	1			T33	1		T115	4		T114	5
valid_sources[0x5f]	267	1			T7	1		T113	5		T54	1
valid_sources[0x60]	239	1			T7	1		T11	2		T102	2
valid_sources[0x61]	186	1			T113	2		T119	4		T120	3
valid_sources[0x62]	104	1			T7	1		T17	2		T115	4
valid_sources[0x63]	120	1			T7	1		T115	1		T112	1
valid_sources[0x64]	113	1			T7	2		T102	1		T31	1
valid_sources[0x65]	604	1			T7	1		T17	1		T102	4
valid_sources[0x66]	145	1			T102	1		T43	1		T113	1
valid_sources[0x67]	300	1			T17	1		T11	4		T43	21
valid_sources[0x68]	154	1			T7	1		T102	1		T114	4
valid_sources[0x69]	642	1			T17	1		T18	1		T112	2
valid_sources[0x6a]	127	1			T20	4		T11	1		T102	1
valid_sources[0x6b]	269	1			T7	5		T102	2		T33	8
valid_sources[0x6c]	140	1			T7	1		T43	16		T113	1
valid_sources[0x6d]	122	1			T17	1		T19	2		T112	2
valid_sources[0x6e]	117	1			T7	1		T17	2		T13	1
valid_sources[0x6f]	90	1			T11	3		T12	1		T112	1
valid_sources[0x70]	771	1			T17	1		T11	2		T102	1
valid_sources[0x71]	1237	1			T112	3		T113	3		T14	108
valid_sources[0x72]	158	1			T112	2		T14	48		T15	1
valid_sources[0x73]	201	1			T102	1		T115	1		T117	1
valid_sources[0x74]	158	1			T11	1		T112	1		T14	15
valid_sources[0x75]	178	1			T8	1		T102	2		T112	1
valid_sources[0x76]	135	1			T102	1		T115	2		T112	1
valid_sources[0x77]	147	1			T8	2		T17	1		T102	2
valid_sources[0x78]	313	1			T12	1		T112	3		T113	1
valid_sources[0x79]	254	1			T10	71		T17	2		T11	1
valid_sources[0x7a]	115	1			T7	2		T17	1		T11	1
valid_sources[0x7b]	287	1			T102	1		T15	186		T61	11
valid_sources[0x7c]	158	1			T18	2		T11	1		T102	3
valid_sources[0x7d]	114	1			T7	1		T19	1		T115	2
valid_sources[0x7e]	136	1			T17	1		T102	3		T115	1
valid_sources[0x7f]	178	1			T12	1		T19	3		T33	15
valid_sources[0x80]	181	1			T102	1		T19	4		T114	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10613

1

T6

3

T7

24

T8

2

values[0x0]

all_enables

biggest_size

12994

1

T14

2560

T15

4220

T16

2467

values[0x1]

all_enables

biggest_size

13025

1

T14

2588

T15

4105

T16

2576

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8659	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

46525

1

T1

1

T3

2

T6

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16069	1			T1	1		T5	1		T6	15
values[0x0]	18702	1			T2	1		T3	3		T27	3
values[0x1]	20413	1			T27	4		T28	8		T35	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5723	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

49461

1

T1

1

T3

2

T6

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	158	1			T17	9		T13	2		T31	1
valid_sources[0x01]	248	1			T14	9		T15	62		T121	4
valid_sources[0x02]	129	1			T14	27		T15	4		T122	1
valid_sources[0x03]	132	1			T36	2		T14	14		T15	6
valid_sources[0x04]	434	1			T14	24		T15	142		T123	1
valid_sources[0x05]	207	1			T14	19		T15	1		T124	1
valid_sources[0x06]	274	1			T22	1		T37	1		T14	28
valid_sources[0x07]	168	1			T36	2		T14	21		T125	2
valid_sources[0x08]	107	1			T14	15		T15	3		T25	1
valid_sources[0x09]	198	1			T82	1		T14	36		T15	4
valid_sources[0x0a]	126	1			T117	1		T14	19		T15	2
valid_sources[0x0b]	123	1			T31	1		T14	20		T126	1
valid_sources[0x0c]	195	1			T82	2		T68	18		T14	17
valid_sources[0x0d]	220	1			T24	2		T14	31		T125	1
valid_sources[0x0e]	119	1			T18	4		T14	33		T15	3
valid_sources[0x0f]	120	1			T27	2		T14	28		T46	9
valid_sources[0x10]	137	1			T127	1		T14	16		T15	3
valid_sources[0x11]	348	1			T11	3		T36	19		T14	21
valid_sources[0x12]	305	1			T14	25		T15	13		T16	129
valid_sources[0x13]	131	1			T14	24		T128	1		T129	1
valid_sources[0x14]	184	1			T37	1		T23	2		T14	28
valid_sources[0x15]	115	1			T37	1		T14	27		T15	3
valid_sources[0x16]	664	1			T14	23		T15	234		T122	2
valid_sources[0x17]	147	1			T14	24		T15	5		T130	3
valid_sources[0x18]	226	1			T117	1		T14	41		T131	16
valid_sources[0x19]	153	1			T11	1		T31	1		T14	36
valid_sources[0x1a]	171	1			T14	7		T15	3		T132	32
valid_sources[0x1b]	129	1			T82	1		T14	13		T55	1
valid_sources[0x1c]	286	1			T17	1		T14	30		T15	2
valid_sources[0x1d]	224	1			T14	31		T15	105		T133	1
valid_sources[0x1e]	189	1			T37	1		T31	2		T36	11
valid_sources[0x1f]	283	1			T117	5		T14	35		T15	104
valid_sources[0x20]	191	1			T14	26		T15	4		T134	1
valid_sources[0x21]	180	1			T82	2		T14	22		T15	5
valid_sources[0x22]	336	1			T31	1		T14	19		T15	158
valid_sources[0x23]	105	1			T20	8		T66	2		T14	15
valid_sources[0x24]	372	1			T17	1		T127	7		T14	22
valid_sources[0x25]	170	1			T82	1		T14	33		T15	4
valid_sources[0x26]	192	1			T82	1		T14	15		T15	3
valid_sources[0x27]	283	1			T23	1		T127	1		T14	36
valid_sources[0x28]	185	1			T14	31		T15	11		T135	3
valid_sources[0x29]	166	1			T14	27		T15	2		T125	2
valid_sources[0x2a]	274	1			T117	1		T14	18		T15	194
valid_sources[0x2b]	201	1			T31	1		T14	24		T15	3
valid_sources[0x2c]	275	1			T13	1		T14	29		T15	123
valid_sources[0x2d]	509	1			T14	27		T15	364		T136	1
valid_sources[0x2e]	141	1			T14	13		T15	27		T122	1
valid_sources[0x2f]	538	1			T31	1		T14	29		T15	370
valid_sources[0x30]	183	1			T14	21		T15	41		T137	16
valid_sources[0x31]	129	1			T14	26		T15	12		T138	9
valid_sources[0x32]	264	1			T139	1		T14	23		T15	90
valid_sources[0x33]	93	1			T40	1		T14	24		T15	2
valid_sources[0x34]	137	1			T14	31		T15	2		T130	4
valid_sources[0x35]	126	1			T14	29		T15	3		T56	1
valid_sources[0x36]	174	1			T82	2		T14	10		T15	1
valid_sources[0x37]	99	1			T13	1		T14	9		T140	1
valid_sources[0x38]	246	1			T14	42		T15	118		T125	2
valid_sources[0x39]	449	1			T13	1		T14	26		T15	1
valid_sources[0x3a]	256	1			T13	1		T27	1		T14	15
valid_sources[0x3b]	145	1			T9	18		T14	14		T15	6
valid_sources[0x3c]	117	1			T23	1		T117	1		T14	28
valid_sources[0x3d]	140	1			T2	1		T14	34		T15	5
valid_sources[0x3e]	140	1			T8	1		T14	25		T141	5
valid_sources[0x3f]	140	1			T14	23		T15	1		T45	42
valid_sources[0x40]	464	1			T14	28		T15	114		T124	1
valid_sources[0x41]	187	1			T11	4		T14	23		T56	1
valid_sources[0x42]	429	1			T14	23		T15	2		T122	1
valid_sources[0x43]	181	1			T83	1		T14	18		T15	7
valid_sources[0x44]	160	1			T14	17		T16	20		T142	1
valid_sources[0x45]	269	1			T31	1		T14	22		T15	146
valid_sources[0x46]	111	1			T14	28		T15	1		T134	1
valid_sources[0x47]	148	1			T17	4		T117	1		T14	22
valid_sources[0x48]	93	1			T14	10		T15	1		T133	1
valid_sources[0x49]	525	1			T14	24		T15	121		T143	1
valid_sources[0x4a]	197	1			T14	28		T15	50		T59	1
valid_sources[0x4b]	188	1			T37	2		T23	1		T83	1
valid_sources[0x4c]	151	1			T83	1		T14	23		T29	2
valid_sources[0x4d]	327	1			T83	1		T14	27		T15	115
valid_sources[0x4e]	97	1			T37	2		T14	27		T15	7
valid_sources[0x4f]	304	1			T14	19		T15	199		T140	1
valid_sources[0x50]	320	1			T14	17		T15	25		T57	2
valid_sources[0x51]	164	1			T17	1		T14	27		T15	1
valid_sources[0x52]	292	1			T37	1		T24	1		T14	30
valid_sources[0x53]	166	1			T14	20		T15	4		T144	2
valid_sources[0x54]	192	1			T31	1		T14	22		T56	2
valid_sources[0x55]	141	1			T3	3		T31	1		T83	1
valid_sources[0x56]	142	1			T14	14		T15	10		T145	2
valid_sources[0x57]	163	1			T31	1		T14	31		T15	1
valid_sources[0x58]	225	1			T14	44		T15	4		T123	2
valid_sources[0x59]	95	1			T20	1		T37	1		T31	1
valid_sources[0x5a]	282	1			T14	32		T15	141		T133	1
valid_sources[0x5b]	269	1			T14	39		T15	136		T144	1
valid_sources[0x5c]	226	1			T13	1		T31	1		T82	1
valid_sources[0x5d]	231	1			T13	1		T82	2		T14	28
valid_sources[0x5e]	146	1			T14	17		T15	17		T146	22
valid_sources[0x5f]	144	1			T14	29		T15	6		T121	2
valid_sources[0x60]	254	1			T14	16		T15	139		T147	1
valid_sources[0x61]	284	1			T83	2		T14	22		T15	157
valid_sources[0x62]	238	1			T117	1		T14	16		T15	1
valid_sources[0x63]	358	1			T37	1		T117	4		T14	22
valid_sources[0x64]	134	1			T23	1		T35	1		T14	27
valid_sources[0x65]	240	1			T14	28		T15	4		T57	1
valid_sources[0x66]	112	1			T117	2		T14	27		T15	2
valid_sources[0x67]	156	1			T14	10		T148	1		T126	1
valid_sources[0x68]	129	1			T14	50		T145	2		T149	5
valid_sources[0x69]	265	1			T14	16		T15	139		T150	1
valid_sources[0x6a]	175	1			T17	5		T14	26		T15	1
valid_sources[0x6b]	185	1			T13	2		T82	2		T14	18
valid_sources[0x6c]	143	1			T37	2		T14	35		T15	2
valid_sources[0x6d]	150	1			T14	18		T15	1		T123	1
valid_sources[0x6e]	163	1			T14	18		T15	2		T133	1
valid_sources[0x6f]	439	1			T14	19		T15	190		T133	1
valid_sources[0x70]	159	1			T11	3		T14	25		T15	2
valid_sources[0x71]	185	1			T17	2		T20	3		T82	3
valid_sources[0x72]	147	1			T14	23		T30	1		T151	1
valid_sources[0x73]	327	1			T14	28		T15	191		T152	1
valid_sources[0x74]	285	1			T5	1		T83	1		T14	11
valid_sources[0x75]	119	1			T65	6		T14	24		T15	7
valid_sources[0x76]	216	1			T1	1		T31	2		T117	9
valid_sources[0x77]	289	1			T14	28		T15	152		T25	2
valid_sources[0x78]	208	1			T11	1		T14	24		T15	2
valid_sources[0x79]	222	1			T20	4		T13	1		T14	23
valid_sources[0x7a]	250	1			T14	29		T133	1		T153	1
valid_sources[0x7b]	245	1			T24	2		T14	31		T145	1
valid_sources[0x7c]	231	1			T14	27		T15	6		T128	1
valid_sources[0x7d]	117	1			T32	1		T14	21		T15	6
valid_sources[0x7e]	136	1			T14	25		T15	9		T56	1
valid_sources[0x7f]	167	1			T14	15		T15	65		T136	1
valid_sources[0x80]	158	1			T34	1		T14	9		T15	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10989

1

T1

1

T6

10

T8

9

values[0x0]

all_enables

biggest_size

17819

1

T3

2

T26

1

T28

2

values[0x1]

all_enables

biggest_size

17717

1

T28

1

T35

1

T68

1