Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

81283

1

T7

233

T8

20

T10

291

full_word

42661

1

T6

2

T7

24

T8

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	123624	1			T6	2		T7	257		T8	22
auto[TlIntgErrCmd]	95	1			T48	3		T49	5		T51	9
auto[TlIntgErrData]	114	1			T48	2		T49	4		T51	3
auto[TlIntgErrBoth]	111	1			T48	5		T49	1		T51	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31900

1

T6

2

T7

257

T8

22

auto[1]

92044

1

T14

16236

T15

31158

T16

18269

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20376	1			T7	233		T8	20		T10	291
auto[TlIntgErrNone]	partial	auto[1]	60614	1			T14	10194		T15	21020		T16	12210
auto[TlIntgErrNone]	full_word	auto[0]	11378	1			T6	2		T7	24		T8	2
auto[TlIntgErrNone]	full_word	auto[1]	31256	1			T14	6042		T15	10138		T16	6059
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T49	1		T51	4		T52	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T48	3		T49	4		T51	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T103	2		T107	1		T108	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T109	1		T110	2		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T49	1		T52	3		T104	5
auto[TlIntgErrData]	partial	auto[1]	54	1			T48	2		T49	3		T51	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T104	1		T107	1		T106	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T52	1		T104	2		T109	2
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T48	1		T51	3		T52	5
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T48	4		T49	1		T51	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T103	1		T106	1		T110	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T52	1		T111	1		T108	1