Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 16244 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 21352 1 T1 17 T2 12 T4 10



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 22478 1 T1 124 T2 12 T4 112
values[0x0] 7372 1 T17 1419 T18 2084 T27 1
values[0x1] 7746 1 T17 1410 T18 2273 T27 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 7353 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 30243 1 T1 76 T2 12 T4 62



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 166 1 T10 2 T135 2 T136 4
valid_sources[0x01] 202 1 T4 2 T20 3 T15 1
valid_sources[0x02] 126 1 T1 5 T8 4 T13 1
valid_sources[0x03] 151 1 T47 1 T34 4 T135 2
valid_sources[0x04] 95 1 T10 1 T13 1 T20 3
valid_sources[0x05] 71 1 T135 3 T86 1 T121 1
valid_sources[0x06] 116 1 T4 1 T20 1 T46 1
valid_sources[0x07] 98 1 T47 1 T135 1 T137 1
valid_sources[0x08] 148 1 T9 4 T15 1 T47 1
valid_sources[0x09] 209 1 T4 1 T8 1 T9 3
valid_sources[0x0a] 153 1 T15 2 T46 2 T36 1
valid_sources[0x0b] 123 1 T4 1 T9 1 T15 3
valid_sources[0x0c] 124 1 T5 1 T9 8 T20 1
valid_sources[0x0d] 93 1 T4 1 T9 5 T20 5
valid_sources[0x0e] 163 1 T9 9 T20 5 T14 9
valid_sources[0x0f] 172 1 T19 1 T13 1 T20 11
valid_sources[0x10] 182 1 T4 3 T15 1 T47 1
valid_sources[0x11] 94 1 T47 1 T135 3 T138 1
valid_sources[0x12] 264 1 T8 18 T9 7 T10 2
valid_sources[0x13] 140 1 T4 1 T5 1 T10 1
valid_sources[0x14] 104 1 T20 2 T36 1 T139 21
valid_sources[0x15] 207 1 T9 9 T13 1 T46 1
valid_sources[0x16] 142 1 T4 1 T14 6 T15 2
valid_sources[0x17] 108 1 T10 1 T13 1 T20 3
valid_sources[0x18] 88 1 T9 1 T20 1 T14 5
valid_sources[0x19] 106 1 T9 1 T15 2 T34 2
valid_sources[0x1a] 137 1 T47 1 T135 3 T87 18
valid_sources[0x1b] 115 1 T9 1 T20 3 T15 1
valid_sources[0x1c] 262 1 T9 4 T10 2 T15 1
valid_sources[0x1d] 107 1 T4 1 T8 1 T34 2
valid_sources[0x1e] 249 1 T10 1 T46 1 T47 2
valid_sources[0x1f] 142 1 T8 11 T13 1 T34 1
valid_sources[0x20] 149 1 T1 32 T4 1 T5 4
valid_sources[0x21] 96 1 T15 1 T135 1 T138 2
valid_sources[0x22] 112 1 T135 1 T120 2 T136 2
valid_sources[0x23] 130 1 T20 11 T15 1 T46 1
valid_sources[0x24] 92 1 T10 1 T47 2 T135 1
valid_sources[0x25] 84 1 T9 1 T46 1 T36 1
valid_sources[0x26] 99 1 T4 3 T15 3 T36 1
valid_sources[0x27] 119 1 T20 5 T46 1 T36 1
valid_sources[0x28] 187 1 T1 15 T4 1 T5 1
valid_sources[0x29] 199 1 T10 3 T20 9 T15 2
valid_sources[0x2a] 93 1 T4 1 T15 2 T137 2
valid_sources[0x2b] 151 1 T4 2 T15 1 T33 1
valid_sources[0x2c] 149 1 T1 6 T4 2 T9 1
valid_sources[0x2d] 143 1 T4 1 T20 8 T34 1
valid_sources[0x2e] 123 1 T4 1 T9 3 T10 1
valid_sources[0x2f] 281 1 T19 1 T20 3 T47 1
valid_sources[0x30] 188 1 T9 6 T20 2 T135 2
valid_sources[0x31] 136 1 T1 17 T4 1 T10 1
valid_sources[0x32] 141 1 T14 2 T15 2 T46 1
valid_sources[0x33] 120 1 T33 1 T135 3 T137 3
valid_sources[0x34] 159 1 T47 1 T34 1 T36 1
valid_sources[0x35] 180 1 T86 1 T136 2 T121 2
valid_sources[0x36] 101 1 T4 1 T9 6 T20 3
valid_sources[0x37] 87 1 T46 1 T36 1 T137 1
valid_sources[0x38] 138 1 T9 2 T10 2 T46 1
valid_sources[0x39] 126 1 T14 8 T47 5 T137 3
valid_sources[0x3a] 149 1 T9 4 T13 1 T20 2
valid_sources[0x3b] 129 1 T1 5 T4 3 T10 1
valid_sources[0x3c] 233 1 T5 2 T9 7 T33 1
valid_sources[0x3d] 138 1 T9 7 T10 1 T20 6
valid_sources[0x3e] 127 1 T4 1 T33 2 T36 2
valid_sources[0x3f] 177 1 T10 1 T13 1 T15 1
valid_sources[0x40] 128 1 T9 13 T135 3 T137 1
valid_sources[0x41] 192 1 T9 1 T20 4 T46 1
valid_sources[0x42] 91 1 T9 5 T33 1 T34 2
valid_sources[0x43] 194 1 T15 1 T135 5 T137 2
valid_sources[0x44] 118 1 T4 2 T13 1 T135 1
valid_sources[0x45] 130 1 T10 1 T46 1 T34 1
valid_sources[0x46] 409 1 T135 2 T86 1 T140 2
valid_sources[0x47] 186 1 T47 1 T48 54 T36 1
valid_sources[0x48] 169 1 T9 5 T47 2 T48 22
valid_sources[0x49] 328 1 T9 3 T20 3 T46 1
valid_sources[0x4a] 93 1 T4 1 T5 1 T10 1
valid_sources[0x4b] 153 1 T20 1 T135 3 T88 14
valid_sources[0x4c] 130 1 T4 1 T8 8 T9 2
valid_sources[0x4d] 219 1 T15 1 T137 1 T120 1
valid_sources[0x4e] 144 1 T1 4 T8 10 T10 1
valid_sources[0x4f] 107 1 T47 1 T36 1 T135 1
valid_sources[0x50] 150 1 T4 2 T135 1 T137 1
valid_sources[0x51] 100 1 T10 1 T88 4 T141 1
valid_sources[0x52] 116 1 T4 2 T36 1 T120 3
valid_sources[0x53] 167 1 T9 1 T13 1 T47 2
valid_sources[0x54] 149 1 T20 2 T34 1 T36 1
valid_sources[0x55] 122 1 T4 1 T20 1 T15 1
valid_sources[0x56] 138 1 T4 1 T10 1 T20 1
valid_sources[0x57] 106 1 T4 1 T46 1 T47 2
valid_sources[0x58] 78 1 T4 1 T10 1 T20 1
valid_sources[0x59] 143 1 T4 2 T36 1 T135 1
valid_sources[0x5a] 118 1 T33 2 T137 1 T120 6
valid_sources[0x5b] 173 1 T4 1 T33 1 T36 1
valid_sources[0x5c] 126 1 T4 1 T14 13 T15 2
valid_sources[0x5d] 269 1 T135 2 T121 1 T141 2
valid_sources[0x5e] 120 1 T4 1 T8 3 T9 2
valid_sources[0x5f] 246 1 T1 3 T9 14 T15 1
valid_sources[0x60] 138 1 T4 2 T5 2 T20 4
valid_sources[0x61] 96 1 T13 1 T20 2 T36 1
valid_sources[0x62] 162 1 T9 2 T20 1 T36 3
valid_sources[0x63] 118 1 T14 17 T15 1 T33 2
valid_sources[0x64] 106 1 T9 6 T10 1 T36 1
valid_sources[0x65] 104 1 T9 3 T10 2 T46 1
valid_sources[0x66] 102 1 T4 1 T9 1 T13 1
valid_sources[0x67] 322 1 T4 1 T9 2 T15 2
valid_sources[0x68] 131 1 T4 1 T9 3 T15 1
valid_sources[0x69] 123 1 T8 1 T9 7 T47 1
valid_sources[0x6a] 129 1 T9 1 T13 1 T34 2
valid_sources[0x6b] 115 1 T4 2 T8 8 T33 1
valid_sources[0x6c] 95 1 T4 2 T9 2 T46 1
valid_sources[0x6d] 87 1 T13 1 T20 3 T15 1
valid_sources[0x6e] 74 1 T10 1 T135 1 T121 1
valid_sources[0x6f] 124 1 T20 1 T15 1 T33 1
valid_sources[0x70] 123 1 T1 4 T4 1 T20 5
valid_sources[0x71] 143 1 T5 6 T13 1 T15 1
valid_sources[0x72] 182 1 T15 3 T48 28 T135 3
valid_sources[0x73] 155 1 T8 3 T10 1 T15 1
valid_sources[0x74] 119 1 T4 1 T9 5 T14 1
valid_sources[0x75] 168 1 T8 1 T20 1 T15 1
valid_sources[0x76] 153 1 T4 1 T13 2 T15 2
valid_sources[0x77] 123 1 T9 2 T20 4 T15 1
valid_sources[0x78] 117 1 T34 1 T135 3 T137 4
valid_sources[0x79] 113 1 T4 1 T20 1 T135 2
valid_sources[0x7a] 137 1 T9 2 T20 3 T47 3
valid_sources[0x7b] 130 1 T9 5 T10 1 T13 1
valid_sources[0x7c] 106 1 T135 1 T86 1 T87 4
valid_sources[0x7d] 167 1 T10 1 T46 1 T135 4
valid_sources[0x7e] 163 1 T13 1 T20 1 T135 2
valid_sources[0x7f] 104 1 T4 1 T20 3 T47 1
valid_sources[0x80] 102 1 T9 1 T13 1 T20 10



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 6767 1 T1 17 T2 12 T4 10
values[0x0] all_enables biggest_size 7285 1 T17 1407 T18 2063 T54 27
values[0x1] all_enables biggest_size 7300 1 T17 1320 T18 2135 T54 25


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 7415 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 29854 1 T1 25 T2 8 T3 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 11791 1 T1 48 T2 19 T3 1
values[0x0] 12234 1 T25 2 T26 6 T12 8
values[0x1] 13244 1 T25 1 T26 5 T12 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5071 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 32198 1 T1 29 T2 11 T3 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 131 1 T31 1 T114 2 T142 2
valid_sources[0x01] 115 1 T143 1 T17 15 T144 1
valid_sources[0x02] 140 1 T14 1 T42 6 T109 2
valid_sources[0x03] 120 1 T38 1 T145 1 T146 4
valid_sources[0x04] 138 1 T2 1 T147 1 T148 1
valid_sources[0x05] 138 1 T149 1 T150 1 T17 19
valid_sources[0x06] 132 1 T88 32 T143 2 T151 1
valid_sources[0x07] 133 1 T2 1 T136 1 T150 1
valid_sources[0x08] 134 1 T1 1 T12 1 T114 1
valid_sources[0x09] 106 1 T42 1 T146 1 T148 1
valid_sources[0x0a] 135 1 T5 3 T148 2 T142 1
valid_sources[0x0b] 227 1 T136 3 T152 1 T145 1
valid_sources[0x0c] 158 1 T153 1 T154 3 T17 11
valid_sources[0x0d] 143 1 T146 1 T150 1 T17 13
valid_sources[0x0e] 141 1 T145 1 T155 1 T156 1
valid_sources[0x0f] 155 1 T38 1 T147 1 T157 1
valid_sources[0x10] 110 1 T6 1 T158 3 T145 1
valid_sources[0x11] 154 1 T19 2 T145 1 T143 1
valid_sources[0x12] 163 1 T37 1 T41 1 T42 5
valid_sources[0x13] 134 1 T41 2 T159 1 T160 1
valid_sources[0x14] 138 1 T16 3 T14 2 T113 1
valid_sources[0x15] 117 1 T149 1 T152 1 T148 1
valid_sources[0x16] 136 1 T152 1 T157 1 T161 1
valid_sources[0x17] 184 1 T145 1 T17 9 T53 1
valid_sources[0x18] 210 1 T34 1 T145 1 T146 1
valid_sources[0x19] 118 1 T74 1 T75 12 T162 1
valid_sources[0x1a] 96 1 T163 1 T44 1 T45 3
valid_sources[0x1b] 134 1 T1 2 T152 1 T147 1
valid_sources[0x1c] 149 1 T158 2 T114 1 T45 1
valid_sources[0x1d] 143 1 T74 1 T111 1 T148 1
valid_sources[0x1e] 167 1 T2 1 T19 1 T46 2
valid_sources[0x1f] 159 1 T1 2 T45 2 T164 1
valid_sources[0x20] 147 1 T19 1 T158 1 T109 1
valid_sources[0x21] 194 1 T14 1 T145 1 T17 17
valid_sources[0x22] 141 1 T145 1 T148 1 T161 1
valid_sources[0x23] 147 1 T37 1 T145 1 T44 6
valid_sources[0x24] 125 1 T113 1 T114 1 T17 15
valid_sources[0x25] 101 1 T17 12 T165 1 T18 11
valid_sources[0x26] 103 1 T33 3 T136 2 T145 1
valid_sources[0x27] 151 1 T1 3 T157 1 T145 2
valid_sources[0x28] 143 1 T19 1 T41 1 T145 2
valid_sources[0x29] 131 1 T109 6 T161 1 T23 1
valid_sources[0x2a] 151 1 T136 1 T157 1 T17 19
valid_sources[0x2b] 108 1 T14 2 T34 4 T69 2
valid_sources[0x2c] 143 1 T166 4 T17 16 T66 3
valid_sources[0x2d] 191 1 T152 1 T147 1 T142 4
valid_sources[0x2e] 102 1 T146 1 T142 1 T143 2
valid_sources[0x2f] 117 1 T156 2 T17 12 T165 1
valid_sources[0x30] 134 1 T167 2 T142 2 T143 2
valid_sources[0x31] 167 1 T168 1 T152 1 T17 24
valid_sources[0x32] 153 1 T1 1 T69 2 T136 1
valid_sources[0x33] 120 1 T43 7 T52 3 T151 2
valid_sources[0x34] 183 1 T150 1 T17 8 T165 1
valid_sources[0x35] 171 1 T87 1 T148 2 T17 7
valid_sources[0x36] 131 1 T41 1 T152 1 T17 17
valid_sources[0x37] 101 1 T19 1 T114 1 T146 1
valid_sources[0x38] 148 1 T21 28 T167 1 T44 2
valid_sources[0x39] 137 1 T149 1 T169 1 T145 2
valid_sources[0x3a] 199 1 T145 1 T114 1 T170 13
valid_sources[0x3b] 164 1 T166 2 T43 7 T151 1
valid_sources[0x3c] 156 1 T1 1 T19 1 T14 2
valid_sources[0x3d] 115 1 T171 1 T136 1 T113 1
valid_sources[0x3e] 121 1 T14 1 T33 1 T74 1
valid_sources[0x3f] 117 1 T140 1 T172 1 T17 11
valid_sources[0x40] 127 1 T14 2 T136 1 T173 4
valid_sources[0x41] 120 1 T17 21 T174 1 T175 2
valid_sources[0x42] 168 1 T26 11 T33 1 T176 32
valid_sources[0x43] 127 1 T1 1 T41 1 T146 1
valid_sources[0x44] 175 1 T149 1 T42 1 T114 2
valid_sources[0x45] 137 1 T22 6 T158 2 T152 1
valid_sources[0x46] 122 1 T19 1 T147 1 T145 1
valid_sources[0x47] 152 1 T146 1 T148 1 T143 1
valid_sources[0x48] 112 1 T2 1 T33 1 T177 1
valid_sources[0x49] 159 1 T49 1 T140 1 T156 6
valid_sources[0x4a] 178 1 T33 1 T157 2 T109 3
valid_sources[0x4b] 145 1 T87 1 T89 16 T42 1
valid_sources[0x4c] 159 1 T14 2 T46 1 T136 1
valid_sources[0x4d] 204 1 T7 1 T33 2 T148 1
valid_sources[0x4e] 127 1 T46 1 T157 6 T151 3
valid_sources[0x4f] 124 1 T167 1 T114 1 T178 3
valid_sources[0x50] 129 1 T17 19 T18 26 T27 4
valid_sources[0x51] 184 1 T33 1 T156 1 T52 1
valid_sources[0x52] 122 1 T38 1 T140 4 T142 1
valid_sources[0x53] 195 1 T136 1 T145 1 T156 1
valid_sources[0x54] 127 1 T33 1 T113 1 T143 2
valid_sources[0x55] 95 1 T1 1 T2 1 T74 1
valid_sources[0x56] 185 1 T34 3 T136 2 T156 3
valid_sources[0x57] 137 1 T1 8 T157 2 T145 2
valid_sources[0x58] 127 1 T33 1 T136 1 T74 1
valid_sources[0x59] 140 1 T136 1 T179 1 T151 1
valid_sources[0x5a] 127 1 T33 2 T145 2 T143 1
valid_sources[0x5b] 160 1 T46 1 T145 3 T142 4
valid_sources[0x5c] 147 1 T12 1 T33 1 T136 2
valid_sources[0x5d] 147 1 T167 1 T113 1 T142 1
valid_sources[0x5e] 149 1 T167 1 T154 1 T161 2
valid_sources[0x5f] 150 1 T150 1 T151 1 T172 1
valid_sources[0x60] 168 1 T14 1 T152 1 T145 2
valid_sources[0x61] 88 1 T145 1 T150 1 T17 10
valid_sources[0x62] 125 1 T19 1 T33 1 T145 1
valid_sources[0x63] 152 1 T156 1 T148 1 T179 1
valid_sources[0x64] 155 1 T152 1 T134 5 T180 32
valid_sources[0x65] 145 1 T147 2 T44 2 T156 1
valid_sources[0x66] 119 1 T158 1 T145 1 T146 1
valid_sources[0x67] 127 1 T52 1 T161 1 T17 11
valid_sources[0x68] 180 1 T2 1 T19 1 T134 3
valid_sources[0x69] 138 1 T14 4 T87 1 T148 1
valid_sources[0x6a] 135 1 T38 2 T152 1 T157 1
valid_sources[0x6b] 289 1 T140 1 T156 1 T17 11
valid_sources[0x6c] 127 1 T14 1 T33 1 T181 1
valid_sources[0x6d] 118 1 T14 2 T22 2 T34 1
valid_sources[0x6e] 130 1 T17 6 T182 1 T183 5
valid_sources[0x6f] 112 1 T16 1 T156 1 T142 1
valid_sources[0x70] 130 1 T14 2 T46 4 T34 1
valid_sources[0x71] 140 1 T33 2 T167 1 T153 2
valid_sources[0x72] 123 1 T19 1 T17 10 T66 1
valid_sources[0x73] 111 1 T134 1 T142 1 T172 1
valid_sources[0x74] 145 1 T1 6 T184 2 T17 16
valid_sources[0x75] 171 1 T14 1 T30 1 T87 3
valid_sources[0x76] 98 1 T5 3 T14 3 T153 1
valid_sources[0x77] 177 1 T1 1 T46 2 T87 2
valid_sources[0x78] 300 1 T37 1 T145 1 T148 1
valid_sources[0x79] 113 1 T167 1 T114 1 T52 5
valid_sources[0x7a] 263 1 T161 2 T17 17 T185 1
valid_sources[0x7b] 149 1 T136 1 T143 1 T172 1
valid_sources[0x7c] 143 1 T136 1 T152 1 T134 3
valid_sources[0x7d] 117 1 T37 2 T87 5 T186 1
valid_sources[0x7e] 128 1 T40 2 T44 2 T151 1
valid_sources[0x7f] 123 1 T40 4 T52 1 T23 2
valid_sources[0x80] 119 1 T43 3 T109 2 T151 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 6977 1 T1 25 T2 8 T3 1
values[0x0] all_enables biggest_size 11472 1 T25 2 T26 1 T12 1
values[0x1] all_enables biggest_size 11405 1 T26 1 T37 1 T38 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%